CN116669526A - MRAM memory cell, writing method, reading method and preparation method thereof - Google Patents
MRAM memory cell, writing method, reading method and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/10—Magnetoresistive devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/01—Manufacture or treatment
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application belongs to the technical field of memory devices, and particularly relates to an MRAM memory cell, a writing method, a reading method and a preparation method thereof. The memory cell comprises a substrate, a first electrode, a ferroelectric layer, a magnetic tunnel junction, a pinning layer and a second electrode which are sequentially stacked; the magnetic tunnel junction comprises a free layer, a tunneling layer and a pinned layer, wherein the free layer is an antiferromagnetic structure layer, and the antiferromagnetic structure layer has perpendicular magnetic anisotropy; the memory cell further comprises a voltage regulating device for changing the magnetization state of the free layer. The application realizes the writing of the MRAM memory cell by utilizing the magnetization state transition of the free layer under the action of the electric field, thereby not only reducing the power consumption of the device, but also reducing the problem of burning damage of the device caused by high current density and improving the service life of the memory device.
Description
Technical Field
The application belongs to the technical field of memory devices, and particularly relates to an MRAM memory cell, a writing method, a reading method and a preparation method thereof.
Background
Magnetic random access memory (MARM) accomplishes data storage by changing the magnetization direction of the free magnetic layer relative to the pinned layer to form different magnetoresistive states corresponding to the parallel and anti-parallel states, respectively. MARM has advantages of high-speed reading and writing, high integration, low power consumption, almost unlimited number of erasures, and the like, and is thus considered as one of candidates for next-generation memory devices.
However, to achieve the magnetization direction switching of the free magnetic layer, a large current is usually required, which tends to increase the power consumption of the memory device, while in the large background of high density memory, the size of the memory cell must be small, which would expose the conductive line to a large current density, and further tend to burn out the cross line to damage the MRAM.
Disclosure of Invention
The application aims to at least solve the problems of increased power consumption, shortened service life of a memory device and the like caused by the fact that the existing high-density memory unit needs to use larger current density to realize magnetization inversion of a free magnetic layer.
The aim is achieved by the following technical scheme:
in a first aspect, the present application provides an MRAM memory cell, including a substrate, a first electrode, a ferroelectric layer, a magnetic tunnel junction, a pinning layer, and a second electrode, which are stacked in order;
the magnetic tunnel junction comprises a free layer, a tunneling layer and a pinned layer;
the free layer is an antiferromagnetic structure layer, and the antiferromagnetic structure layer has perpendicular magnetic anisotropy;
the memory cell further comprises a voltage regulating device for changing the magnetization state of the free layer.
The memory unit enables the ferroelectric layer to generate an electric field through the voltage regulating device, the electric field is used for changing the magnetization state of the free layer and realizing information writing, write current density can be reduced, power consumption of the device is reduced, and service life of the device is prolonged.
In some embodiments of the application, the voltage regulating device comprises an electrode disposed between the first electrode and the free layer and a voltage V1, the voltage V1 causing the ferroelectric layer to generate an electric field and for changing the magnetization state of the free layer. The voltage regulating device includes an electrode disposed between the first electrode and the free layer and applying a voltage V1 to generate an electric field for changing a magnetization state of the free layer.
In some embodiments of the present application, the antiferromagnetic structure layer comprises a first ferromagnetic layer, a second ferromagnetic layer, and a first spacer layer between the first ferromagnetic layer and the second ferromagnetic layer, and the first ferromagnetic layer and the second ferromagnetic layer are perpendicular magnetic anisotropies.
In some embodiments of the application, a transition layer is provided between the ferroelectric layer and the free layer.
In some embodiments of the present application, the transition layer is used to buffer match the ferroelectric layer, and the transition layer is an oxide layer.
In some embodiments of the application, a second spacer layer is disposed between the pinned layer and the pinned layer.
In a second aspect, the present application provides a writing method of the MRAM memory cell in the first aspect, where the writing method includes:
acquiring a writing instruction of the storage unit;
applying a voltage to the ferroelectric layer according to the instruction to generate an electric field for changing a magnetization state of the free layer;
acquiring a first resistance value of the free layer according to the magnetization state;
and finishing the writing operation of the memory cell according to the first resistance value.
In a third aspect, the present application provides a method for reading the MRAM memory cell according to the first aspect, where the method includes:
acquiring a reading instruction of the storage unit;
applying a current signal to the free layer according to the instruction to obtain a second resistance value of the free layer;
and finishing the reading operation of the memory cell according to the second resistance value.
In a fourth aspect, the present application provides a method for preparing an MRAM memory cell, the method comprising:
providing a substrate;
sequentially forming a first electrode and a ferroelectric layer on one side of the substrate;
forming a free layer, a tunneling layer, a pinned layer, a pinning layer and a second electrode on the surface of the ferroelectric layer;
an electrode is provided between the first electrode and the free layer and a voltage V1 is applied, and an electrode is provided between the first electrode and the second electrode and a voltage V2 is applied. According to the preparation method, on the premise of reducing the write current density of the device, the complexity of the integrated process of the device is reduced, and the device is convenient to integrate.
In some embodiments of the present application, the first electrode and ferroelectric layer are formed as follows:
forming a first electrode on one side of the substrate by adopting a sputtering method;
depositing and growing a ferroelectric layer on the surface of the first electrode;
growing a TiN layer on the surface of the ferroelectric layer by adopting a sputtering method;
high-temperature annealing treatment;
the TiN layer is etched away.
The beneficial effects of the technical scheme disclosed by the application are mainly shown as follows:
1. the MRAM memory cell designed by the present application can reduce the write current density by providing an electrode between the first electrode and the free layer and applying a voltage V1 to cause the ferroelectric layer to generate an electric field for changing the magnetization state of the free layer and realizing the writing of information, for example, compared with a device not applying the present principles, the write current density of the present application can be reduced from pJ-level power consumption to fJ-level, thereby realizing the technical effects of reducing the device power consumption and improving the device lifetime.
2. The preparation method of the MRAM memory cell reduces the complexity of the device integration process and facilitates the device integration.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
FIG. 1 schematically illustrates a schematic diagram of magnetization state transitions of an MRAM memory cell according to an embodiment of the application; wherein, FIG. 1A shows that the non-applied voltage is in an antiferromagnetic state, and FIG. 1B shows that the non-applied voltage is changed into a ferromagnetic state;
fig. 2 schematically shows a schematic structure of a memory cell according to an embodiment of the present application;
FIG. 3 schematically illustrates a process flow diagram of a memory cell according to an embodiment of the application;
fig. 4 schematically shows a process flow diagram of a memory cell according to an embodiment of the application.
The reference numerals in the drawings are as follows:
100. a substrate; 200. a first electrode; 300. a ferroelectric layer; 400. a transition layer; 500. a free layer; 600. a tunneling layer; 700. a pinned layer; 800. a second isolation layer; 900. pinning the layer; 1000. a second electrode;
510. a first ferromagnetic layer; 520. a first isolation layer; 530. a second ferromagnetic layer;
2000. a protective layer; 3000. an ethyl orthosilicate layer;
4000-1, metal electrode; 4000-2, metal electrode; 4000-3, metal electrode; 4000-4, metal electrode.
Detailed Description
In the prior art, a traditional magnetic random access memory consists of a free layer, a pinned layer and a pinning layer, and is positioned at the vertical intersection of a word line and a bit line, and a magnetic field is generated through the current magnetic induction effect on the word line and the bit line in the writing process, so that the magnetization direction of the free layer is turned over; the magnetization directions of the free layer and the fixed layer are the same to realize low magnetic resistance, and the magnetization directions are opposite to realize high magnetic resistance. MRAM determines whether stored data is 0 or 1 by detecting the level of magnetoresistance. Because a large current is required to turn the magnetization direction of the free layer, the power consumption of the memory device is easily increased, and in the large background of high-density memory, the size of the memory cell must be small, which makes the wire face a large current density, and the burning cross line is easily caused to damage the MRAM.
In order to reduce the energy consumption of the whole device and improve the service life of the device, a thicker ferroelectric material is usually required to be introduced by adopting the magnetization inversion mode of the magnetic free layer in the tunneling junction by using the voltage. In the prior art, an artificial antiferromagnetic device is also disclosed, which uses an electric field to regulate and control the magnetization of the free layer and the pinned layer, and the relative orientation of the magnetization of the free layer and the pinned layer is directly switched by combining current to realize data writing, wherein the magnetization conversion principle of the artificial antiferromagnetic device is as shown in fig. 1. The method can reduce the write current density and realize the technical purpose of saving energy consumption, but the prior art mainly discusses in principle, and is not explored in terms of preparation and specific implementation modes of devices.
In order to solve the technical problems, the application provides an MRAM memory cell, a writing method, a reading method and a preparation method thereof, and the memory cell designed by the application not only reduces the power consumption of devices, but also reduces the problem of burning damage of the devices caused by high current density, improves the service life of the memory devices, and is convenient for device integration.
The first aspect of the present application for achieving the above technical effects provides an MRAM memory cell, which includes a substrate, a first electrode, a ferroelectric layer, a magnetic tunnel junction, a pinning layer, and a second electrode that are stacked in order; wherein the magnetic tunnel junction comprises a free layer, a tunneling layer, and a pinned layer; the free layer is an antiferromagnetic structure layer having perpendicular magnetic anisotropy; the magnetic anisotropy is determined by the structure of the layers within the antiferromagnetic structure layer. The memory cell further comprises a voltage regulating device for changing the magnetization state of the free layer.
In some embodiments, the voltage regulating device includes an electrode disposed between the first electrode and the free layer and applying a voltage V1 to generate an electric field for changing a magnetization state of the free layer.
When an electrode is arranged between the first electrode and the free layer and a voltage V1 is applied, the ferroelectric layer positioned at one side of the first electrode generates an external electric field, and the external electric field acts on the free layer to enable the antiferromagnetic state of the antiferromagnetic structure layer of the free layer to be converted into a ferromagnetic state, and after the external electric field is removed, the ferromagnetic state of the antiferromagnetic structure layer is annealed to the antiferromagnetic state again, namely, the conversion between the antiferromagnetic state and the ferromagnetic state is realized through electric field regulation, and then, the relative magnetization directions between the free layer with the antiferromagnetic structure layer and the pinning layer are utilized to realize data writing and reading.
In some embodiments, the antiferromagnetic structure layer comprises a first ferromagnetic layer, a second ferromagnetic layer, and a first spacer layer between the first ferromagnetic layer and the second ferromagnetic layer, and the first ferromagnetic layer and the second ferromagnetic layer are magnetically anisotropic in a vertical plane.
The antiferromagnetic structure layer is a stacked structure formed by a first ferromagnetic layer, a first isolation layer and a second ferromagnetic layer, wherein the magnetization direction of the first ferromagnetic layer or the second ferromagnetic layer is perpendicularly directed out of plane or parallel to in plane, and the first isolation layer is used for controlling the magnetization direction between the first ferromagnetic layer and the second ferromagnetic layer not to be affected by each other.
The materials of the first or second ferromagnetic layers include, but are not limited to Fe, co, coFe, ni, coCrPt, coFeB, (Co/Ni) p 、(Co/Pd) m 、(Co/Pt) n M, n, p refer to the number of repetitions of the multi-layer stack.
The first spacer layer is a non-magnetic spacer material including, but not limited to, any of Nb, ta, cr, mo, W, re, ru, os, rh, ir, pt, cu, ag or Au.
In some embodiments, a transition layer is provided between the ferroelectric layer and the free layer.
The ferroelectric layer is a Hf-based ferroelectric material including, but not limited to, metal oxides having ferroelectric polarization properties, such as HfZrO, etc., wherein HfZrO has the ferroelectric properties of the target brick, as a preferred material of the present application.
In some embodiments, a transition layer is used to buffer the matching ferroelectric layer. The transition layer is arranged between the ferroelectric layer and the free layer of the magnetic tunnel junction, the transition layer is an oxide layer, and the oxide layer material comprises, but is not limited to, mgO.
In some embodiments, a second spacer layer is disposed between the pinned layer and the pinned layer.
The second isolation layer is used for controlling the magnetic moment direction of the pinning layer to be free from the influence of the magnetization state of the antiferromagnetic structure layer.
The second spacer layer is also a non-magnetic spacer material, including but not limited to any of Nb, ta, cr, mo, W, re, ru, os, rh, ir, pt, cu, ag or Au, which remains the same as the material of the first spacer layer described above.
In some embodiments, the tunneling layer is an oxide layer, the oxide layer material including, but not limited to, mgO.
In some embodiments, the pinned layer is a magnetic layer, the magnetic layer material including, but not limited to Fe, co, coFe, ni, coCrPt, coFeB, (Co/Ni) p 、(Co/Pd) m 、(Co/Pt) n M, n, p refer to the number of repetitions of the multi-layer stack.
In some embodiments, the pinning layer employs a manganese-based antiferromagnetic material comprising IrMn or FeMn or a multilayer film artificial antiferromagnetic material including, but not limited to Fe, co, coFe, ni, coCrPt, coFeB, (Co/Ni) p 、(Co/Pd) m 、(Co/Pt) n M, n, p refer to the number of repetitions of the multi-layer stack.
In some embodiments, the first electrode and the second electrode include, but are not limited to, titanium nitride.
In some embodiments, the substrate is a material conventional in the art, preferably a silicon wafer.
The present application provides a writing method for the MRAM memory cell, which includes: acquiring a writing instruction of a storage unit; applying a voltage to the ferroelectric layer according to the instruction to generate an electric field for changing a magnetization state of the free layer; acquiring a first resistance value of the free layer according to the magnetization state; and finishing the writing operation on the memory cell according to the first resistance value. The writing mode can reduce writing current density and power consumption of the device.
A third aspect of the present application to achieve the above technical effects is to provide a reading method of the MRAM memory cell, where the reading method includes: acquiring a reading instruction of a storage unit; applying a current signal to the free layer according to the instruction to obtain a second resistance value of the free layer; and finishing the reading operation on the memory cell according to the second resistance value.
The fourth aspect of the present application for achieving the above technical effects is to provide a method for manufacturing the MRAM memory cell, which includes: providing a substrate; sequentially forming a first electrode and a ferroelectric layer on one side of a substrate; forming a free layer, a tunneling layer, a pinned layer, a pinning layer and a second electrode on the surface of the ferroelectric layer; an electrode is provided between the first electrode and the free layer and a voltage V1 is applied, and an electrode is provided between the first electrode and the second electrode and a voltage V2 is applied.
The preparation method has high operation feasibility and is beneficial to improving the integration level of the device.
In some embodiments, the first electrode and the ferroelectric layer are formed as follows:
forming a first electrode on one side of the substrate by adopting a sputtering method; depositing and growing a ferroelectric layer on the surface of the first electrode; growing a TiN layer on the surface of the ferroelectric layer by adopting a sputtering method; high-temperature annealing treatment; the TiN layer is etched away.
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Example 1
As can be seen from fig. 2, the MRAM memory cell includes a substrate 100, a first electrode 200, a ferroelectric layer 300, a transition layer 400, a free layer 500, a tunneling layer 600, a pinned layer 700, a second isolation layer 800, a pinned layer 900 and a second electrode 1000, which are stacked in this order, wherein the free layer 500 is an antiferromagnetic structure layer, and the antiferromagnetic structure layer is a stacked structure formed by a first ferromagnetic layer 510, a first isolation layer 520 and a second ferromagnetic layer 530, and the first isolation layer 520 is used for controlling the magnetization direction between the first ferromagnetic layer 510 and the second ferromagnetic layer 560 not to be affected by each other.
Meanwhile, the tunneling layer 600, the pinned layer 700, the first spacer 800, the pinning layer 900, and the second electrode 1000 constitute a pillar for maintaining its magnetic properties by using in-plane magnetic anisotropy. A protective layer 2000 is also formed around the periphery of the pillars, the protective layer material including, but not limited to, silicon nitride.
Further, an ethyl orthosilicate layer 3000 is formed around the outer periphery of the cell, and the ethyl orthosilicate layer is used to wrap the cell and isolate the electrode wires in the later stage from each other, and mainly serves as a protective layer for insulation.
As can be seen from fig. 2, the memory cell further includes four metal electrodes 4000-1, 4000-2, 4000-3 and 4000-4, respectively, one end of the metal electrode 4000-1 is connected to the first electrode 200, one end of the metal electrode 4000-2 is connected to the free layer 500, a voltage V1 is applied between the metal electrode 4000-1 and the metal electrode 4000-2 to generate an electric field for changing the magnetization state of the free layer 500 to achieve information writing of the memory cell, in addition, one end of the metal electrode 4000-3 is connected to the second electrode 1000, one end of the metal electrode 4000-4 is connected to the first electrode 200, and a voltage V2 is applied between the metal electrode 4000-3 and the metal electrode 4000-4 to apply a current signal to the free layer 500 to complete information reading of the memory cell.
The method for manufacturing the MRAM memory cell having the above structure will be described in detail with reference to fig. 3 and 4:
(a) Providing a silicon wafer, and removing a natural oxide layer on the surface of the silicon wafer by adopting a standard cleaning process of a buffer oxide etching solution to obtain a substrate 100;
(b) A layer of first electrode 200 is grown by a magnetron sputtering process, and TiN is selected to be grown as the first electrode 200 in the embodiment; growing a layer of HfZrO with ferroelectric polarization characteristics on the first electrode 200 by using deionized water and a precursor of Hf as a ferroelectric layer 300 by using an atomic deposition technology, and growing a layer of TiN on the ferroelectric layer 300 by continuing a magnetron sputtering process; wherein the precursor of Hf includes, but is not limited to, any form conventional in the art;
(c) High temperature annealing treatment, and etching to eliminate TiN on the surface of the ferroelectric layer 300;
(d) Sequentially growing a transition layer 400, a first ferromagnetic layer 510, a first isolation layer 520, a second ferromagnetic layer 530, a tunneling layer 600, a pinned layer 700, a second isolation layer 800 and a pinning layer 900 on the surface of a ferroelectric layer 300 by utilizing a magnetron sputtering process, placing a sample in a nitrogen environment for rapid annealing treatment, inducing the ferroelectric layer 300 to form a ferroelectric phase, forming a perpendicular magnetic anisotropy by a free layer 500, and continuously growing a second electrode 1000 on the surface, wherein the second electrode 1000 is also a layer of TiN;
(e) Coating photoresist on the surface of the second electrode 1000;
(f) In combination with the photolithography process, the tunneling layer 600, the pinned layer 700, the first isolation layer 800, the pinning layer 900, and the second electrode 1000 form a pillar for maintaining the magnetic properties thereof by using in-plane magnetic anisotropy, and are etched from the surface of the second electrode 1000 toward the direction of the first electrode 200 to the surface of the free layer 500.
(g) A silicon nitride protective layer 2000 is also formed on the periphery of the columnar body;
(h) Etching from the surface of the silicon nitride protective layer 2000 to the surface of the first electrode 200 in the direction of the substrate 100 in combination with the photolithography process;
(i) Etching the first electrode 200 to the surface of the substrate 100 in combination with a photolithography process;
(j) An ethyl orthosilicate layer 3000 is further formed on the outer periphery of the unit;
(k) Chemically and mechanically polishing the ethyl orthosilicate layer 3000 and the SiN layer 109 on top of the cell;
(l) Coating photoresist on the top of the unit and forming three through holes by combining a photoetching process; each through hole is respectively abutted to the surface of the first electrode 200, the surface of the second ferromagnetic layer 530 and the surface of the first electrode 200;
(m) performing metal filling formation on the via hole through a deposition process, forming a metal electrode 4000-1, a metal electrode 4000-2, and a metal electrode 4000-3, respectively, wherein one end of the metal electrode 4000-1 is connected to the first electrode 200, one end of the metal electrode 4000-2 is connected to the free layer 500, V1 is applied between the metal electrode 4000-1 and the metal electrode 4000-2 to generate an electric field for changing a magnetization state of the free layer 500 to achieve information writing of the memory cell, and furthermore, one end of the metal electrode 4000-3 is connected to the second electrode 1000, one end of the metal electrode 4000-4 is connected to the first electrode 200, and V2 is applied between the metal electrode 4000-3 and the metal electrode 4000-4 to apply a current signal to the free layer 500 to complete information reading of the memory cell.
Therefore, the MRAM memory cell designed in the present application can reduce the write current density by providing an electrode between the first electrode and the free layer and applying a voltage V1 to cause the ferroelectric layer to generate an electric field for changing the magnetization state of the free layer and realizing writing of information, wherein the write current density of the present application can be reduced from pJ level power consumption to fJ level, reducing device power consumption and achieving the technical object of improving the device lifetime, compared to a device not applying the present principles. In addition, the preparation method of the MRAM memory cell reduces the complexity of the device integration process and facilitates the device integration.
It is to be understood that the terminology used herein is for the purpose of describing particular example embodiments only, and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," "includes," "including," and "having" are inclusive and therefore specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order described or illustrated, unless an order of performance is explicitly stated. It should also be appreciated that additional or alternative steps may be used.
The present application is not limited to the above-mentioned embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present application are intended to be included in the scope of the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.
Claims (10)
1. An MRAM memory cell is characterized by comprising a substrate, a first electrode, a ferroelectric layer, a magnetic tunnel junction, a pinning layer and a second electrode which are sequentially stacked;
the magnetic tunnel junction comprises a free layer, a tunneling layer and a pinned layer;
the free layer is an antiferromagnetic structure layer, and the antiferromagnetic structure layer has perpendicular magnetic anisotropy;
the memory cell further comprises a voltage regulating device for changing the magnetization state of the free layer.
2. The memory cell of claim 1, wherein the voltage regulating device comprises an electrode disposed between the first electrode and the free layer and a voltage V1, the voltage V1 causing the ferroelectric layer to generate an electric field and for changing a magnetization state of the free layer.
3. The memory cell of claim 1, wherein the antiferromagnetic structure layer comprises a first ferromagnetic layer, a second ferromagnetic layer, and a first spacer layer between the first ferromagnetic layer and the second ferromagnetic layer, and wherein the first ferromagnetic layer and the second ferromagnetic layer are perpendicular magnetic anisotropies.
4. A memory cell according to claim 1, 2 or 3, characterized in that a transition layer is provided between the ferroelectric layer and the free layer.
5. The memory cell of claim 4 wherein the transition layer is for buffer matching the ferroelectric layer, the transition layer being an oxide layer.
6. The memory cell of claim 1 or 2 or 3 or 5, wherein a second spacer layer is provided between the pinned layer and the pinned layer.
7. A method of writing an MRAM memory cell according to any of claims 1 to 6, wherein the method of writing comprises:
acquiring a writing instruction of the storage unit;
applying a voltage to the ferroelectric layer according to the instruction to generate an electric field for changing a magnetization state of the free layer;
acquiring a first resistance value of the free layer according to the magnetization state;
and finishing the writing operation of the memory cell according to the first resistance value.
8. A method of reading an MRAM memory cell according to any one of claims 1 to 6, comprising:
acquiring a reading instruction of the storage unit;
applying a current signal to the free layer according to the instruction to obtain a second resistance value of the free layer;
and finishing the reading operation of the memory cell according to the second resistance value.
9. A method for fabricating an MRAM memory cell, the method comprising:
providing a substrate;
sequentially forming a first electrode and a ferroelectric layer on one side of the substrate;
forming a free layer, a tunneling layer, a pinned layer, a pinning layer and a second electrode on the surface of the ferroelectric layer;
an electrode is provided between the first electrode and the free layer and a voltage V1 is applied, and an electrode is provided between the first electrode and the second electrode and a voltage V2 is applied.
10. The method of claim 9, wherein the first electrode and ferroelectric layer are formed as follows:
forming a first electrode on one side of the substrate by adopting a sputtering method;
depositing and growing a ferroelectric layer on the surface of the first electrode;
growing a TiN layer on the surface of the ferroelectric layer by adopting a sputtering method;
high-temperature annealing treatment;
the TiN layer is etched away.
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