CN116669423A - Flash memory device and forming method thereof - Google Patents

Flash memory device and forming method thereof Download PDF

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Publication number
CN116669423A
CN116669423A CN202210140396.4A CN202210140396A CN116669423A CN 116669423 A CN116669423 A CN 116669423A CN 202210140396 A CN202210140396 A CN 202210140396A CN 116669423 A CN116669423 A CN 116669423A
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semiconductor substrate
layer
gate oxide
oxide layer
etching
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李志国
王军
隋振超
刘玉丽
李越
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Zhongxin North Integrated Circuit Manufacturing Beijing Co ltd
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Zhongxin North Integrated Circuit Manufacturing Beijing Co ltd
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Priority to CN202210140396.4A priority Critical patent/CN116669423A/en
Publication of CN116669423A publication Critical patent/CN116669423A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

The application provides a flash memory device and a forming method thereof, wherein the flash memory device comprises: a gate oxide layer, a gate electrode layer and a hard mask layer are sequentially formed on the surface of the semiconductor substrate; the first groove penetrates through the hard mask layer, the gate electrode layer and the gate oxide layer and extends into the semiconductor substrate, wherein the junction of the gate oxide layer and the semiconductor substrate is in an arc shape. In the technical scheme of the application, the junction between the gate oxide layer and the semiconductor substrate is exposed when the first groove is formed, then the sacrificial layer is used for rounding the junction between the gate oxide layer and the semiconductor substrate and further protecting the junction between the gate oxide layer and the semiconductor substrate, and the junction between the gate oxide layer and the semiconductor substrate is not damaged when the etching is continued along the first groove, so that the junction between the semiconductor substrate and the gate oxide layer is in an arc shape, and the problem of electric leakage between adjacent active areas or between the active areas and the control grid is solved.

Description

Flash memory device and forming method thereof
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a flash memory device and a method for forming the same.
Background
The memory cells of a NAND flash memory device are subject to interference from surrounding adjacent memory cells during operation. The size scaling further exacerbates the disturb effect as the technology nodes of 20nm and below are entered during NAND flash. Especially, when the tip of the active region presents a sharp angle shape, leakage interference is more obvious, and there are two types of failures that generally reduce reliability: leakage between adjacent active regions and leakage between the active regions and the control gate.
Therefore, there is a need to provide a more efficient and reliable solution.
Disclosure of Invention
The application provides a flash memory device and a forming method thereof, which can enable the junction of a semiconductor substrate and a gate oxide layer to be in an arc shape and solve the problem of electric leakage between adjacent active areas or between the active areas and a gate layer.
One aspect of the present application provides a method for forming a flash memory device, including: providing a semiconductor substrate, wherein a gate oxide layer, a gate electrode layer and a hard mask layer are sequentially formed on the surface of the semiconductor substrate; etching the hard mask layer, the gate layer and the gate oxide layer to the semiconductor substrate to form a first groove; forming a sacrificial layer on the side wall and the bottom of the first groove and the hard mask layer, wherein the sacrificial layer covers the junction of the gate oxide layer and the semiconductor substrate; etching the sacrificial layer and the semiconductor substrate to a set depth of the semiconductor substrate along the first groove, and just exposing the junction of the gate oxide layer and the semiconductor substrate, wherein the junction of the gate oxide layer and the semiconductor substrate is in an arc shape.
In some embodiments of the present application, a method of forming a first trench in the semiconductor substrate by etching the hard mask layer, the gate layer, and the gate oxide layer includes: forming an etching stop layer on the surface of the hard mask layer; forming a patterned mask layer on the surface of the etching stop layer, wherein the patterned mask layer defines the position of the first groove; and etching the etching stop layer, the hard mask layer, the gate layer and the gate oxide layer into the semiconductor substrate by taking the patterned mask layer as a mask to form the first groove.
In some embodiments of the application, the etch stop layer has a thickness of 1500 to 1800 angstroms.
In some embodiments of the present application, etching process parameters for etching the etch stop layer, the hard mask layer, the gate oxide layer to form a first trench in the semiconductor substrate include: the etching gas includes CF 4 The method comprises the steps of carrying out a first treatment on the surface of the The etching time is 20 to 40 seconds.
In some embodiments of the present application, after etching the sacrificial layer and the semiconductor substrate along the first trench to a set depth of the semiconductor substrate and just exposing an interface between the gate oxide layer and the semiconductor substrate, the method further includes: and removing the etching stop layer.
In some embodiments of the application, the first trench bottom is 100 to 200 angstroms below the gate oxide layer bottom surface.
In some embodiments of the present application, the method of forming a sacrificial layer on the first trench sidewall and bottom and the hard mask layer comprises a TEOS process.
In some embodiments of the application, the sacrificial layer has a thickness of 30 to 80 angstroms.
In some embodiments of the present application, the method of etching the sacrificial layer and the semiconductor substrate along the first trench to a set depth of the semiconductor substrate and just exposing the junction of the gate oxide layer and the semiconductor substrate is anisotropic etching.
In some embodiments of the present application, etching the sacrificial layer and the semiconductor substrate along the first trench to a set depth of the semiconductor substrate and just exposing an interface of the gate oxide layer and the semiconductor substrate includes: the etchant includes Cl 2 The method comprises the steps of carrying out a first treatment on the surface of the The etching time is 90 to 150 seconds.
In some embodiments of the present application, after etching the sacrificial layer and the semiconductor substrate along the first trench to a set depth of the semiconductor substrate and just exposing an interface between the gate oxide layer and the semiconductor substrate, an aspect ratio of the first trench is 14:1 or more.
Another aspect of the present application also provides a flash memory device, including: a gate oxide layer, a gate electrode layer and a hard mask layer are sequentially formed on the surface of the semiconductor substrate; the first groove penetrates through the hard mask layer, the gate electrode layer and the gate oxide layer and extends into the semiconductor substrate, wherein the junction of the gate oxide layer and the semiconductor substrate is in an arc shape.
In some embodiments of the application, the aspect ratio of the first trench is 14:1 or more.
The application provides a flash memory device and a forming method thereof, wherein the junction between a gate oxide layer and a semiconductor substrate is exposed when a first groove is formed, then the junction between the gate oxide layer and the semiconductor substrate is rounded by using a sacrificial layer, and the junction between the gate oxide layer and the semiconductor substrate is further protected, the junction between the gate oxide layer and the semiconductor substrate is not damaged when the first groove is etched, and the junction between the semiconductor substrate and the gate oxide layer can be made to be arc, so that the problem of electric leakage between adjacent active areas or between the active areas and a control grid is solved.
Drawings
The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals refer to like structure throughout the several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description only and are not intended to limit the scope of the application, as other embodiments may equally well accomplish the inventive intent in this disclosure. It should be understood that the drawings are not to scale.
Wherein:
FIGS. 1-3 are schematic diagrams illustrating steps in a method for forming a flash memory device;
FIG. 4 is a schematic diagram of the edge corner morphology of a semiconductor substrate interfacing with a gate oxide layer in some flash memory device structures;
fig. 5 to 10 are schematic structural views illustrating steps in a method for forming a flash memory device according to an embodiment of the application;
fig. 11 is a schematic structural diagram of a junction between a gate oxide layer and a semiconductor substrate in a flash memory device structure according to an embodiment of the present application.
Detailed Description
The following description provides specific applications and requirements of the application to enable any person skilled in the art to make and use the application. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
The technical scheme of the application is described in detail below with reference to the examples and the accompanying drawings.
Unlike the logic period process in which the active region is formed first, then the corners of the active region are rounded and filled with isolating material, then the gate oxide is deposited and the polysilicon gate is etched, the NAND flash memory device is formed by depositing the gate oxide and the floating gate on the substrate or the epitaxial layer first and then the active region is formed.
Fig. 1-3 are schematic structural diagrams illustrating steps in a method for forming a flash memory device.
Referring to fig. 1, a semiconductor substrate 100 is provided, and a gate oxide layer 110, a gate layer 120, and a hard mask layer 130 are sequentially formed on the surface of the semiconductor substrate 100.
Referring to fig. 2, the hard mask layer 130, the gate layer 120, the gate oxide layer 110 are etched to the surface of the semiconductor substrate 100 to form a first trench 140.
Referring to fig. 3, the semiconductor substrate 100 is continuously etched along the first trench 140 to a set depth of the semiconductor substrate 100.
The main problems of this technique are: the first trench 140 stops on the surface of the semiconductor substrate 100 in the step shown in fig. 2, and the semiconductor substrate 100 is etched further along the first trench 140 in the subsequent step shown in fig. 3. However, in the process shown in fig. 3, on the one hand, the semiconductor substrate 100 is etched in the horizontal direction due to the difference in the etching selectivity between the gate oxide layer 110 and the semiconductor substrate 100 when the longitudinal etching is performed, and the gate oxide layer 110 is not etched; on the other hand, in order to meet the requirement of the operation breakdown voltage of the NAND flash memory device, the shallow trench of the active area (i.e., the set depth) needs to reach a depth of more than 2000 angstroms, and during the long-term vertical etching process, the top corner of the active area (i.e., the position indicated by the dashed line box 130 in fig. 3, i.e., the interface between the gate oxide layer 110 and the semiconductor substrate 100) is continuously sharpened, which results in the aggravation of the mutual interference between the active areas of the memory cell. Moreover, since the final aspect ratio of the first trench 140 exceeds 14:1, it is difficult to find a suitable process to round the active region corners without affecting the floating gate and isolation structure sidewall morphology.
Fig. 4 is a schematic diagram of the edge corner morphology of a semiconductor substrate interfacing with a gate oxide layer in some flash memory device structures. Fig. 4 shows an enlarged view of the location of the dashed box 150 in fig. 3.
Referring to fig. 4, due to the long-time longitudinal etching and the difference in etching selectivity between the gate oxide layer 110 and the semiconductor substrate 100, the portion where the semiconductor substrate 100 and the gate oxide layer 110 meet forms a sharp arc-shaped corner, affecting the device performance.
In view of the above, the present application provides a flash memory device and a method for forming the same, in which the junction between the gate oxide layer and the semiconductor substrate is exposed when the first trench is formed, and then the junction between the gate oxide layer and the semiconductor substrate is rounded by using the sacrificial layer, and the junction between the gate oxide layer and the semiconductor substrate is further protected, and the junction between the gate oxide layer and the semiconductor substrate is not damaged when the subsequent etching is continued along the first trench, so that the junction between the semiconductor substrate and the gate oxide layer is in a circular arc shape, and the problem of leakage between adjacent active regions or between the active regions and the control gate is solved.
Fig. 5 to 10 are schematic structural diagrams illustrating steps in a method for forming a flash memory device according to an embodiment of the application. The method for forming the flash memory device according to the embodiment of the application is described in detail below with reference to the accompanying drawings.
Referring to fig. 5, a semiconductor substrate 200 is provided, and a gate oxide layer 210, a gate layer 220, and a hard mask layer 230 are sequentially formed on the surface of the semiconductor substrate 200.
In some embodiments of the present application, the material of the semiconductor substrate 200 comprises (i) an elemental semiconductor, such as silicon or germanium, etc.; (ii) A compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or the like; (iii) Alloy semiconductors such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, gallium indium phosphide, or the like; or (iv) combinations of the above. In addition, the semiconductor substrate 200 may be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of the present application, the semiconductor substrate 200 may be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic).
In some embodiments of the present application, the material of the gate oxide layer 210 is silicon oxide. The method for forming the gate oxide layer 210 includes a thermal oxidation process, a chemical vapor deposition process, a physical vapor deposition process, or the like.
In some embodiments of the present application, the material of the gate layer 220 comprises polysilicon. The method of forming the gate layer 220 includes a chemical vapor deposition process or a physical vapor deposition process, etc.
In some embodiments of the present application, the material of the hard mask layer 230 comprises silicon nitride. The method of forming the hard mask layer 230 includes a chemical vapor deposition process or a physical vapor deposition process, etc. The hard mask layer 230 is used to protect the gate layer 220 during subsequent processing.
Referring to fig. 6 to 8, the hard mask layer 230, the gate layer 220, the gate oxide layer 210 are etched to form a first trench 260 in the semiconductor substrate 200.
Referring to fig. 6, an etch stop layer 240 is formed on the surface of the hard mask layer 230. The etch stop layer 240 is used as an etch stop layer in forming the patterned mask layer to improve the patterning accuracy of the patterned mask layer.
In some embodiments of the present application, the etch stop layer 240 has a thickness of 1500 to 1800 angstroms, such as 1550 angstroms, 1600 angstroms, 1650 angstroms, 1700 angstroms, 1750 angstroms, or the like. In conventional processes, the etch stop layer is about 1000 angstroms thick. In the technical scheme of the application, since the etching amount is more than that in the conventional process when the first groove is formed by subsequent etching, the thickness of the etching stop layer 240 is increased by a proper amount to meet the etching requirement.
In some embodiments of the present application, the material of the etch stop layer 240 comprises silicon nitride. The method of forming the etch stop layer 240 includes a chemical vapor deposition process, a physical vapor deposition process, or the like.
A patterned mask layer 250 is formed on the surface of the etch stop layer 240 as shown in fig. 7, the patterned mask layer 250 defining the location of the first trench.
In some embodiments of the present application, the method of forming the patterned mask layer 250 is, for example, a double exposure process (double patterning). The double exposure process is similar to the process adopted in the conventional process, and is not described herein.
Referring to fig. 8, the etching stop layer 240, the hard mask layer 230, the gate layer 220, and the gate oxide layer 210 are etched using the patterned mask layer 250 as a mask to form the first trench 260 in the semiconductor substrate 200.
In some embodiments of the present application, the patterned mask layer 250 is completely consumed during etching to form the first trench 260. In other embodiments of the present application, after the first trench 260 is etched, the patterned mask layer 250 remains on the surface of the etching stop layer 240, and the patterned mask layer 250 is removed.
In some embodiments of the present application, the etching process parameters for etching the etch stop layer 240, the hard mask layer 230, the gate layer 220, the gate oxide layer 210 to form the first trench 260 in the semiconductor substrate 200 include: the etching gas includes CF 4 The method comprises the steps of carrying out a first treatment on the surface of the Etching time20 to 40 seconds.
In some embodiments of the present application, the bottom of the first trench 260 is 100 to 200 a, such as 120 a, 140 a, 160 a or 180 a, below the bottom surface of the gate oxide layer 210. In a conventional process, the first trench 260 stops at the surface of the semiconductor substrate 200. In the solution of the present application, the first trench 260 extends into the semiconductor substrate 200 to expose the junction between the semiconductor substrate 200 and the gate oxide layer 210, so as to facilitate the subsequent rounding process at the junction between the semiconductor substrate 200 and the gate oxide layer 210 and protect the junction between the semiconductor substrate 200 and the gate oxide layer 210.
Referring to fig. 9, a sacrificial layer 270 is formed on the sidewall and bottom of the first trench 260 and the surface of the etch stop layer 240 on the hard mask layer 230, and the sacrificial layer 270 covers the junction between the gate oxide layer 210 and the semiconductor substrate 200. The sacrificial layer 270 may protect the interface between the semiconductor substrate 200 and the gate oxide layer 210 from being excessively etched in a long-time longitudinal etching so that arc-shaped sharp corners are not formed.
In some embodiments of the present application, the material of the sacrificial layer 270 is silicon oxide.
In some embodiments of the present application, the method of forming the sacrificial layer 270 on the sidewalls and bottom of the first trench 260 and the surface of the etch stop layer 240 on the hard mask layer 230 includes a dry or wet oxidation process, such as a TEOS process. By using this process, on the one hand, silicon oxide is deposited on the side wall and bottom of the first trench 260 and on the surface of the etching stop layer 240 on the hard mask layer 230, and on the other hand, silicon of the semiconductor substrate 200 can be oxidized to form silicon oxide in a small amount, so that the sharp corner portion formed by the etching process at the junction between the semiconductor substrate 200 and the gate oxide layer 210 can be oxidized (i.e. rounded) to further form an arc at the junction between the semiconductor substrate 200 and the gate oxide layer 210.
In other embodiments of the present application, the method of forming the sacrificial layer 270 on the sidewall and bottom of the first trench 260 and the surface of the etch stop layer 240 on the hard mask layer 230 includes a chemical vapor deposition process or a physical vapor deposition process, etc.
In some embodiments of the application, the sacrificial layer 270 has a thickness of 30 to 80 angstroms, such as 40 angstroms, 50 angstroms, 60 angstroms, or 70 angstroms, or the like. The thickness of the sacrificial layer 270 is set to ensure that the sacrificial layer 270 is completely consumed in the horizontal direction right after the subsequent etching is continued along the first trench 260.
Referring to fig. 10, the sacrificial layer 270 and the semiconductor substrate 200 are etched along the first trench 260 to a set depth of the semiconductor substrate 200 and just expose the junction of the gate oxide layer 210 and the semiconductor substrate 200 (indicated by a dotted line box 280), and the junction of the gate oxide layer 210 and the semiconductor substrate 200 (indicated by a dotted line box 280) is in the shape of an arc, that is, at two top corners of the semiconductor substrate 200.
In some embodiments of the present application, the etch stop layer 240 is also completely consumed after etching the sacrificial layer 270 and the semiconductor substrate 200 along the first trench 260 to a set depth of the semiconductor substrate 200 and just exposing the junction of the gate oxide layer 210 and the semiconductor substrate 200 (shown in dashed box 280).
In other embodiments of the present application, the etching stop layer 240 is removed after the sacrificial layer 270 and the semiconductor substrate 200 are etched along the first trench 260 to a set depth of the semiconductor substrate 200 and the etching stop layer 240 remains just after the junction of the gate oxide layer 210 and the semiconductor substrate 200 is exposed (shown in dashed box 280).
In some embodiments of the present application, the method of etching the sacrificial layer 270 and the semiconductor substrate 200 along the first trench 260 to a set depth of the semiconductor substrate 200 and just exposing the junction of the gate oxide layer 210 and the semiconductor substrate 200 (shown by the dashed box 280) is anisotropic etching.
In some embodiments of the present application, the sacrificial layer 270 and the semiconductor substrate 200 are etched along the first trench 260 to a set depth of the semiconductor substrate 200 and just exposing the junction of the gate oxide layer 210 and the semiconductor substrate 200 (dashed line box280) includes: the etchant includes Cl 2 The method comprises the steps of carrying out a first treatment on the surface of the The etching time is 90 to 150 seconds.
In some embodiments of the present application, the aspect ratio of the first trench 260 is 14:1 or more after etching the sacrificial layer 270 and the semiconductor substrate 200 along the first trench 260 to a set depth of the semiconductor substrate 200 and just exposing the junction of the gate oxide layer 210 and the semiconductor substrate 200 (shown by a dashed box 280).
In some embodiments of the present application, the set depth (i.e., the depth of the first trench 260 in the semiconductor substrate 200) is greater than or equal to 2000 angstroms.
In the technical solution of the present application, on the one hand, the sharp corner at the junction between the gate oxide layer 210 and the semiconductor substrate 200 (indicated by the dashed box 280) may be oxidized during the formation of the sacrificial layer 270, so that the junction between the gate oxide layer 210 and the semiconductor substrate 200 (indicated by the dashed box 280) is in a circular arc shape; on the other hand, the sacrificial layer 270 may also protect the junction between the gate oxide layer 210 and the semiconductor substrate 200 (i.e., etched instead of the junction between the gate oxide layer 210 and the semiconductor substrate 200) in the subsequent etching process, so that the junction between the gate oxide layer 210 and the semiconductor substrate 200 (shown by the dashed box 280) is in an arc shape. And further, the problem of active region leakage is solved, and the device performance is improved.
Fig. 11 is a schematic structural diagram of a junction between a gate oxide layer and a semiconductor substrate in a flash memory device structure according to an embodiment of the present application. Fig. 11 shows an enlarged view of the position of the dashed box 280 in fig. 10.
Referring to fig. 11, in the embodiment of the present application, a boundary (indicated by a dashed box 280) between the gate oxide layer 210 and the semiconductor substrate 200 is in a circular arc shape.
According to the method for forming the flash memory device, the junction between the gate oxide layer and the semiconductor substrate is exposed when the first groove is formed, then the sacrificial layer is used for rounding the junction between the gate oxide layer and the semiconductor substrate and further protecting the junction between the gate oxide layer and the semiconductor substrate, the junction between the gate oxide layer and the semiconductor substrate is not damaged when the first groove is etched continuously, the junction between the semiconductor substrate and the gate oxide layer can be made to be circular arcs, and the problem of electric leakage between adjacent active areas or between the active areas and the control grid is solved.
An embodiment of the present application further provides a flash memory device, as shown in fig. 10, including: a semiconductor substrate 200, wherein a gate oxide layer 210, a gate electrode layer 220 and a hard mask layer 230 are sequentially formed on the surface of the semiconductor substrate 200; the first trench 260 penetrates through the hard mask layer 230, the gate layer 220, and the gate oxide layer 210 and extends into the semiconductor substrate 200, wherein a boundary (indicated by a dashed box 280) between the gate oxide layer 210 and the semiconductor substrate 200 is in a circular arc shape.
In some embodiments of the present application, the material of the semiconductor substrate 200 comprises (i) an elemental semiconductor, such as silicon or germanium, etc.; (ii) A compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or the like; (iii) Alloy semiconductors such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, gallium indium phosphide, or the like; or (iv) combinations of the above. In addition, the semiconductor substrate 200 may be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of the present application, the semiconductor substrate 200 may be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic).
In some embodiments of the present application, the material of the gate oxide layer 210 is silicon oxide.
In some embodiments of the present application, the material of the gate layer 220 comprises polysilicon.
In some embodiments of the present application, the material of the hard mask layer 230 comprises silicon nitride. The hard mask layer 230 is used to protect the gate layer 220.
In some embodiments of the application, the aspect ratio of the first trench 260 is 14:1 or more. The first trench 260 is used to form an isolation structure.
In some embodiments of the present application, the first trench 260 has a depth of 2000 angstroms or more in the semiconductor substrate 200.
Fig. 11 is a schematic structural diagram of a junction between a gate oxide layer and a semiconductor substrate in a flash memory device structure according to an embodiment of the present application. Fig. 11 shows an enlarged view of the position of the dashed box 280 in fig. 10.
Referring to fig. 11, in the embodiment of the present application, a boundary (indicated by a dashed box 280) between the gate oxide layer 210 and the semiconductor substrate 200 is in a circular arc shape. Therefore, the problem of active region leakage is solved, and the device performance is improved.
The application provides a flash memory device and a forming method thereof, wherein the junction between a gate oxide layer and a semiconductor substrate is exposed when a first groove is formed, then the junction between the gate oxide layer and the semiconductor substrate is rounded by using a sacrificial layer, and the junction between the gate oxide layer and the semiconductor substrate is further protected, the junction between the gate oxide layer and the semiconductor substrate is not damaged when the first groove is etched, and the junction between the semiconductor substrate and the gate oxide layer can be made to be arc, so that the problem of electric leakage between adjacent active areas or between the active areas and a control grid is solved.
In view of the foregoing, it will be evident to those skilled in the art after reading this disclosure that the foregoing application may be presented by way of example only and may not be limiting. Although not explicitly described herein, those skilled in the art will appreciate that the present application is intended to embrace a variety of reasonable alterations, improvements and modifications to the embodiments. Such alterations, improvements, and modifications are intended to be within the spirit and scope of the exemplary embodiments of the application.
It should be understood that the term "and/or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.
Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means without intermediate elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present application. Like reference numerals or like reference numerals designate like elements throughout the specification.
Furthermore, the present description describes example embodiments with reference to idealized example cross-sectional and/or plan and/or perspective views. Thus, differences from the illustrated shapes, due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

Claims (13)

1. A method of forming a flash memory device, comprising:
providing a semiconductor substrate, wherein a gate oxide layer, a gate electrode layer and a hard mask layer are sequentially formed on the surface of the semiconductor substrate;
etching the hard mask layer, the gate layer and the gate oxide layer to the semiconductor substrate to form a first groove;
forming a sacrificial layer on the side wall and the bottom of the first groove and the hard mask layer, wherein the sacrificial layer covers the junction of the gate oxide layer and the semiconductor substrate;
etching the sacrificial layer and the semiconductor substrate to a set depth of the semiconductor substrate along the first groove, and just exposing the junction of the gate oxide layer and the semiconductor substrate, wherein the junction of the gate oxide layer and the semiconductor substrate is in an arc shape.
2. The method of forming a flash memory device of claim 1, wherein etching the hard mask layer, the gate oxide layer into the semiconductor substrate to form a first trench comprises:
forming an etching stop layer on the surface of the hard mask layer;
forming a patterned mask layer on the surface of the etching stop layer, wherein the patterned mask layer defines the position of the first groove;
and etching the etching stop layer, the hard mask layer, the gate layer and the gate oxide layer into the semiconductor substrate by taking the patterned mask layer as a mask to form the first groove.
3. The method of forming a flash memory device of claim 2, wherein the etch stop layer has a thickness of 1500 to 1800 angstroms.
4. The method of forming a flash memory device of claim 2, wherein etching process parameters for etching the etch stop layer, the hard mask layer, the gate oxide layer to form a first trench in the semiconductor substrate comprise: the etching gas includes CF 4 The method comprises the steps of carrying out a first treatment on the surface of the The etching time is 20 to 40 seconds.
5. The method of forming a flash memory device of claim 2, wherein etching the sacrificial layer and the semiconductor substrate along the first trench to a set depth of the semiconductor substrate and just exposing an interface of the gate oxide layer and the semiconductor substrate further comprises: and removing the etching stop layer.
6. The method of forming a flash memory device of claim 1, wherein a bottom of the first trench is 100 to 200 angstroms below a bottom surface of the gate oxide layer.
7. The method of forming a flash memory device of claim 1, wherein the method of forming a sacrificial layer on the first trench sidewall and bottom and the hard mask layer comprises a TEOS process.
8. The method of forming a flash memory device of claim 1, wherein the sacrificial layer has a thickness of 30 to 80 angstroms.
9. The method of forming a flash memory device of claim 1, wherein etching the sacrificial layer and the semiconductor substrate along the first trench to a set depth of the semiconductor substrate and just exposing an interface of the gate oxide layer and the semiconductor substrate is an anisotropic etch.
10. The method of forming a flash memory device of claim 1, wherein etching the sacrificial layer and the semiconductor substrate along the first trench to a set depth of the semiconductor substrate and just exposing etching process parameters at an interface of the gate oxide layer and the semiconductor substrate comprises: the etchant includes Cl 2 The method comprises the steps of carrying out a first treatment on the surface of the The etching time is 90 to 150 seconds.
11. The method of forming a flash memory device of claim 1, wherein an aspect ratio of the first trench is 14:1 or greater after etching the sacrificial layer and the semiconductor substrate along the first trench to a set depth of the semiconductor substrate and just exposing an interface of the gate oxide layer and the semiconductor substrate.
12. A flash memory device, comprising:
a gate oxide layer, a gate electrode layer and a hard mask layer are sequentially formed on the surface of the semiconductor substrate;
the first groove penetrates through the hard mask layer, the gate electrode layer and the gate oxide layer and extends into the semiconductor substrate, wherein the junction of the gate oxide layer and the semiconductor substrate is in an arc shape.
13. The flash memory device of claim 12, wherein the aspect ratio of the first trench is 14:1 or greater.
CN202210140396.4A 2022-02-16 2022-02-16 Flash memory device and forming method thereof Pending CN116669423A (en)

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