CN116667845A - Phase discriminator, delay phase-locked loop circuit and signal processing method - Google Patents

Abstract

The embodiment of the application provides a phase discriminator, a delay phase-locked loop circuit and a signal processing method, and relates to the technical field of integrated circuits. The phase detector includes: an edge detection circuit and an SR latch, wherein the edge detection circuit is used for sampling a feedback clock signal at the rising edge of an input clock signal and outputting the sampling result of the feedback clock signal to the SR latch; and the SR latch is used for determining an output signal of the output end Q according to the sampling result and the input clock signal. The phase discriminator in the embodiment of the application is provided with the edge detection circuit and the SR latch, so that the phase relation of two input signals can be detected in an edge sampling mode, the judgment of the phase relation is easier, and the influence of a phase discrimination dead zone can be eliminated because the output signal of the phase discriminator is not a periodic pulse signal.

Description

Phase discriminator, delay phase-locked loop circuit and signal processing method

Technical Field

The application relates to the technical field of integrated circuits, in particular to a phase discriminator, a delay phase-locked loop circuit and a signal processing method.

Background

The phase discriminator is a circuit module which is widely used in a high-speed interface chip to complete the clock recovery function. The phase detector in the related art is shown in fig. 1, and is composed of four D flip-flops (FF 1, FF2, FF3, FF 4) and two exclusive or gates (XOR 1, XOR 2), din represents a received random data stream, which is random 0,1, corresponding to two states of low level and high level, respectively. CK is the local clock signal, the duty cycle is 50%, the frequency is equal to the code rate of the data stream, FF1, FF2, FF4 are rising edge samples, and FF3 is a falling edge sample.

For the moment when a certain CK rising edge just finishes, S3 is the data sampled at the moment, S0 and S2 are the sampling results of the data before half a period, and S1 is the sampling result of the last period. When S1 and S2 coincide, it is explained that the rising edge of CK is the optimal sampling point when the falling edge of CK is at the same time as the rising edge of data, since it is farthest from the changing edge of both ends of data, after the falling edge of CK (i.e., the timing of the rising edge of CK by half a cycle), at this time X outputs 0, y outputs 1, indicating clock advance. When S3 and S2 coincide, the changing edge of the data is described as being before the falling edge of CK, and X is output 1 and Y is output 0 at this time, indicating clock hysteresis. The phase detector thus completes the clock phase lead or lag verification process.

However, since the output signal of the phase detector in the related art is a periodic pulse signal, the pulse width and the input signal are proportional to each other in phase difference. When the phase difference of the input signal is too small, the pulse width of the output signal is too small, and a charge pump switch of a later stage may not be opened, so that a phase discrimination dead zone is generated.

Disclosure of Invention

The embodiment of the application provides a phase detector, a delay phase-locked loop circuit and a signal processing method.

According to a first aspect of an embodiment of the present application, there is provided a phase detector, including: an edge detection circuit and an SR latch, wherein,

the edge detection circuit is used for sampling a feedback clock signal at the rising edge of an input clock signal and outputting the sampling result of the feedback clock signal to the SR latch;

the SR latch is used for determining an output signal of the output end Q according to the sampling result of the feedback clock signal and the input clock signal;

wherein the edge detection circuit comprises: a first NAND gate, a second NAND gate, a third NAND gate and a fourth NAND gate, wherein,

the first input end of the first NAND gate is used for receiving the input clock signal, and the second input end of the first NAND gate is connected with the output end of the second NAND gate;

the output end of the first NAND gate is respectively connected with the second input end of the second NAND gate, the second input end of the fourth NAND gate and the setting end of the SR latch;

the first input end of the second NAND gate is respectively connected with the output end of the third NAND gate and the third input end of the fourth NAND gate;

the first input end of the third NAND gate is used for receiving the feedback clock signal, and the second input end of the third NAND gate is connected with the output end of the fourth NAND gate;

the first input end of the fourth NAND gate is used for receiving the input clock signal, and the output end of the fourth NAND gate is also connected with the reset end of the SR latch.

In one possible implementation, the SR latch includes: a fifth NAND gate and a sixth NAND gate, wherein,

the first input end of the fifth NAND gate is the set end of the SR latch, and the second input end of the fifth NAND gate is connected with the output end of the sixth NAND gate;

the first input end of the sixth NAND gate is a reset end of the SR latch, and the second input end of the sixth NAND gate is connected with the output end Q of the fifth NAND gate.

In another possible implementation, the SR latch is specifically configured to:

if the phase of the feedback clock signal lagging behind the input clock signal is determined to be in a first range value based on the sampling result, determining that the output signal of the output end Q is in a low level;

if the sampling result represents that the feedback clock signal lags behind the phase of the input clock signal within a second range value, determining that the output signal of the output end Q is high level;

wherein the first range value is less than the second range value.

According to a second aspect of an embodiment of the present application, there is provided a delay locked loop circuit comprising control logic, a delay line and a phase detector as described in any of the embodiments of the first aspect above, wherein,

the phase discriminator is used for comparing the phase difference of the input clock signal and the feedback clock signal to obtain an output signal, and outputting the output signal to the control logic circuit to serve as an input signal of the control logic circuit;

the control logic circuit is used for determining a delay control signal according to the input signal and outputting the delay control signal to the delay line so as to control the rising edges of the input clock signal and the feedback clock signal to be consistent;

the feedback clock signal is output to the phase detector through the delay line by the input clock signal.

In one possible implementation, the control logic circuit includes a register whose value characterizes the direction of adjustment of the delay control signal.

In another possible implementation, the delay control signal is used to control the number of clock buffers accessing the delay line.

According to a third aspect of an embodiment of the present application, there is provided a clock adjustment circuit including a delay locked loop circuit as described in the second aspect above.

According to a fourth aspect of embodiments of the present application, there is provided a signal processing method, the method comprising:

receiving an input signal of a control logic circuit in a Delay Locked Loop (DLL) circuit;

determining the locking type of the DLL circuit according to the jump type of the input signal and the value of a register in the control logic circuit;

wherein the value of the register characterizes the direction of adjustment of the delay control signal.

In one possible implementation, the determining the lock type of the DLL circuit includes:

if the input signal jumps from low level to high level and the value of the register is a first value, determining that the locking type of the DLL circuit is full period locking;

if the input signal jumps from low level to high level and the value of the register is a second value, determining that the locking type of the DLL circuit is half-cycle locking;

if the input signal jumps from high level to low level and the value of the register is a first value, determining that the locking type of the DLL circuit is half-cycle locking;

if the input signal jumps from high level to low level and the value of the register is a second value, determining that the locking type of the DLL circuit is periodic locking;

wherein the first value characterizes an increasing direction of adjustment of the delay control signal and the second value characterizes a decreasing direction of adjustment of the delay control signal.

In another possible implementation, the method further includes:

an initial value of the delay control signal is set to one half of a maximum delay value.

In the embodiment of the application, the phase detector is provided with the edge detection circuit and the SR latch, so that the phase relation of two input signals can be detected in an edge sampling mode, the judgment of the phase relation is easier, and the influence of a phase detection dead zone can be eliminated because the output signal of the phase detector is not a periodic pulse signal.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings that are required to be used in the description of the embodiments of the present application will be briefly described below.

Fig. 1 is a schematic structural diagram of a phase detector in the related art;

fig. 2 is a schematic structural diagram of a phase detector according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of a phase detector according to a second embodiment of the present application;

FIG. 4 is a schematic diagram showing a phase relationship between an input clock signal and a feedback clock signal according to an embodiment of the present application;

FIG. 5 is a second schematic diagram of a phase relationship between an input clock signal and a feedback clock signal according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of a delay locked loop circuit according to an embodiment of the present application;

fig. 7 is a schematic flow chart of a signal processing method according to an embodiment of the present application;

fig. 8 is a second flowchart of a signal processing method according to an embodiment of the present application.

Description of the drawings:

a 10-phase detector;

11-an edge detection circuit; a 12-SR latch;

111-a first nand gate; 112-a second nand gate; 113-a third nand gate; 114-a fourth nand gate;

121-fifth nand gate; 122-sixth nand gate;

a 30-delay phase locked loop circuit;

31-control logic; 32-delay line.

Detailed Description

Embodiments of the present application are described below with reference to the drawings in the present application. It should be understood that the embodiments described below with reference to the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application, and the technical solutions of the embodiments of the present application are not limited.

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail with reference to the accompanying drawings.

Fig. 1 is a schematic diagram of a phase detector in the related art. As in the phase detector shown in fig. 1, the outputs are all continuous pulse signals, the pulse width being related to the phase difference of the input signals. Therefore, if the duty ratio of the input signal changes, the pulse width output by the phase detector also changes, and the circuit structure of the phase detector is complex, and there is generally a phase detection dead zone, that is, after the phase difference is smaller than a certain value, the output voltage of the phase detector is close to zero. At this time, the phase detector cannot detect a phase difference below a certain limit, thereby affecting the locking accuracy of the DLL circuit.

Aiming at the technical problems in the prior art, the embodiment of the application provides a phase discriminator, a delay phase-locked loop circuit and a signal processing method.

The technical solutions of the embodiments of the present application and technical effects produced by the technical solutions of the present application are described below by describing several exemplary embodiments. It should be noted that the following embodiments may be referred to, or combined with each other, and the description will not be repeated for the same terms, similar features, similar implementation steps, and the like in different embodiments.

Fig. 2 is a schematic structural diagram of a phase detector according to an embodiment of the present application. The phase detector 10 as shown in fig. 2 includes: an edge detection circuit 11 and an SR latch 12.

The edge detection circuit 11 is configured to sample the feedback clock signal fbclk at a rising edge of the input clock signal iclk, and output a sampling result of the feedback clock signal fbclk to the SR latch 12. An SR latch 12 for determining an output signal of the output terminal Q according to a sampling result of the feedback clock signal and the input clock signal iclk.

Fig. 3 is a schematic diagram of a phase detector according to a second embodiment of the present application.

In one possible implementation, as shown in fig. 3, the edge detection circuit 11 includes: the first nand gate 111, the second nand gate 112, the third nand gate 113 and the fourth nand gate 114, wherein a first input terminal of the first nand gate 111 is used for receiving the input clock signal iclk, and a second input terminal is connected to an output terminal of the second nand gate 112. The output terminal of the first nand gate 11 is connected to the second input terminal of the second nand gate 112, the second input terminal of the fourth nand gate 114 and the set terminal of the SR latch, respectively. The first input terminal of the second nand gate 112 is connected to the output terminal of the third nand gate 113 and the third input terminal of the fourth nand gate 114, respectively. The first input terminal of the third nand gate 113 is for receiving the feedback clock signal fbclk, and the second input terminal is connected to the output terminal of the fourth nand gate 114. The first input of the fourth NAND gate 114 is for receiving an input clock signal iclk, and the output is also coupled to the reset of the SR latch.

In this embodiment, the phase relation of the two input signals can be detected by an edge detection circuit and an SR latch provided in the phase detector in an edge sampling manner, so that the judgment of the phase relation is easier, and the influence of the phase detection dead zone can be eliminated because the output signal of the phase detector is not a periodic pulse signal.

Illustratively, the sampling result of the feedback clock signal fbclk may be high or low.

In another possible implementation, as shown in fig. 3, the SR latch 12 includes: a first input end of the fifth nand gate 121 is a set end of the SR latch, and a second input end of the fifth nand gate 121 is connected to an output end of the sixth nand gate 122. The first input terminal of the sixth nand gate 122 is the reset terminal of the SR latch, and the second input terminal is connected to the output terminal Q of the fifth nand gate 121.

That is, the phase detector 10 in the embodiment of the present application may be composed of five two-input nand gates (the first nand gate 111, the second nand gate 112, the third nand gate 113, the fifth nand gate 121, the sixth nand gate 122) and one three-input nand gate (the fourth nand gate 114). A specific connection relationship may be shown in fig. 3, where Sn and Rn are internal signals, when the clock signal iclk=0 is input, sn=1, rn=1, and the output signal Q remains in the original state. The rising edge of the input clock signal iclk triggers a change of the output signal Q, if the feedback clock signal fbclk=1, sn=0, rn=1, the output signal q=1; if the feedback clock signal fbclk=0, sn=1, rn=0, the output signal q=0. I.e. the rising edge of the input clock signal iclk samples the level of the feedback clock signal fbclk, and the level of the output signal Q is the same as the level of the feedback clock signal fbclk. Where "0" characterizes a low level and "1" characterizes a high level.

In another possible implementation, the SR latch 12 is specifically configured to:

if the phase of the feedback clock signal fbclk lagging the input clock signal iclk is determined to be in the first range value based on the sampling result, determining that the output signal of the output end Q is in a low level;

if the sampling result represents that the phase of the feedback clock signal fbclk lagging the input clock signal iclk is in the second range value, determining that the output signal of the output end Q is in a high level;

wherein the first range value is less than the second range value.

Illustratively, the first range of values may be 0 to 180deg and the second range of values may be 180 to 360deg.

Fig. 4 is a schematic diagram showing a phase relationship between an input clock signal and a feedback clock signal according to an embodiment of the present application. As shown in fig. 4, when the feedback clock signal fbclk lags the input clock signal iclk by 0 to 180deg, the output signal q=0 of the phase detector. Where "0" characterizes a low level and "1" characterizes a high level.

Fig. 5 is a schematic diagram showing a phase relationship between an input clock signal and a feedback clock signal according to an embodiment of the present application. As shown in fig. 5, when the feedback clock signal fbclk lags the input clock signal iclk by 180-360 deg., the output signal q=1 of the phase detector. Where "0" characterizes a low level and "1" characterizes a high level.

Embodiments of the present application also provide a delay locked loop circuit (Delay Locked Loop, DLL circuit for short) that may include the phase detector 10 described in any of the above embodiments.

In this embodiment, the DLL circuit is mainly used in a digital circuit for phase delay compensation, clock adjustment. The main principle is to insert a clock buffer (buffer) between the input clock and the output clock, and control the rising edges of the input clock and the feedback clock to be consistent by determining the delay progression through control logic. Compared with the traditional PLL (Phase Locked Loop, phase-locked loop), the DLL circuit has the advantages of high precision, small jitter, insensitivity to power supply noise and the like, and is easy to realize by using a digital circuit mode.

Fig. 6 is a schematic structural diagram of a delay locked loop circuit according to an embodiment of the present application.

In an alternative embodiment, a delay locked loop circuit 30 as shown in fig. 6 includes a phase detector 10, a control logic circuit 31, and a delay line 32. The phase detector 10 is configured to compare a phase difference between an input clock signal and a feedback clock signal to obtain an output signal, and output the output signal to the control logic circuit 31 as an input signal of the control logic circuit 31. And a control logic circuit 31 for determining a delay control signal from the input signal and outputting to the delay line 32 to control the rising edges of the input clock signal and the feedback clock signal to coincide. Wherein the feedback clock signal is output from the input clock signal to the phase detector 10 via the delay line 32.

That is, the phase detector 10 in the DLL circuit compares the phase difference between the input clock signal and the feedback clock signal to obtain a phase discrimination result (lead, lag) which is input to the control logic circuit 31 (which may be implemented by digital control logic) to generate an N-bit binary code (which may be characterized as the delay control signal above), and changes the buffer (or number, quantity) level (or number of buffers) to which the delay line 32 is connected, so that the input clock signal and the feedback clock signal are locked. The control logic 31 may use a dichotomy, i.e. it may find the target binary code faster each time the intermediate value in the adjustment range is taken from the phase discrimination result.

Specifically, in this embodiment, when the output signal Q of the phase detector 10 (i.e., the input signal of the control logic circuit 31) transitions from a low level (characterized by 0) to a high level (characterized by 1), the feedback clock signal fbclk completes half-cycle locking with the input clock signal iclk, at which time the feedback clock signal fbclk is in opposite phase to the input clock signal iclk; when the output signal Q of the phase detector 10 transitions from 1 to 0, the feedback clock signal fbclk completes the full period lock with the input clock signal iclk, at which time the feedback clock signal fbclk is in phase with the input clock signal iclk.

That is, in this embodiment, the control logic circuit 31 judges the phase relationship of the feedback clock signal fbclk and the input clock signal iclk by detecting the transition of the input signal Q.

The control logic 31 preferably completes the half cycle lock. The delay code (code) initial value may be set to half of the delay code maximum value. If q=0, it is explained that the delay of the feedback clock signal fbclk needs to be increased, and the delay code is increased until Q jumps from 0 to 1. If q=1, it is explained that the delay of the feedback clock signal fbclk needs to be reduced, the delay code is reduced until Q jumps from 1 to 0.

However, the DLL circuit is affected by factors such as process, voltage, temperature, etc., and may not be able to complete half-cycle locking, for example, in two possible cases:

1) When the feedback clock signal fbclk lags behind the input clock signal iclk by a small phase (close to 0 deg), q=0 at this time, the delay code should increase, but tuning the delay code to the maximum value still cannot jump Q from 0 to 1;

2) When the feedback clock signal fbclk lags the input clock signal iclk by a large phase (close to 360 deg), where q=1, the delay code should be reduced, but tuning the delay code to a minimum still fails to transition Q from 1 to 0.

When the two special conditions occur, the adjusting direction needs to be changed, so that full-period locking is realized. Thus, a register D for adjusting the direction can be added inside the digital control logic.

In one possible implementation, the control logic 31 comprises a register, the value of which characterizes the direction of adjustment of the delay control signal used to control the number of clock buffers accessing the delay line 32.

For example, the value of register d=1 delay code may be set to increase and the value of register d=0 delay code may be set to decrease. It should be understood that other schemes for taking the value of register D are not excluded.

In summary, in the scheme of the embodiment of the present application, the lock type of the DLL circuit is determined to be half-cycle lock or full-cycle lock by controlling the transition type of the input signal Q of the logic circuit 31 and the value of the register D for adjusting the direction. For details, see the following table:

q initial level	The value of register D	Q hop type	Locking type
				0	0	Jump from 0 to 1	Full cycle lock
0	1	Jump from 0 to 1	Half cycle locking
				1	0	Jump from 1 to 0	Half cycle locking
1	1	Jump from 1 to 0	Full cycle lock

In this embodiment, the delay line 32 may be a variable delay line in the related art, which is not limited by the embodiment of the present application.

The embodiment of the application also provides a clock adjusting circuit which comprises the delay phase-locked loop circuit in the embodiment.

It should be appreciated that in this embodiment, the clock adjustment circuit may also include other devices and/or circuits. The connection relation between the delay phase-locked loop circuit and other devices and/or circuits in the clock adjustment circuit can refer to the circuit structure of the clock adjustment circuit in the related art, and for brevity of description, the embodiments of the present application are not described herein again.

The embodiment of the application also provides a signal processing method. Fig. 7 is a flowchart of a signal processing method according to an embodiment of the present application. The method as shown in fig. 7 includes:

s100, receiving an input signal of a control logic circuit in the Delay Locked Loop (DLL) circuit.

S101, determining the locking type of the DLL circuit according to the jump type of the input signal and the value of a register in the control logic circuit.

Wherein the value of the register characterizes the direction of adjustment of the delay control signal.

In this embodiment, the lock type of the DLL circuit is half-cycle lock or full-cycle lock according to the transition type of the input signal of the control logic circuit in the DLL circuit and the value of the register D representing the adjustment direction of the delay control signal, so that the determination result can be made more accurate.

It should be noted that, because of the existence of the "phase detector dead zone", the phase detector in the prior art cannot detect the phase difference below a certain limit, and further affects the locking precision of the delay locked loop (Delay Locked Loop, DLL) circuit. The phase detector 10 in the above embodiment may be used in the DLL circuit in the above embodiment, and since the edge detection circuit and the SR latch are disposed in the phase detector, the phase relationship between two input signals may be detected in an edge sampling manner, so that the judgment of the phase relationship is easier, and since the output signal of the phase detector is not a periodic pulse signal, the influence of the phase detection dead zone can be eliminated, and further the influence on the locking precision of the DLL circuit is reduced.

In one possible implementation, determining the lock type of the DLL circuit may include at least one of:

if the input signal jumps from low level to high level and the value of the register is the first value, the locking type of the DLL circuit is determined to be full period locking.

If the input signal transitions from a low level to a high level and the value of the register is a second value, the lock type of the DLL circuit is determined to be half-cycle locked.

If the input signal transitions from a high level to a low level and the value of the register is a first value, the lock type of the DLL circuit is determined to be half-cycle locked.

If the input signal jumps from high level to low level and the value of the register is a second value, the locking type of the DLL circuit is determined to be periodic locking.

Wherein the first value characterizes an increasing direction of adjustment of the delay control signal and the second value characterizes a decreasing direction of adjustment of the delay control signal.

Illustratively, if the first value is 1, the second value is 0; alternatively, the first value is 0 and the second value is 1; alternatively, the first value and the second value may have other values, which are not limited in any way in the embodiment of the present application.

In another possible implementation, the method further includes:

the initial value of the delay control signal is set to one half of the maximum delay value.

In this embodiment, in order to more quickly determine the lock type of the DLL circuit, a bisection method may be employed to determine the delay control signal that controls the delay line.

Illustratively, in this embodiment, assume that: delay code is an 8-bit binary unsigned number, denoted as delay [7:0], and delay [7:0] =2' b11111111 is the maximum value, corresponding to decimal 127. The initial value of the delay code may be half of delay [7:0 ].

A specific implementation procedure of a signal processing method in the embodiment of the present application is described in detail below with reference to fig. 8. Fig. 8 is a second flowchart of a signal processing method according to an embodiment of the present application.

The method as shown in fig. 8 includes:

s101, setting the initial value of the delay code to be half of the maximum value.

S102, judging whether the input signal Q of the control logic circuit is at a low level (namely, Q=0; if not (the input signal Q is high level, i.e., q=1), the delay code is reduced and step S104 is performed.

S103, judging whether an input signal Q of the control logic circuit jumps from a low level to a high level (namely, Q=0- > 1; if not, the delay code is reduced and it is determined that the DLL circuit has completed full cycle locking.

S104, judging whether the input signal Q of the control logic circuit jumps from a high level to a low level (namely, Q=1- > 0; if not, the delay code is increased, and the DLL circuit is determined to have completed full cycle locking.

Therefore, in the embodiment of the application, the jump type (q=0- >1, or q=1- > 0) of the input signal of the control logic circuit in the DLL circuit and the change direction of the delay code are combined, so that the locking type of the DLL circuit can be accurately judged to be half-cycle locking or full-cycle locking.

By applying the embodiment of the application, at least the following beneficial effects can be realized:

the DLL circuit provided by the embodiment of the application can detect the phase relation of two input signals in an edge sampling mode due to the adoption of the phase discriminator provided with the edge detection circuit and the SR latch, so that the judgment of the phase relation is easier, and the influence of a phase discrimination dead zone can be eliminated because the output signal of the phase discriminator is not a periodic pulse signal, and the influence on the locking precision of the DLL circuit is further reduced.

Those of skill in the art will appreciate that the various operations, methods, steps in the flow, acts, schemes, and alternatives discussed in the present application may be alternated, altered, combined, or eliminated. Further, other steps, means, or steps in a process having various operations, methods, or procedures discussed herein may be alternated, altered, rearranged, disassembled, combined, or eliminated. Further, steps, measures, schemes in the prior art with various operations, methods, flows disclosed in the present application may also be alternated, altered, rearranged, decomposed, combined, or deleted.

In the description of the present application, directions or positional relationships indicated by words such as "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., are based on exemplary directions or positional relationships shown in the drawings, are for convenience of description or simplification of describing embodiments of the present application, and do not indicate or imply that the devices or components referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application.

The terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.

In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.

In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.

The foregoing is only a part of the embodiments of the present application, and it should be noted that, for those skilled in the art, other similar implementation means based on the technical idea of the present application may be adopted without departing from the technical idea of the solution of the present application, which is also within the protection scope of the embodiments of the present application.

Claims (10)

1. A phase detector, comprising: an edge detection circuit and an SR latch, wherein,

the edge detection circuit is used for sampling a feedback clock signal at the rising edge of an input clock signal and outputting the sampling result of the feedback clock signal to the SR latch;

the SR latch is used for determining an output signal of the output end Q according to the sampling result of the feedback clock signal and the input clock signal;

wherein the edge detection circuit comprises: a first NAND gate, a second NAND gate, a third NAND gate and a fourth NAND gate;

the first input end of the first NAND gate is used for receiving the input clock signal, and the second input end of the first NAND gate is connected with the output end of the second NAND gate;

the output end of the first NAND gate is respectively connected with the second input end of the second NAND gate, the second input end of the fourth NAND gate and the setting end of the SR latch;

the first input end of the second NAND gate is respectively connected with the output end of the third NAND gate and the third input end of the fourth NAND gate;

the first input end of the third NAND gate is used for receiving the feedback clock signal, and the second input end of the third NAND gate is connected with the output end of the fourth NAND gate;

the first input end of the fourth NAND gate is used for receiving the input clock signal, and the output end of the fourth NAND gate is also connected with the reset end of the SR latch.

2. The phase detector of claim 1, wherein the SR latch comprises: a fifth NAND gate and a sixth NAND gate, wherein,

the first input end of the fifth NAND gate is the set end of the SR latch, and the second input end of the fifth NAND gate is connected with the output end of the sixth NAND gate;

the first input end of the sixth NAND gate is a reset end of the SR latch, and the second input end of the sixth NAND gate is connected with the output end Q of the fifth NAND gate.

3. The method according to claim 1 or2, characterized in that the SR latch is in particular for:

if the phase of the feedback clock signal lagging behind the input clock signal is determined to be in a first range value based on the sampling result, determining that the output signal of the output end Q is in a low level;

if the sampling result represents that the feedback clock signal lags behind the phase of the input clock signal within a second range value, determining that the output signal of the output end Q is high level;

wherein the first range value is less than the second range value.

4. A delay locked loop circuit, comprising: control logic, delay line and phase detector according to any of claims 1-3, wherein,

the phase discriminator is used for comparing the phase difference of the input clock signal and the feedback clock signal to obtain an output signal, and outputting the output signal to the control logic circuit to serve as an input signal of the control logic circuit;

the control logic circuit is used for determining a delay control signal according to the input signal and outputting the delay control signal to the delay line so as to control the rising edges of the input clock signal and the feedback clock signal to be consistent;

the feedback clock signal is output to the phase detector through the delay line by the input clock signal.

5. The delay locked loop circuit of claim 4 wherein the control logic comprises a register, a value of the register characterizing an adjustment direction of the delay control signal.

6. A delay locked loop circuit as claimed in claim 4 or 5, wherein the delay control signal is used to control the number of clock buffers accessing the delay line.

7. A clock adjustment circuit, comprising: a delay locked loop circuit as claimed in any one of claims 4 to 6.

8. A method of signal processing, the method comprising:

receiving an input signal of a control logic circuit in a Delay Locked Loop (DLL) circuit;

determining the locking type of the DLL circuit according to the jump type of the input signal and the value of a register in the control logic circuit;

wherein the value of the register characterizes the direction of adjustment of the delay control signal.

9. The method of claim 8, wherein the determining the lock type of the DLL circuit comprises:

if the input signal jumps from low level to high level and the value of the register is a first value, determining that the locking type of the DLL circuit is full period locking;

if the input signal jumps from low level to high level and the value of the register is a second value, determining that the locking type of the DLL circuit is half-cycle locking;

if the input signal jumps from high level to low level and the value of the register is a first value, determining that the locking type of the DLL circuit is half-cycle locking;

if the input signal jumps from high level to low level and the value of the register is a second value, determining that the locking type of the DLL circuit is periodic locking;

wherein the first value characterizes an increasing direction of adjustment of the delay control signal and the second value characterizes a decreasing direction of adjustment of the delay control signal.

10. The method according to claim 8 or 9, characterized in that the method further comprises:

an initial value of the delay control signal is set to one half of a maximum delay value.