CN116667822A

CN116667822A - Ring voltage controlled oscillator, driving method thereof, phase locked loop and electronic equipment

Info

Publication number: CN116667822A
Application number: CN202210157051.XA
Authority: CN
Inventors: 岱晓丹
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-02-21
Filing date: 2022-02-21
Publication date: 2023-08-29
Also published as: WO2023155485A1

Abstract

The embodiment of the application provides a ring voltage controlled oscillator, a driving method thereof, a phase-locked loop and electronic equipment, relates to the technical field of radio frequency, and aims to solve the problem of how to improve the power supply rejection ratio of the ring voltage controlled oscillator. The ring voltage controlled oscillator includes: the grid electrode of the switching tube is coupled with the voltage control end, the first electrode of the switching tube is coupled with the power supply voltage end, and the second electrode of the switching tube is coupled with the oscillating circuit; the input end of the noise amplifying circuit is coupled with the power supply voltage end, and the output end of the noise amplifying circuit is coupled with the substrate electrode of the switching tube; and the oscillating circuit is used for generating a clock signal according to the output of the second pole of the switching tube.

Description

Ring voltage controlled oscillator, driving method thereof, phase locked loop and electronic equipment

Technical Field

The present application relates to the field of radio frequency technologies, and in particular, to a ring voltage controlled oscillator, a driving method thereof, a phase locked loop, and an electronic device.

Background

In recent years, due to the rapid development of microelectronic technology, modern electronic systems are also developed toward high performance and high integration. Taking wireless communication as an example, following the 5G age, higher-speed digital communication services are spreading. The phase-locked loop (phase locked loop, PLL) is a core circuit in the electronic device, and is used for providing a clock signal to the electronic device, and indexes such as spectrum noise, jitter and the like of a signal output by the phase-locked loop directly affect the overall performance of the electronic device. The increasing demands on electronics require that phase locked loops provide high quality clocks at higher speeds.

A voltage-controlled oscillator (VCO) is a core module in a phase-locked loop, and when its control voltage varies within a certain range, its output terminal can obtain a voltage signal with a continuously variable frequency. The mainstream voltage-controlled oscillators are mainly classified into ring voltage-controlled oscillators (ring vco) and inductance capacitance (LC) voltage-controlled oscillators. The LC voltage-controlled oscillator is low in integration level due to the fact that inductance is needed, and is not suitable for application occasions with high integration level requirements. The greatest advantage of ring voltage controlled oscillators over LC voltage controlled oscillators is that they are small in area and can generate multi-phase clocks, but they suffer from slight disadvantages in terms of power supply noise and power consumption.

In the mainstream products, the ring voltage controlled oscillator has two structures of using an N-type transistor and a P-type transistor as a switching tube, and the Power Supply Rejection Ratio (PSRR) of the two structures is poor, that is, the influence of power supply noise on the jitter (jitter) of an output clock is large, so that the performance of electronic equipment is influenced. Therefore, how to increase the power supply rejection ratio of the ring voltage controlled oscillator becomes a hotspot and difficulty in current research.

Disclosure of Invention

The embodiment of the application provides a ring voltage controlled oscillator, a driving method thereof, a phase-locked loop and electronic equipment, which are used for solving the problem of how to improve the power supply rejection ratio of the ring voltage controlled oscillator.

In order to achieve the above purpose, the application adopts the following technical scheme:

in a first aspect of an embodiment of the present application, there is provided a ring voltage controlled oscillator, including: the grid electrode of the switching tube is coupled with the voltage control end, the first electrode of the switching tube is coupled with the power supply voltage end, and the second electrode of the switching tube is coupled with the oscillating circuit; the switching tube is used for outputting a signal to the oscillating circuit from the second pole of the switching tube under the control of the voltage control end; the input end of the noise amplifying circuit is coupled with the power supply voltage end, and the output end of the noise amplifying circuit is coupled with the substrate electrode of the switching tube; the power supply voltage amplifying circuit is used for receiving the power supply voltage of the power supply voltage end, amplifying power supply noise of the power supply voltage and outputting the amplified power supply noise to a substrate electrode of the switching tube; the oscillating circuit is used for generating a clock signal according to the output of the second pole of the switching tube; the threshold voltage of the switching tube is adjusted under the influence of amplified power supply noise received by the substrate electrode by the switching tube so as to inhibit the power supply noise of the power supply voltage received by the first electrode of the switching tube.

According to the annular voltage-controlled oscillator provided by the embodiment of the application, the substrate electrode of the switching tube is coupled with the noise amplifying circuit, the noise amplifying circuit transmits amplified power supply noise to the substrate electrode, the amplified power supply noise can change the threshold voltage of the switching tube and influence the output of the switching tube, so that the clock frequency of a clock signal is also influenced. The amplified power supply noise has the effect on the clock frequency, and can exactly offset the effect on the clock frequency caused by the power supply noise of the power supply voltage received by the first pole of the switching tube, so that the effect of reducing the effect of the power supply noise on the clock frequency is achieved. In other words, in the embodiment of the application, the power supply noise is extracted and processed (for example, amplified in a certain proportion), the extracted power supply noise (amplified power supply noise) is transmitted to the substrate electrode of the switching tube, the voltage threshold of the switching tube is changed by using the body effect of the switching tube, and the influence of the components occupied by the factors such as parasitic factors, the power supply noise and the like on the clock frequency is counteracted, so that the effect of improving the power supply rejection ratio is achieved. In addition, the annular voltage-controlled oscillator provided by the embodiment of the application can be an N-type transistor or a P-type transistor, and has wide application range. In addition, the embodiment of the application does not need to arrange a noise reduction circuit connected in series with the switching tube, can not need to additionally consume the voltage threshold degree of the power supply voltage, has smaller consumption on the power supply voltage, and can realize the generation of a high-speed clock signal under low power supply voltage. Moreover, the larger the ratio of the frequency of the clock signal output by the ring voltage controlled oscillator to the power supply voltage frequency, the larger the range of oscillation frequencies achievable by the ring voltage controlled oscillator. However, the larger the ratio of the frequency of the clock signal output by the ring voltage controlled oscillator to the frequency of the power supply voltage, the larger the influence of the power supply noise on the power supply rejection ratio. Therefore, the ratio of the frequency of the clock signal output by the annular voltage-controlled oscillator of the annular voltage-controlled oscillator to the frequency of the power supply voltage and the power supply rejection ratio need to be comprehensively considered. The embodiment of the application can reduce or even eliminate the influence of power supply noise on the power supply rejection ratio by introducing the noise amplifying circuit into the annular voltage-controlled oscillator, solves the problem of the mutual compromise of the oscillation frequency range and the power supply rejection ratio, and can be applied to products of the annular voltage-controlled oscillator which are required to have the ratio of the frequency of the clock signal output by the large annular voltage-controlled oscillator to the frequency of the power supply voltage.

In one possible implementation, the noise amplification circuit includes a noise extraction circuit, an amplifier, and a dc voltage reduction circuit; the noise extraction circuit is coupled with the power supply voltage end, the first voltage end and the input end of the amplifier; the output end of the amplifier is coupled with the direct-current voltage reduction circuit; the direct-current voltage reduction circuit is also coupled with the power supply voltage end and the substrate electrode of the switching tube. A realization scheme with simple structure.

In one possible implementation, the noise extraction circuit includes a first capacitor and a first resistor; the first end of the first capacitor is coupled with the power supply voltage end, and the second end of the first capacitor is coupled with the first end of the first resistor and the input end of the amplifier; the second terminal of the first resistor is coupled to the first voltage terminal. A realization scheme with simple structure.

In one possible implementation, the noise extraction circuit further includes a second resistor and a first transistor; the first end of the second resistor is coupled with the power supply voltage end, and the second end of the second resistor is coupled with the first pole and the grid electrode of the first transistor and the first voltage end; the second pole of the first transistor is coupled with the second voltage terminal. By adding a second resistor and a first transistor in the noise extraction circuit, noise at the first voltage terminal can be reduced.

In one possible implementation, the noise extraction circuit includes a third resistor and a fourth resistor; the first end of the third resistor is coupled with the power supply voltage end, and the second end of the third resistor is coupled with the first end of the second resistor and the input end of the amplifier; the second terminal of the fourth resistor is coupled to the first voltage terminal.

In one possible implementation, the dc voltage reduction circuit includes a second capacitor and a fifth resistor; the first end of the second capacitor is coupled with the output end of the amplifier, and the second end of the second capacitor is coupled with the first end of the fifth resistor and the substrate electrode; the second terminal of the fifth resistor is coupled to the power voltage terminal. A realization scheme with simple structure.

In one possible implementation, the amplifier includes a second transistor, a third transistor, at least one fourth transistor, and a fifth transistor; the second transistor and the fifth transistor are both N-type transistors, and the third transistor and the fourth transistor are both P-type transistors; the grid electrode of the second transistor is coupled with the input end of the amplifier, the first electrode of the second transistor is coupled with the grid electrode and the second electrode of the third transistor, and the second electrode of the second transistor is coupled with the third voltage end; the grid electrode of the third transistor is also coupled with the grid electrode of the fourth transistor, and the first electrode of the third transistor is coupled with the power supply voltage end; the first pole of the fourth transistor is coupled with the power supply voltage end, and the second pole of the fourth transistor is coupled with the output end of the amplifier and the grid electrode of the fifth transistor and the first pole; the second pole of the fifth transistor is coupled to the third voltage terminal. A realization scheme with simple structure.

In one possible implementation, the switching transistor is a P-type transistor. A realization scheme with simple structure.

In one possible implementation manner, the oscillating circuit includes N cascaded inverters, an output end of the nth inverter is coupled to an input end of the first inverter, and the N inverters are all coupled to a second pole of the switching tube; the output end of the Nth inverter is used for outputting a clock signal, and N is an odd number which is greater than or equal to 3. A realization scheme with simple structure.

A second aspect of an embodiment of the present application provides a phase locked loop, including the ring voltage controlled oscillator of any one of the first aspects and a loop filter, an output terminal of the loop filter being coupled to a voltage control terminal of the ring voltage controlled oscillator for transmitting a control voltage to the voltage control terminal.

The phase-locked loop provided in the second aspect includes the ring voltage controlled oscillator in any one of the first aspects, and its advantages are the same as those of the ring voltage controlled oscillator, and will not be described here again.

A third aspect of an embodiment of the present application provides a radio frequency chip, including the phase-locked loop of the second aspect.

The radio frequency chip provided in the third aspect includes the phase-locked loop in the second aspect, and its beneficial effects are the same as those of the phase-locked loop, and will not be described here again.

In a fourth aspect of the embodiment of the present application, there is provided an electronic device including the radio frequency chip of the third aspect and a circuit board, where the radio frequency chip is disposed on the circuit board.

The electronic device provided in the fourth aspect includes the radio frequency chip of the third aspect, and the beneficial effects thereof are the same as those of the radio frequency chip, and are not described herein.

In a fifth aspect of the embodiments of the present application, a driving method of a ring voltage controlled oscillator is provided, where the ring voltage controlled oscillator includes a switching tube, a noise amplifying circuit and an oscillating circuit; the driving method of the annular voltage-controlled oscillator comprises the following steps: the input end of the noise amplifying circuit receives the power supply voltage of the power supply voltage end, amplifies the power supply noise of the power supply voltage, and outputs the amplified power supply noise from the output end to the substrate electrode of the switching tube; a first pole of the switching tube receives the power supply voltage of the power supply voltage end, and a substrate pole of the switching tube receives amplified power supply noise; the threshold voltage of the switching tube is adjusted under the influence of amplified power supply noise received by the substrate electrode by the switching tube so as to inhibit the power supply noise of the power supply voltage received by the first electrode of the switching tube; the grid electrode of the switching tube receives the control voltage of the voltage control end, and the switching tube outputs a signal to the oscillating circuit from the second pole of the switching tube under the control of the control voltage; the oscillating circuit generates a clock signal according to the output of the second pole of the switching tube.

Advantageous effects of the driving method of the ring voltage controlled oscillator provided in the fifth aspect are the same as those of the ring voltage controlled oscillator provided in the first aspect, and will not be described here again.

In one possible implementation, the noise amplification circuit includes a noise extraction circuit, an amplifier, and a dc voltage reduction circuit; the input end of the noise amplifying circuit receives the power supply voltage of the power supply voltage end, amplifies the power supply noise of the power supply voltage and outputs the amplified power supply noise to the substrate electrode of the switching tube, and the noise amplifying circuit comprises: the noise extraction circuit receives the power supply voltage of the power supply voltage end, and after extracting the power supply noise in the power supply voltage, the noise extraction circuit transmits the power supply noise to the amplifier; the amplifier amplifies the received signal and outputs the amplified signal to the direct-current voltage reduction circuit; the direct-current voltage reduction circuit reduces the received direct-current voltage to the direct-current voltage in the power supply voltage, and transmits the direct-current voltage in the power supply voltage and the received amplified power supply noise to the substrate electrode of the switching tube.

In one possible implementation, the noise extraction circuit includes a first capacitor and a first resistor; the noise extraction circuit receives a power supply voltage of a power supply voltage end, and after extracting power supply noise in the power supply voltage, the noise extraction circuit transmits the power supply noise to an amplifier, and the noise extraction circuit comprises: the first end of the first capacitor receives the power supply voltage of the power supply voltage end, and power supply noise in the power supply voltage is transmitted to the second end of the first capacitor; the second end of the first resistor receives the signal of the first voltage end and transmits the signal of the first voltage end to the second end of the first capacitor; the signal of the first voltage terminal and the power supply noise are used as output signals of the noise extraction circuit and are transmitted to the amplifier.

In one possible implementation, the noise extraction circuit includes a third resistor and a fourth resistor; the noise extraction circuit receives a power supply voltage of a power supply voltage end, and after extracting power supply noise in the power supply voltage, the noise extraction circuit transmits the power supply noise to an amplifier, and the noise extraction circuit comprises: the first end of the third resistor receives the power supply voltage of the power supply voltage end, and the second end of the fourth resistor receives the signal of the first voltage end; the power supply voltage is divided according to the proportion of the third resistor and the fourth resistor; the signal at the second end of the third resistor is transmitted to the amplifier as an output signal of the noise extraction circuit.

In one possible implementation, the dc voltage reduction circuit includes a second capacitor and a fifth resistor; the direct-current voltage reduction circuit reduces the received direct-current voltage to the direct-current voltage in the power supply voltage, and transmits the direct-current voltage in the power supply voltage and the received amplified power supply noise to a substrate electrode of a switching tube, and the direct-current voltage reduction circuit comprises: the first end of the second capacitor receives the direct current voltage output by the amplifier and amplified power supply noise, and the amplified power supply noise is transmitted to the second end of the second capacitor; the second end of the fifth resistor receives the power supply voltage of the power supply voltage end and transmits the power supply voltage to the second end of the second capacitor; the power supply voltage and the amplified power supply noise are used as output signals of the direct-current voltage reduction circuit and are transmitted to the substrate electrode of the switching tube.

Drawings

Fig. 1A is a schematic diagram of a frame of an electronic device according to an embodiment of the present application;

fig. 1B is a schematic diagram of a frame of a wireless communication module according to an embodiment of the present application;

fig. 1C is a schematic diagram of a phase locked loop according to an embodiment of the present application;

fig. 2A is a schematic structural diagram of a ring vco according to an embodiment of the present application;

fig. 2B is a schematic structural diagram of another ring vco according to an embodiment of the present application;

fig. 3 is a schematic diagram of a frame of a ring vco according to an embodiment of the present application;

fig. 4 is a schematic diagram of a noise amplifier according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a noise amplifier shown in fig. 4 according to an embodiment of the present application;

fig. 6A is a schematic structural diagram of another noise amplifier shown in fig. 4 according to an embodiment of the present application;

FIG. 6B is a schematic diagram of a noise amplifier shown in FIG. 4 according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of a noise amplifier shown in fig. 4 according to another embodiment of the present application;

fig. 8A is a schematic structural diagram of a ring vco shown in fig. 3 according to an embodiment of the present application;

FIG. 8B is a schematic diagram illustrating another embodiment of the ring voltage controlled oscillator shown in FIG. 3;

fig. 9 is a schematic diagram of parasitic effects of a ring vco according to an embodiment of the present application.

Reference numerals

110-a processor; 120-an external memory interface; 121-an internal memory; 130-universal serial bus interface; 140-a charge management module; 141-a power management module; 142-battery; 1-antenna 2-antenna; 150-a mobile communication module; 160-a wireless communication module; 161-receiver; 162-transmitter; 163-phase locked loop; 1631-a phase detector; 1632-a loop filter; 164-digital baseband; 170-an audio module; 170A-a speaker; 170B-receiver; 170C-microphone; 170D-earphone interface; 180-a sensor module; 190-camera; 191-a display screen; 200' -voltage controlled oscillator; 200-a ring voltage controlled oscillator; 10-a noise reduction circuit; 20-switching tube; 30-an oscillating circuit; 31-a first inverter; 32-a second inverter; 33-a third inverter; a 40-noise amplifying circuit; 41-a noise extraction circuit; 42-an amplifier; 43-dc voltage reduction circuit.

Detailed Description

The following description of the technical solutions according to the embodiments of the present application will be given with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments.

Hereinafter, the terms "second," "first," and the like are used for descriptive convenience only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "second," "first," etc. may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.

Furthermore, in embodiments of the present application, the terms "upper," "lower," "left," "right," and the like may be defined by, but are not limited to, orientations relative to the component illustrated in the figures, it being understood that the directional terms may be used for relative description and clarity, and may be modified accordingly in response to changes in the orientation of the component illustrated in the figures.

In embodiments of the present application, unless explicitly specified and limited otherwise, the term "connected" is to be construed broadly, and for example, "connected" may be either a fixed connection, a removable connection, or an integral unit; can be directly connected or indirectly connected through an intermediate medium. Furthermore, the term "coupled" may be a direct electrical connection, or an indirect electrical connection via an intermediary. The term "contact" may be direct contact or indirect contact through an intermediary.

In the embodiment of the present application, "and/or" describes the association relationship of the association object, which means that three relationships may exist, for example, a and/or B may be represented: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship.

In the embodiment of the application, the power supply noise is one of electromagnetic interference, and is external interference introduced from a power supply voltage terminal. The power supply voltage Vcc may be, for example, direct Current (DC). The power supply voltage Vcc itself is a low-frequency dc voltage, and the power supply noise of the power supply voltage Vcc is a high-frequency signal having a frequency greater than a predetermined frequency.

In the embodiment of the application, the power supply rejection ratio is the ratio of the input power supply variation (in volts) to the converter output variation (in volts).

In the embodiment of the application, the transconductance refers to the ratio of the drain current variation to the gate-source voltage variation.

In the embodiment of the application, the first pole and the second pole of the same transistor are a source electrode and a drain electrode. That is, for a transistor, the first pole is the source and the second pole is the drain. In the case of the first electrode being the drain electrode, the second electrode is the source electrode. For example, the transistor is a P-type transistor, the first pole of the transistor is the source, and the second pole of the transistor is the drain. The transistor is an N-type transistor, the drain electrode of the first electrode of the transistor, and the source electrode of the second electrode of the transistor. The gate, source, drain, and substrate of the transistor may be referred to as a gate terminal, a source terminal, a drain terminal, and a substrate terminal, respectively. The substrate pole of a transistor is also understood to be the substrate of a transistor.

The embodiment of the application provides electronic equipment. The electronic device is, for example, a consumer electronic product, a household electronic product, a vehicle-mounted electronic product, a financial terminal product, or a communication electronic product. Among the consumer electronics products are, for example, mobile phones, tablet computers (pad), notebook computers, electronic readers, personal computers (personal computer, PC), personal digital assistants (personal digital assistant, PDA), desktop displays, smart wearable products (e.g., smart watches, smart bracelets), virtual Reality (VR) terminals, augmented reality (augmented reality, AR) terminals, drones, audio, etc. Household electronic products such as intelligent door locks, televisions, remote controllers, refrigerators, small household appliances (e.g., soymilk makers, sweeping robots) and the like. The vehicle-mounted electronic products are, for example, vehicle-mounted navigator, vehicle-mounted high-density digital video disc (digital video disc, DVD) and the like. Financial end products such as automated teller machine (automated teller machine, ATM) machines, self-service terminals, and the like. The communication electronic product is a communication device such as a server, a memory, a base station, a wireless communication device, a clock signal chip, and the like. The embodiment of the application does not limit the specific form of the electronic device.

As illustrated in fig. 1A, the electronic device is a mobile phone. The handset may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (universal serial bus, USB) interface 130, a charge management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, a camera 190, a display 191, and the like. The charging management module 140, the power management module 141, the mobile communication module 150, the wireless communication module 160, and the like may be disposed on a circuit board of the mobile phone.

It will be appreciated that the structure illustrated in the embodiments of the present application is not intended to be limiting in any way. In other embodiments of the application, the handset may include more or fewer components than shown, or certain components may be combined, or certain components may be split, or different arrangements of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

The processor 110 may include one or more processing units, such as: the processor 110 may include an application processor (application processor, AP), a modem processor, a graphics processor (graphics processing unit, GPU), an image signal processor (image signal processor, ISP), a controller, a video codec, a digital signal processor (digital signal processor, DSP), a baseband processor, and/or a neural network processor (neural-network processing unit, NPU), etc. Wherein the different processing units may be separate devices or may be integrated in one or more processors. The mobile phone realizes the display function through the GPU, the display screen 191, the application processor, and the like.

The external memory interface 120 may be used to connect to an external memory card, such as a Micro SD card, to extend the memory capabilities of the handset. The external memory card communicates with the processor 110 through an external memory interface 120 to implement data storage functions. For example, files such as music, video, etc. are stored in an external memory card.

The internal memory 121 may be used to store one or more computer programs, including instructions. The processor 110 can cause the mobile phone to execute various functional applications, data processing, and the like by executing the above-described instructions stored in the internal memory 121.

The charge management module 140 is configured to receive a charge input from a charger. The power management module 141 is used for connecting the battery 142, and the charge management module 140 and the processor 110. The power management module 141 receives input from the battery 142 and/or the charge management module 140 to power the processor 110, the internal memory 121, the display 191, the camera 190, the wireless communication module 160, and the like.

The handset may implement audio functions through an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, an application processor, and the like. Such as music playing, recording, etc.

The sensor module 180 may include a pressure sensor, a gyroscope sensor, a barometric sensor, a magnetic sensor, an acceleration sensor, a distance sensor, a proximity sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor, a bone conduction sensor, and the like.

In addition, the mobile phone may further include one or more components such as a key, a motor, an indicator, a subscriber identity module (subscriber identification module, SIM) card interface, and the embodiment of the present application is not limited in this regard.

The wireless communication function of the mobile phone can be realized by the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, a modem processor, a baseband processor and the like. The antennas 1 and 2 are used for transmitting and receiving electromagnetic wave signals.

The mobile communication module 150 may provide a solution for wireless communication including 2G/3G/4G/5G, etc. applied to a cell phone.

The wireless communication module 160 may provide solutions for wireless communication including wireless local area network (wireless local area networks, WLAN) (e.g., wireless fidelity (wireless fidelity, wi-Fi) network), bluetooth (BT), global navigation satellite system (global navigation satellite system, GNSS), frequency modulation (frequency modulation, FM), near field wireless communication technology (near field communication, NFC), infrared technology (IR), etc. applied to a cell phone. The wireless communication module 160 may be one or more devices that integrate one or more communication processing modules.

By way of example, as shown in fig. 1B, wireless communication module 160 includes a receiver 161, a transmitter 162, a phase-locked loop 163, and a digital baseband 164.

The phase locked loop 163 is used to provide frequency signals to the transmitter 162 and the receiver 161. The receiver 161 is configured to receive and process the electromagnetic wave signal sent from the antenna 2, and mix the processed electromagnetic wave signal with a frequency signal provided by the phase-locked loop 163 to form a mixed electromagnetic wave signal, and send the mixed electromagnetic wave signal to the digital baseband 164. The transmitter 162 is configured to receive and process the electromagnetic wave signal provided by the digital baseband 164, mix the processed electromagnetic wave signal with the frequency signal provided by the phase-locked loop 163, form a mixed electromagnetic wave signal, and send the mixed electromagnetic wave signal to the antenna 2 and send the mixed electromagnetic wave signal out through the antenna 2.

An embodiment of the present application provides a radio frequency chip, which includes the receiver 161, the transmitter 162, and the pll 163.

The embodiment of the present application further provides a phase locked loop 163, as shown in fig. 1C, where the phase locked loop (phase locked loop, PLL) 163 includes a Phase Detector (PD) 1631, a Loop Filter (LF) 1632, and a voltage controlled oscillator (voltage controlled oscillator, VCO) 200'.

An input of the phase detector 1631 is connected to an output of the voltage controlled oscillator 200', an output of the phase detector 1631 is connected to an input of the loop filter 1632, and an output of the loop filter 1632 is connected to an input of the voltage controlled oscillator 200'.

The phase detector 1631 is configured to output a pulse error signal corresponding to the difference between the frequency of the reference signal output from the reference frequency source and the frequency of the output signal of the voltage-controlled oscillator 200'.

The loop filter 1632 is configured to output a voltage error signal corresponding to the pulse signal according to the pulse error signal.

The voltage-controlled oscillator 200' is configured to generate a frequency signal corresponding to the voltage error signal according to the voltage error signal, so as to achieve that the frequency signal output by the voltage-controlled oscillator is consistent with the frequency of the reference signal.

The phase-locked loop 163 operates on the principle that a phase difference between an input signal and an output signal is detected, the detected phase difference signal is converted into a voltage signal by the phase detector 1631 and output, the voltage signal is filtered by the loop filter 1632 to form a control voltage of the voltage-controlled oscillator 100, the frequency of the output signal of the voltage-controlled oscillator 100 is controlled, and the frequency and the phase of the output signal of the voltage-controlled oscillator 100 are fed back to the phase detector 1631 through a feedback path.

The phase locked loop 163 is an important component for providing a clock signal in an electronic device, and the voltage controlled oscillator 200' is an important component in the phase locked loop 163, and controls the frequency of the generated clock by voltage.

The mainstream voltage-controlled oscillator 200' is mainly divided into a ring voltage-controlled oscillator (ring vco) and an inductance capacitance (LC) voltage-controlled oscillator. The LC voltage-controlled oscillator is low in integration level due to the fact that inductance is needed, and is not suitable for application occasions with high integration level requirements. The greatest advantage of ring voltage controlled oscillators over LC voltage controlled oscillators is that they are small in area and can generate multi-phase clocks, but they suffer from slight disadvantages in terms of power supply noise and power consumption. With the continuous increase of clock rates required by electronic devices, ring voltage-controlled oscillators are often used for generating multiphase clocks below 20GHz, and the requirements of the ring voltage-controlled oscillators on the process and the power supply voltage are also increasing.

In the mainstream product, as shown in fig. 2A, the ring voltage controlled oscillator 200 includes a switching tube 20 and an oscillating circuit 30.

The gate of the switching tube 20 is coupled to the voltage control terminal Vctrl, the first pole of the switching tube 20 is coupled to the power supply voltage terminal (volt current condenser, VCC), and the second pole of the switching tube 20 is coupled to the oscillating circuit 30. The oscillating circuit 30 is configured to generate the clock signal CLK according to the signal output from the second pole of the switching tube 20. The oscillating circuit 30 can generate clock signals CLK with different frequencies by controlling the magnitude of the control voltage output by the voltage control terminal Vctrl.

The switching transistor 20 may be an N-type transistor or a P-type transistor. However, whether the switching transistor 20 is an N-type transistor or a P-type transistor, the Power Supply Rejection Ratio (PSRR) of the ring voltage controlled oscillator 200 is poor, i.e., the power supply noise has a large influence on the jitter (jitter) of the output clock, thereby affecting the performance of the electronic device.

To reduce the power supply rejection ratio of the ring voltage controlled oscillator 200, in some embodiments, as shown in fig. 2B, the ring voltage controlled oscillator 200 includes a noise reduction circuit 10, a switching tube 20, and an oscillator circuit 30.

The noise reduction circuit 10 includes an N-type transistor MN, a resistor R, and a capacitor C. The first terminal of the capacitor C is coupled to the reference ground, the second terminal of the capacitor C is coupled to the gate of the N-type transistor MN and the first terminal of the resistor R, the first terminal of the N-type transistor MN is coupled to the second terminal of the resistor R and the power supply voltage terminal VCC, and the second terminal of the N-type transistor is coupled to the first terminal of the switching transistor 20.

The switching tube 20 is an N-type transistor, the gate of the switching tube 20 is coupled to the voltage control terminal Vctrl, and the second pole of the switching tube 20 is coupled to the oscillating circuit 30.

The oscillating circuit 30 is configured to generate the clock signal CLK according to the signal output from the second pole of the switching tube 20.

By adding an N-type transistor Mn between the switching transistor 20 and the supply voltage terminal VCC, the N-type transistor Mn is operated in a saturation region (the gate and source of the N-type transistor Mn are coupled), and the N-type transistor Mn is equivalent to a resistor without losing the supply voltage of the supply voltage terminal VCC. Therefore, the N-type transistor Mn operating in the saturation region serves as a resistor, which can effectively isolate the power supply noise of the power supply voltage in the power supply voltage terminal VCC and improve the power supply rejection ratio of the ring voltage controlled oscillator 200. The capacitor C and the resistor R are further utilized to filter out the high-frequency noise in the power supply voltage terminal VCC, so that the high-frequency noise of the power supply voltage terminal VCC can be prevented from flowing into the switching tube 20 from the gate of the N-type transistor Mn, so as to further improve the power supply rejection ratio of the ring voltage-controlled oscillator 200.

However, the presence of the N-type transistor Mn, while reducing the power supply rejection ratio of the ring voltage controlled oscillator 200, may consume a voltage threshold (or understood as a voltage duty cycle) of the power supply voltage. Resulting in a drop in the highest clock frequency that can be generated by the ring voltage controlled oscillator 200, which is insufficient to meet the high frequency clock generation requirements at low supply voltages. The ring voltage controlled oscillator 200 shown in fig. 2B is only suitable for the structure in which the switching transistor 20 is an N-type transistor, but is not suitable for the structure in which the switching transistor 20 is a P-type transistor.

Therefore, how to generate a high-speed clock with a high power supply rejection ratio at a low power supply voltage becomes a current difficult technology.

Based on this, the embodiment of the present application also provides a ring voltage controlled oscillator 200 for generating a high-speed clock with a high power supply rejection ratio at a low power supply voltage.

As shown in fig. 3, the ring voltage controlled oscillator 200 includes: a switching tube 20, an oscillating circuit 30 and a noise amplifying circuit 40.

The gate of the switching tube 20 is coupled to the voltage control terminal Vctrl, the first pole of the switching tube 20 is coupled to the power supply voltage terminal VCC, the second pole of the switching tube 20 is coupled to the oscillating circuit 30, and the substrate pole of the switching tube 20 is coupled to the output terminal of the noise amplifying circuit 40.

The input terminal of the noise amplifying circuit 40 is coupled to the power voltage terminal VCC, and is configured to receive the power voltage VCC from the input terminal, amplify the power noise Δv of the power voltage VCC, and output the amplified power noise Δv to the substrate electrode of the switching tube 20 from the input terminal.

That is, during the driving of the ring voltage controlled oscillator 200, the noise amplifying circuit 40 receives the power supply voltage VCC of the power supply voltage terminal VCC, amplifies the power supply noise Δv of the power supply voltage VCC, and outputs the amplified power supply noise Δv' to the substrate electrode of the switching transistor 20.

The power supply voltage VCC transmitted by the power supply voltage terminal VCC includes a direct current signal and a high frequency alternating current signal. In the embodiment of the present application, the dc voltage included in the power supply voltage Vcc is referred to as a first dc voltage V1, and the high-frequency ac signal is referred to as power supply noise Δv.

Regarding the structure of the noise amplification circuit 40, as shown in fig. 4, in some embodiments, the noise amplification circuit 40 includes a noise extraction circuit 41, an amplifier 42, and a direct-current voltage reduction circuit 43.

The noise extraction circuit 41 is coupled to the power supply voltage terminal VCC, the first voltage terminal V1, and the input terminal of the amplifier 42.

During the driving process of the ring voltage controlled oscillator 200, the noise extraction circuit 41 receives the power supply voltage VCC of the power supply voltage terminal VCC, extracts the power supply noise Δv from the power supply voltage VCC, and then transmits the power supply noise Δv to the amplifier 42.

When the noise extraction circuit 41 extracts the power supply noise Δv, the power supply noise Δv may be reduced or not, which is not limited in the embodiment of the present application.

In some embodiments, as shown in fig. 5, the noise extraction circuit 41 includes a third resistor R3 and a fourth resistor R4.

The first end of the third resistor R3 is coupled to the power supply voltage terminal VCC, and the second end of the third resistor R3 is coupled to both the first end of the second resistor R2 and the input terminal of the amplifier 42. The second terminal of the fourth resistor R4 is coupled to the first voltage terminal V1.

During the driving process of the ring voltage controlled oscillator 200, the first terminal of the third resistor R3 receives the power voltage VCC of the power voltage terminal VCC, and the second terminal of the fourth resistor R4 receives the signal (including the second dc voltage V2) of the first voltage terminal V1. According to the voltage division principle, the first direct-current voltage V1 and the power supply noise Δv in the power supply voltage Vcc are divided in proportion to the third resistor R3 and the fourth resistor R4.

The second dc voltage V2 in the signal of the first voltage terminal V1 may be different from the first dc voltage V1 in the power voltage VCC of the power voltage terminal VCC. The second dc voltage V2 of the first voltage terminal V1 is, for example, smaller than the first dc voltage V1 of the power supply voltage terminal VCC. For example, the first voltage terminal V1 is a reference ground terminal.

For example, the third resistor R3 has a resistance R3, the fourth resistor R4 has a resistance R4, the power supply voltage of the power supply voltage terminal VCC is VCC, and the first voltage terminal V1 is a reference ground. Then, after the voltage is divided according to the voltage division principle, the distribution ratio of the voltage at the second end of the third resistor R3 is as follows: r 4/(r3+r4). The first direct voltage V1 and the power supply noise Δv in the power supply voltage Vcc are both reduced proportionally. The power supply noise at the second end of the third resistor R3 is referred to as reduced power supply noise Δv″, Δv= Δv×r4/(r3+r4). The dc voltage at the second end of the third resistor R3 is referred to as the reduced first dc voltage v1 ", v 1" =v1×r4/(r3+r4).

The signal at the second end of the third resistor R3 includes the reduced first dc voltage V1 "and the reduced power supply noise Δv", and is transmitted to the amplifier 42 as an output signal of the noise extraction circuit 41. That is, in the noise extraction circuit 41 shown in fig. 5, both the first direct-current voltage V1 and the power supply noise Δv in the power supply voltage Vcc are reduced.

Then, based on the structure of the noise extraction circuit 41 shown in fig. 5, after the noise extraction circuit 41 receives the power supply voltage VCC of the power supply voltage terminal VCC, the signal output from the noise extraction circuit 41 is the reduced first direct current voltage V1 "and the reduced power supply noise Δv". For example, the reduced first dc voltage v1″=v1×r4/(r3+r4), and the reduced power supply noise Δv "= Δv×r4/(r3+r4).

Two resistors connected in series are adopted, the power supply voltage Vcc of the power supply voltage end VCC is reduced by utilizing the voltage division principle, and the structure and the process are simple.

With respect to the structure of the amplifier 42, with continued reference to fig. 5, the input of the amplifier 42 is coupled to the noise extraction circuit 41, and the output of the amplifier 42 is coupled to the dc voltage reduction circuit 43.

During the driving of the ring voltage controlled oscillator 200, the amplifier 42 amplifies and outputs the received dc voltage (reduced first dc voltage V1 ") and the received power supply noise (reduced power supply noise Δv").

The amplification factor of the amplifier 42 can be adjusted as needed. The power supply noise received by the amplifier 42 may be different depending on the structure of the noise extraction circuit 41, and the amplification factor of the amplifier 42 may be different depending on the received power supply noise.

As illustrated in fig. 5, the noise extraction circuit 41 includes two third resistors R3 and fourth resistors R4 connected in series, for example. The power supply noise outputted from the noise extraction circuit 41 is the reduced power supply noise Δv ", and the dc voltage outputted from the noise extraction circuit 41 is the reduced first dc voltage v1". For example, the reduced power supply noise Δv "= Δv×r4/(r3+r4). The reduced first dc voltage v1 "=v1×r4/(r3+r4).

Then, in order to amplify the amplified power supply noise Δv' =k×Δv outputted from the amplifier 42, the received power supply noise (reduced power supply noise Δv ") needs to be amplified by k×r3+r4)/r 4. As such, the amplified power supply noise Δv' = Δv ". K (r3+r4)/r4= Δv [ r 4/(r3+r4) ]xk [ (r3+r4)/r4 ] = Δv x K output from the amplifier 42.

It should be appreciated that the amplifier 42 amplifies the received supply noise (Δv ") by a factor K (r3+r4)/r 4, and simultaneously amplifies the received reduced first dc voltage v1″ by a factor K (r3+r4)/r 4. Then, the signal output from the amplifier 42 is the amplified dc voltage and the amplified power supply noise Δv'. For example, the amplified power supply noise Δv' = Δv×k, in the embodiment of the present application, the amplified dc voltage is referred to as a third dc voltage V3, v3=v1″ ×k (r3+r4)/r4=v1×r 4/(r3+r4) ]×k [ (r3+r4)/r 4] =v1×k.

Regarding the structure of the noise extraction circuit 41, in other embodiments, as shown in fig. 6A, the noise extraction circuit 41 includes a first capacitor C1 and a first resistor R1.

The first end of the first capacitor C1 is coupled to the power voltage terminal VCC, and the second end of the first capacitor C1 is coupled to the first end of the first resistor R1 and the input terminal of the amplifier 42. The second terminal of the first resistor R1 is coupled to the first voltage terminal V1. In this case, the noise extraction circuit 41 can be regarded as a high-pass filter.

In the driving process of the ring voltage-controlled oscillator 200, the first end of the first capacitor C1 receives the power voltage VCC of the power voltage end VCC, and the power noise Δv in the power voltage VCC is transmitted to the second end of the first capacitor C1 according to the principle of the capacitor passing ac and dc. The second terminal of the first resistor R1 receives the signal of the first voltage terminal V1, and transmits the signal of the first voltage terminal V1 to the second terminal of the first capacitor C1, where the second dc voltage V2 in the signal of the first voltage terminal V1 is used as the dc bias of the amplifier 42. The noise in the signal at the first voltage terminal V1 is negligible or taken into account when designing the amplification of the amplifier 42. According to the high-pass filtering principle, the first capacitor C1 filters out the low-frequency signal (i.e., the first dc voltage V1) in the power voltage VCC output by the power voltage terminal VCC, and allows the high-frequency signal (i.e., the power noise Δv) in the power voltage VCC output by the power voltage terminal VCC to pass through. The low frequency signal at the second end of the first capacitor C1 is determined by the voltage at the second end of the first resistor R1 (the second dc voltage V2 at the first voltage end V1). Therefore, the noise extraction circuit 41 reduces the low frequency signal (dc signal) at the second end of the first capacitor C1 to the second dc voltage V2 at the first voltage end V1, and the power supply noise Δv is unchanged. The signal of the first voltage terminal V1 and the power supply noise Δv are transmitted to the amplifier 42 as output signals of the noise extracting circuit 41.

That is, in the noise extraction circuit 41 shown in fig. 6A, only the first direct-current voltage V1 in the power supply voltage Vcc is reduced, and the power supply noise Δv in the power supply voltage Vcc is not reduced.

The magnitude of the second direct current voltage V2 of the first voltage terminal V1 is not limited, and the second direct current voltage V2 is reasonably set according to the requirement.

In some embodiments, the second dc voltage V2 of the first voltage terminal V1 is smaller than the first dc voltage V1 of the power voltage terminal VCC to adapt to the operating voltage of the amplifier 42.

For example, as shown in fig. 6A, the signal of the first voltage terminal V1 is directly provided by the signal terminal. In this way, the ring voltage controlled oscillator 200 has a simple structure and high integration.

Alternatively, as illustrated in fig. 6B, the signal of the first voltage terminal V1 is provided by a circuit structure.

In this case, as shown in fig. 6B, the noise extraction circuit 41 further includes a second resistor R2 and a first transistor M1.

The first terminal of the second resistor R2 is coupled to the power voltage terminal VCC, and the second terminal of the second resistor R2 is coupled to the first pole and gate of the first transistor M1 and the first voltage terminal V1. The second pole of the first transistor M1 is coupled to the second voltage terminal V2.

The first transistor M1 may be an N-type transistor as shown in fig. 6B, or a P-type transistor. The second voltage terminal V2 may be, for example, a reference ground terminal.

During the driving of the ring voltage controlled oscillator 200, the first transistor M1 operates in the saturation region, which is equivalent to a resistor. By the voltage division between the second resistor R2 and the first transistor M1, the power supply voltage Vcc at the first end of the second resistor R2 is divided according to the ratio of the second resistor R2 to the first transistor M1, and the signal at the second end of the second resistor R2 is used as the signal at the first voltage end V1. At this time, the first voltage terminal V1 receives a voltage obtained by dividing the power supply voltage Vcc. Not only the first direct-current voltage V1 in the power supply voltage Vcc but also the power supply noise Δv in the power supply voltage Vcc are divided.

The second dc voltage V2 of the first voltage terminal V1 is provided by the first transistor M1 and the second resistor R2, and after the power voltage VCC of the power voltage terminal VCC passes through the second resistor R2, the first dc voltage V1 is reduced to the second dc voltage V2, and the power noise Δv in the power voltage VCC is reduced. Compared with the direct supply of the second direct current voltage v2 through the voltage terminal, the cooperation of the first transistor M1 and the second resistor R2 to supply the second direct current voltage v2 can reduce noise carried by the second direct current voltage v 2.

Then, based on the structure of the noise extraction circuit 41 shown in fig. 6A and 6B, after the noise extraction circuit 41 receives the power supply voltage VCC of the power supply voltage terminal VCC, the signal output from the noise extraction circuit 41 is the second direct current voltage V2 and the power supply noise Δv which is not reduced. In this way, the need for amplification of the amplifier 42 can be reduced when the power supply noise needs to be amplified to a particular level.

With respect to the amplifier 42, please continue to refer to fig. 6A, an input terminal of the amplifier 42 is coupled to the noise extraction circuit 41, and an output terminal of the amplifier 42 is coupled to the dc voltage reduction circuit 43.

During the driving of the ring voltage controlled oscillator 200, the amplifier 42 amplifies the received dc voltage (second dc voltage V2) and the received power supply noise (power supply noise Δv), and outputs the amplified dc voltage and the amplified power supply noise to the dc voltage reduction circuit 43.

The amplification factor of the amplifier 42 is K, and the amplification factor K of the amplifier 42 can be adjusted as required. As is clear from the above description of the noise extraction circuit 41, the power supply noise received by the amplifier 42 may be the reduced power supply noise Δv″ or may be the unreduced power supply noise Δv according to the structure of the noise extraction circuit 41. The amplification of the amplifier 42 may also be different depending on the power supply noise received.

As illustrated in fig. 6A, the noise extraction circuit 41 includes a first capacitor C1 and a first resistor R1 connected in series. The power supply noise outputted from the noise extraction circuit 41 is unchanged power supply noise Δv, and the dc voltage outputted from the noise extraction circuit 41 is the second dc voltage V2.

Then, in order to amplify the amplified power supply noise Δv' =k×Δv output from the amplifier 42, it is necessary to amplify the power supply noise (power supply noise Δv) received multiple times. Thus, the amplified power supply noise Δv' = Δv×k outputted from the amplifier 42.

It will be appreciated that the amplifier 42 amplifies the received supply noise (Δv) by a factor of K, and simultaneously amplifies the received second dc voltage V2 by a factor of K. Then, the signal output from the amplifier 42 is the third dc voltage V3 and the amplified power supply noise Δv'. For example, the amplified power supply noise Δv' = Δv×k, and the third dc voltage v3=v2×k.

The specific structure of the amplifier 42 is not limited in the embodiment of the present application, and the structure having an amplifying effect on signals in the related art is applicable to the present application.

To simplify the circuit structure of the ring voltage controlled oscillator 200, the amplifier 42 does not require an additional bias voltage and the gain bandwidth product of the amplifier 42 is improved. In some embodiments, the amplifier 42 is a single-stage differential amplifier.

In some embodiments, as shown in fig. 7, the amplifier 42 includes a second transistor M2, a third transistor M3, at least one fourth transistor M4, and a fifth transistor M5.

As illustrated in fig. 7, the second transistor M2 and the fifth transistor M5 are both N-type transistors, and the third transistor M3 and the fourth transistor M4 are both P-type transistors.

The second pole of the second transistor M2 and the second pole of the fifth transistor M5 are both coupled to the third voltage terminal V3, and the first pole of the third transistor M3 and the first pole of the fourth transistor M4 are both coupled to the power supply voltage terminal VCC.

In detail, the gate of the second transistor M2 is coupled to the input terminal of the amplifier 42, the first pole of the second transistor M2 is coupled to both the gate and the second pole of the third transistor M3, and the second pole of the second transistor M2 is coupled to the third voltage terminal V3.

The gate of the third transistor M3 is further coupled to the gate of the fourth transistor M4, and the first pole of the third transistor M3 is coupled to the power voltage terminal VCC.

The first pole of the fourth transistor M4 is coupled to the power voltage terminal VCC, and the second pole of the fourth transistor M4 is coupled to the output terminal of the amplifier 42 and the gate and the first pole of the fifth transistor M5.

The second pole of the fifth transistor M5 is coupled to the third voltage terminal V3. The third voltage terminal V3 may be, for example, a reference ground terminal.

In some embodiments, the amplifier 42 includes a fourth transistor M4.

Thus, the amplifier 42 has a simple structure and is easy to layout.

In other embodiments, the amplifier 42 includes a plurality of fourth transistors M4 in parallel.

Thus, the number of fourth transistors M4 turned on can be adjusted as needed to adjust the amplification factor of the amplifier 42. That is, when the amplifier 42 includes a plurality of fourth transistors M4 connected in parallel, the amplification factor of the amplifier 42 can be adjusted as needed. The gain of the amplifier 42 is adjustable (e.g. may be adjustable in the range of 0dB to 15 dB) by means of an adjustable number of turned-on fourth transistors M4. I.e. the amplification factor K of the amplifier 42 is adjustable). Thereby, the influence of the power noise DeltaV on the power supply rejection ratio can be offset to the greatest extent.

For example, a switching control tube coupled to the fourth transistors M4 may be provided, by which the on and off of each fourth transistor M4 is independently controlled.

During the driving process of the ring voltage-controlled oscillator 200, the second transistor M2, the third transistor M3, the at least one fourth transistor M4 and the fifth transistor M5 are all operated in the saturation region, and the first voltage signal V is transmitted to the gate of the second transistor M2 ₁ Amplified as a current signal I2 by a second transistor M2, i2=gm2×v ₁ . At this time, the second transistor M2 outputs the second voltage signal V to the third transistor M3 ₂ ＝I2/gm3＝(gm2*V ₁ ) Gm3. Second voltage signal V ₂ Amplified as a current signal I4 by a fourth transistor M4, i4=gm4×v ₂ . At this time, the fourth transistor M4 outputs the third voltage signal V to the fifth transistor M5 ₃ ＝I4/gm5＝[(gm4*gm2*V ₁ )/gm3]Gm5. The gate of the fifth transistor M5 is coupled to the first pole of the fifth transistor M5 for receiving the third voltage signal V outputted from the fourth transistor M4 ₃ . Gain of amplifier 42 = V ₃ /V ₁ ＝[(gm4*gm2)/gm3]Gm5, the gain (amplification factor) of the amplifier 42 can be controlled by adjusting the number of the fourth transistors M4 in the amplifier 42 (corresponding to adjusting the size of gm 4). Wherein gm2 is the transconductance of the second transistor M2, gm3 is the transconductance of the third transistor M3, gm4 is the transconductance of the at least one fourth transistor M4, and gm5 is the transconductance of the fifth transistor M5.

In some embodiments, the second dc voltage V2 of the first voltage terminal V1 is of a magnitude capable of controlling the second transistor M2, the third transistor M3, the at least one fourth transistor M4 and the fifth transistor M5 to operate in the saturation region.

By adopting a structure including the second transistor M2, the third transistor M3, at least one fourth transistor M4, and the fifth transistor M5 as the amplifier 42 in the embodiment of the present application, the structure is simple, and the integration level is high.

In addition, based on the noise extraction circuit 41 shown in fig. 7, the transistors in the noise extraction circuit 41 are affected by the process (P), the voltage (V), and the temperature (T), and the transistors in the amplifier 42 are also affected by PVT. The two effects are combined to have a relatively small effect on the amplification factor of the amplifier 42. The simulation shows that, based on the structures of the noise extraction circuit 41 and the amplifier 42 shown in fig. 7, under different PVT influences, the gain difference of the amplifier 42 is within 1dB in the frequency range of 40 kHz-800 MHz, the difference is smaller, and the amplifier 42 has better PVT convergence. That is, based on the configuration shown in fig. 7, the amplifier 42 is stable in amplification of signals in the 40kHz to 800MHz band under the influence of different PVT.

As shown in fig. 5, the dc voltage reducing circuit 43 is coupled to the output terminal of the amplifier 42, and receives the signal output by the amplifier 42. The dc voltage reduction circuit 43 is further coupled to the power voltage terminal VCC, and the signal output by the output terminal Vout of the dc voltage reduction circuit 43 is the signal output by the noise amplifying circuit 40, and the output terminal Vout of the dc voltage reduction circuit 43 is coupled to the substrate electrode of the switching tube 20.

In the driving process of the ring voltage-controlled oscillator 200, the dc voltage reduction circuit 43 receives the signal output by the amplifier 42, reduces the third dc voltage V3 output by the received amplifier 42 to the first dc voltage V1 in the power supply voltage Vcc, and transmits the first dc voltage V1 in the power supply voltage Vcc and the amplified power supply noise Δv' output by the received amplifier 42 to the substrate electrode of the switching transistor 20.

As for the dc voltage reducing circuit 43, as shown in fig. 5, the dc voltage reducing circuit 43 includes a second capacitor C2 and a fifth resistor R5.

The first end of the second capacitor C2 is coupled to the output terminal of the amplifier 42, and the second end of the second capacitor C2 is coupled to the first end of the fifth resistor R5 and the output terminal Vout of the dc voltage reduction circuit 43.

The second terminal of the fifth resistor R5 is coupled to the power voltage terminal VCC.

In the driving process of the ring voltage-controlled oscillator 200, the first end of the second capacitor C2 receives the third dc voltage V3 and the amplified power noise Δv 'output by the amplifier 42, and according to the principle that the capacitor is connected to ac and blocks dc, the amplified power noise Δv' in the signal output by the amplifier 42 is transmitted to the second end of the second capacitor C2. The second end of the fifth resistor R5 receives the power supply voltage VCC of the power supply voltage terminal VCC and transmits the power supply voltage VCC to the second end of the second capacitor C2. According to the high-pass filtering principle, the second capacitor C2 filters out the low-frequency signal (the third dc voltage V3) in the signal output from the amplifier 42, and allows the high-frequency signal (the amplified power supply noise Δv') in the signal output from the amplifier 42 to pass. The low frequency signal at the second end of the second capacitor C2 is determined by the voltage at the second end of the fifth resistor R5 (the first dc voltage v1 in the power supply voltage Vcc). Therefore, the dc voltage reducing circuit 43 reduces the low frequency signal at the second end of the second capacitor C2 to the first dc voltage V1, and the amplified power supply noise Δv' outputted from the amplifier 42 is unchanged.

The power supply voltage Vcc and the amplified power supply noise Δv' are outputted from the output terminal Vout of the dc voltage reduction circuit 43 as the output signal of the dc voltage reduction circuit 43, and are transferred to the substrate electrode of the switching transistor 20.

In setting K in the amplification factor of the amplifier 42, the power supply noise Δv in the power supply voltage Vcc received by the second end of the fifth resistor R5 in the dc voltage reduction circuit 43 may be taken into consideration.

As shown in fig. 8A, regarding the switching tube 20, the gate of the switching tube 20 is coupled to the voltage control terminal Vctrl, the first pole of the switching tube 20 is coupled to the power voltage terminal VCC, the second pole of the switching tube 20 is coupled to the oscillating circuit 30, and the substrate pole of the switching tube 20 is coupled to the noise amplifying circuit 40.

The voltage control terminal Vctrl is coupled to, for example, the loop filter 1632 in the phase-locked loop 163, and is configured to receive the control voltage output by the loop filter 1632. The switching tube 20 is configured to output a signal from the second pole of the switching tube 20 to the oscillating circuit 30 under the control of the control voltage received by the voltage control terminal Vctrl.

The switching transistor 20 may be an N-type transistor or a P-type transistor. The type of transistor may be, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET).

In the embodiment of the present application, the switching transistor 20 may be a transistor, or may be a plurality of transistors connected in series or in parallel, and fig. 8A only illustrates an example in which the switching transistor 20 is a P-type transistor. In the embodiment of the application, the transistor with the arrow pointing to the gate direction is a P-type transistor, and the transistor with the arrow deviating from the gate direction is an N-type transistor.

In the switching tube 20 according to the embodiment of the present application, on the basis that the gate, the source and the drain of the switching tube 20 receive signals, the substrate electrode also receives signals different from the first electrode (the substrate electrode of the switching tube 20 shown in fig. 2A is coupled to the first electrode). And the noise in the signal received by the substrate electrode is amplified power supply noise Δv ' (Δv ' =k×Δv), and the amplified power supply noise Δv ' is greater than the power supply noise Δv in the power supply voltage Vcc received by the first electrode.

For example, the power supply voltage VCC transmitted by the power supply voltage terminal VCC includes a first dc voltage V1 and a carried power supply noise Δv, and the noise amplifying circuit 40 amplifies the power supply noise Δv in the power supply voltage VCC to k×Δv, generates an amplified power supply noise Δv ' (Δv ' =k×Δv), and then transmits the amplified power supply noise Δv ' and the first dc voltage V1 in the power supply voltage VCC to the substrate electrode of the switching tube 20.

That is, during the ring voltage controlled oscillator driving, the noise amplifying circuit 40 receives the power supply voltage VCC of the power supply voltage terminal VCC, does not amplify the first dc voltage V1 in the power supply voltage VCC, and amplifies only the power supply noise Δv in the power supply voltage VCC. The first direct current voltage V1 and the amplified power supply noise Δv' are then output to the substrate electrode of the switching tube 20.

The first pole of the switch tube 20 receives the power voltage VCC (including the first dc voltage V1 and the power noise Δv) of the power voltage terminal VCC, the substrate pole of the switch tube 20 receives the first dc voltage V1 and the amplified power noise Δv', and the signal received by the substrate pole can adjust the threshold voltage of the switch tube 20 to suppress the power noise Δv of the power voltage VCC received by the first pole of the switch tube 20. The gate of the switching tube 20 receives the control voltage of the voltage control terminal Vctrl, and the switching tube 20 outputs a signal from the second pole of the switching tube 20 to the oscillating circuit 30 under the control of the control voltage.

With continued reference to fig. 8A, the oscillating circuit 30 is coupled to the second pole of the switch tube 20, and the oscillating circuit 30 is configured to generate the clock signal CLK according to the output of the second pole of the switch tube 20.

That is, during the driving process of the ring voltage controlled oscillator 200, the oscillating circuit 30 generates the clock signal CLK according to the output of the second pole of the switching tube 20.

Regarding the structure of the oscillating circuit 30, in some embodiments, the oscillating circuit 30 includes N cascaded inverters, wherein the output terminal of the nth inverter is coupled to the input terminal of the first inverter, and the N inverters are all coupled to the second pole of the switching tube 20.

The output end of the nth inverter is used as the output end of the oscillating circuit 30 for outputting the clock signal CLK, and N is an odd number greater than or equal to 3.

As shown in fig. 8A, the oscillating circuit 30 includes 3 inverters sequentially connected end to end, the 3 inverters are a first inverter 31, a second inverter 32 and a third inverter 33, respectively, an output terminal of the first inverter 31 is connected to an input terminal of the second inverter 32, an output terminal of the second inverter 32 is connected to an input terminal of the third inverter 33, an output terminal of the third inverter 33 is an output terminal of the oscillating circuit 30, and an output terminal of the third inverter 33 is connected to an input terminal of the first inverter 31. The output terminal of the third inverter 33 is used as the output terminal of the oscillating circuit 30 for outputting the clock signal CLK.

The first inverter 31, the second inverter 32 and the third inverter 33 respectively include two connection terminals, one of which is coupled to the second pole of the switching tube 20, and the other of which is coupled to the fourth voltage terminal V4.

In order to reduce the static power consumption of the inverter, the anti-interference capability, the power utilization rate and the load carrying capability of the inverter are improved. In some embodiments, the inverter included in the oscillating circuit 30 is a complementary metal oxide semiconductor (complementary metal oxide semiconductor, CMOS) inverter.

As illustrated in fig. 8B, the first inverter 31 includes a first N-type pipe Mn1 and a first P-type pipe Mp1 connected in series, the second inverter 32 includes a second N-type pipe Mn2 and a second P-type pipe Mp2 connected in series, and the third inverter 33 includes a third N-type pipe Mn3 and a third P-type pipe Mp3 connected in series.

The gate of the first P-type tube Mp1 and the gate of the first N-type tube Mn1 are both coupled to the second pole of the third P-type tube Mp3, the first pole of the first P-type tube Mp1 is coupled to the second pole of the switching tube 20, the second pole of the first P-type tube Mp1 is coupled to the first pole of the first N-type tube Mn1, and the second pole of the first N-type tube Mn1 is coupled to the fourth voltage terminal V4.

For example, the first N-type tube Mn1 serves as a driving tube (pull-down tube), and the first P-type tube Mp1 serves as a load tube (pull-up tube). The gate of the first P-type tube Mp1 and the gate of the first N-type tube Mn1 are coupled together as the signal input terminal of the first inverter 31. The source of the first N-type transistor Mn1 is coupled to the reference ground, the source of the first P-type transistor Mp1 is coupled to the second pole of the switch tube 20, and the drains of the first N-type transistor Mn1 and the first P-type transistor Mp1 are coupled together as the output of the first inverter 31.

The gate of the second P-type tube Mp2 and the gate of the second N-type tube Mn2 are both coupled to the second pole of the first P-type tube Mp1, the first pole of the second P-type tube Mp2 is coupled to the second pole of the switching tube 20, the second pole of the second P-type tube Mp2 is coupled to the first pole of the second N-type tube Mn2, and the second pole of the second N-type tube Mn2 is coupled to the fourth voltage terminal V4.

For example, the second N-type tube Mn2 serves as a driving tube (pull-down tube), and the second P-type tube Mp2 serves as a load tube (pull-up tube). The gate of the second P-type transistor Mp2 and the gate of the second N-type transistor Mn2 are coupled together as the signal input terminal of the second inverter 32. The source of the second N-type transistor Mn2 is coupled to the reference ground, the source of the second P-type transistor Mp2 is coupled to the second pole of the switch transistor 20, and the drains of the second N-type transistor Mn2 and the second P-type transistor Mp2 are coupled together as the output of the second inverter 32.

The gate of the third P-type tube Mp3 and the gate of the third N-type tube Mn3 are both coupled to the second pole of the second P-type tube Mp2, the first pole of the third P-type tube Mp3 is coupled to the second pole of the switching tube 20, the second pole of the third P-type tube Mp3 is coupled to the first pole of the third N-type tube Mn3, and the second pole of the third N-type tube Mn3 is coupled to the fourth voltage terminal V4. The second pole of the third P-type transistor Mp3 is used as the output terminal of the third inverter 33 (i.e. the output terminal of the oscillating circuit 30) to output the clock signal CLK.

For example, the third N-type tube Mn3 serves as a driving tube (pull-down tube), and the third P-type tube Mp3 serves as a load tube (pull-up tube). The gate of the third P-type pipe Mp3 and the gate of the third N-type pipe Mn3 are coupled together as the signal input terminal of the third inverter 33. The source of the third N-type tube Mn3 is coupled to the reference ground, the source of the third P-type tube Mp3 is coupled to the second pole of the switch tube 20, and the drains of the third N-type tube Mn3 and the third P-type tube Mp3 are coupled together as the output of the third inverter 33.

That is, the oscillator circuit 30 is formed by ending an odd number of inverters by the inherent transmission delay time of the gate circuit. During the driving process of the ring voltage controlled oscillator 200, the oscillation principle of the oscillation circuit 30 can be explained as follows by using the barkhausen criterion: the loop is disconnected at any point, the open loop gain is more than or equal to 1, the open loop phase shift reaches 180 degrees, the negative feedback is utilized to form a closed loop, the total phase shift of the closed loop reaches 360 degrees, and the positive feedback is formed. The output (e.g., current signal) of the second pole of the switching tube 20 determines the transmission delay of each inverter, and thus determines the oscillation frequency of the finally generated clock signal CLK.

The above description has been made on the structure of the ring voltage controlled oscillator 200 provided in the embodiment of the present application, and the following description is made on the principle of suppressing the power supply noise Δv of the power supply voltage Vcc in the ring voltage controlled oscillator 200:

as shown in fig. 9, during operation of the switching tube 20, there are a gate-source parasitic capacitance (Cgs), a gate-drain parasitic capacitance (Cgd), a source-drain parasitic capacitance (Cds), and a source-drain parasitic resistance (Rds). The output clock frequency Freq of the ring voltage controlled oscillator 200 is calculated as follows:

Freq＝Kico*Iring；(1)

where Kico is the clock frequency (GHz/A) generated by the unit current, and Iring is the signal provided by the second pole of the switching tube 20 to the oscillator circuit 30.

Iring＝Gm*Vgs+Cgd*△V+Cds*△V+△V/Rds；(2)

Where Gm is the transconductance of the switching tube 20, vgs is the gate-source voltage of the switching tube 20, cgd is the gate-drain parasitic capacitance of the switching tube 20, Δv is the power supply noise of the power supply voltage VCC transmitted by the power supply voltage terminal VCC, cds is the source-drain parasitic capacitance of the switching tube 20, and Rds is the source-drain parasitic resistance of the switching tube 20.

Vth＝Vth0+γ*Vbs＝Vth0+γ*(K-1)*△V；(3)

Where Vth is the threshold voltage of the switching tube 20, vth0 is the threshold voltage of the switching tube 20 without taking the body effect (body effect) into account, γ is the body effect factor, vbs is the substrate source voltage of the switching tube 20, K is the amplification factor of the noise amplifying circuit 40 to the power supply noise Δv in the power supply voltage Vcc, and K >1.

Gm＝μ*Cox*(W/L)*(Vgs-Vth) ² /2＝μ*Cox*(W/L)*(Vgs-Vth0-γ*(K-1)*△V) ² /2 (4)

Where μ is the electron mobility of the switching tube 20, cox is the capacitance of the gate oxide per unit area, and W/L is the aspect ratio of the channel of the switching tube 20.

Substituting the above formulas (2), (3) and (4) into formula (1) yields:

Freq＝Kico*(Gm*Vgs+Cgd*△V+Cds*△V+△V/Rds)

＝Kico*(Vgs*μ*Cox*(W/L)*(Vgs-Vth0-γ*(K-1)*△V) ² /2+Cgd*△V+Cds*△V+△V/Rds)。

wherein, cgd Δv+cds Δv+Δv/Rds in the above formula is parasitic of the power noise Δv through the switching tube 20, and interferes with the clock frequency, and the presence of this portion increases the current signal Iring, thereby reducing the power rejection ratio of the ring voltage controlled oscillator 200. And γ (K-1) Δv is the influence on the clock frequency after the substrate electrode of the switching tube 20 is coupled to the noise amplifying circuit 40 to introduce the amplified power supply noise Δv' to the substrate electrode of the switching tube 20. As can be seen from the formula, γ (K-1) Δv has the effect of counteracting Cgd Δv+cds+Δv+Δv/Rds. That is, the amplified power supply noise Δv' is introduced into the substrate electrode of the switching transistor 20, and has an effect of canceling the influence of the power supply noise Δv on the clock frequency, thereby reducing the current signal Iring and increasing the power supply rejection ratio of the ring voltage controlled oscillator 200. By adjusting the amplification factor of the power supply noise Δv, the influence of the power supply noise Δv of the power supply signal received by the first pole of the switching tube 20 on the clock frequency can be eliminated as much as possible, so as to eliminate the influence of the power supply noise Δv on the power supply rejection ratio.

Here, the working principle of the ring voltage controlled oscillator 200 provided in the embodiment of the present application will be described with reference to the above calculation formula of the clock frequency. By adjusting the control voltage received by the gate of the switching tube 20, the threshold voltage Vth of the switching tube 20 can be adjusted to change the current Iring supplied to the oscillating circuit 30 by the second pole of the switching tube 20, thereby changing the clock frequency of the ring voltage controlled oscillator 200, and realizing the control of the clock frequency of the ring voltage controlled oscillator 200 by the control voltage of the voltage control terminal Vctrl.

As can be seen from the above description, in the ring voltage-controlled oscillator 200 according to the embodiment of the present application, the substrate electrode of the switching tube 20 is coupled to the noise amplifying circuit 40, the noise amplifying circuit 40 transmits the amplified power noise Δv 'to the substrate electrode, and the amplified power noise Δv' can change the threshold voltage Vth of the switching tube, and affect the current signal Iring output by the switching tube 20, thereby also affecting the clock frequency of the clock signal CLK. The amplified power supply noise delta V' has an effect on the clock frequency, which can exactly cancel the effect on the clock frequency by the power supply noise delta V of the power supply voltage Vcc received by the first pole of the switch tube 20, thereby achieving the effect of reducing the effect on the clock frequency by the power supply noise delta V. That is, in the embodiment of the present application, the power noise Δv is extracted and processed (for example, amplified in a certain proportion), and the extracted power noise (amplified power noise Δv') is transmitted to the substrate electrode of the switching tube 20, and the voltage threshold of the switching tube 20 is changed by using the body effect of the switching tube 20, so as to cancel the influence of the parasitic factor and the component occupied by the power noise Δv on the clock frequency, thereby achieving the effect of improving the power supply rejection ratio.

In addition, in the ring voltage controlled oscillator 200 provided in the embodiment of the present application, the switching tube 20 may be an N-type transistor or a P-type transistor, which has a wide application range. In addition, the embodiment of the application does not need to arrange the noise reduction circuit 10 connected in series with the switch tube 20, can not additionally consume the voltage threshold degree of the power supply voltage Vcc, has smaller consumption on the power supply voltage Vcc, and can realize the generation of high-speed clock signals under low power supply voltage.

Also, the larger Kvco (ratio of the frequency of the clock signal CLK output by the ring voltage controlled oscillator 200 to the frequency of the power supply voltage Vcc) of the ring voltage controlled oscillator 200, the larger the range of oscillation frequency that the ring voltage controlled oscillator 200 can achieve. However, the larger Kvco, the larger the influence of the power supply noise Δv on the power supply rejection ratio. Therefore, the Kvco and the power supply rejection ratio of the ring voltage controlled oscillator 200 need to be considered in combination. By introducing the noise amplifying circuit 40 into the ring voltage controlled oscillator 200, the embodiment of the application can reduce or even eliminate the influence of the power supply noise DeltaV on the power supply rejection ratio, solves the problem of the mutual compromise of the oscillation frequency range and the power supply rejection ratio, and can be applied to products requiring the ring voltage controlled oscillator 200 with large Kvco.

It should be noted that, the noise amplifying circuit 40 provided in the embodiment of the present application may be applied not only to the variable annular voltage-controlled oscillator 200 in the present application, but also to any circuit that needs to amplify power supply noise.

The present application is not limited to the above embodiments, and any changes or substitutions within the technical scope of the present application should be covered by the scope of the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.

Claims

1. A ring voltage controlled oscillator comprising:

the grid electrode of the switching tube is coupled with the voltage control end, the first electrode of the switching tube is coupled with the power supply voltage end, and the second electrode of the switching tube is coupled with the oscillating circuit;

the input end of the noise amplifying circuit is coupled with the power supply voltage end, and the output end of the noise amplifying circuit is coupled with the substrate electrode of the switching tube;

and the oscillating circuit is used for generating a clock signal according to the output of the second pole of the switching tube.

2. The ring voltage controlled oscillator of claim 1, wherein the noise amplification circuit comprises a noise extraction circuit, an amplifier, and a dc voltage reduction circuit;

the noise extraction circuit is coupled with the power supply voltage end, the first voltage end and the input end of the amplifier;

The output end of the amplifier is coupled with the direct-current voltage reduction circuit;

the direct-current voltage reduction circuit is also coupled with the power supply voltage end and the substrate electrode of the switching tube.

3. The ring voltage controlled oscillator of claim 2, wherein the noise extraction circuit comprises a first capacitor and a first resistor;

the first end of the first capacitor is coupled with the power supply voltage end, and the second end of the first capacitor is coupled with the first end of the first resistor and the input end of the amplifier;

the second terminal of the first resistor is coupled to the first voltage terminal.

4. The ring voltage controlled oscillator of claim 3, wherein the noise extraction circuit further comprises a second resistor and a first transistor;

a first end of the second resistor is coupled with the power supply voltage end, and a second end of the second resistor is coupled with a first pole and a grid of the first transistor and the first voltage end;

the second pole of the first transistor is coupled to a second voltage terminal.

5. The ring voltage controlled oscillator of claim 2, wherein the noise extraction circuit comprises a third resistor and a fourth resistor;

The first end of the third resistor is coupled with the power supply voltage end, and the second end of the third resistor is coupled with the first end of the second resistor and the input end of the amplifier;

the second terminal of the fourth resistor is coupled to the first voltage terminal.

6. The ring voltage controlled oscillator of any one of claims 2-5, wherein the dc voltage reduction circuit comprises a second capacitor and a fifth resistor;

the first end of the second capacitor is coupled with the output end of the amplifier, and the second end of the second capacitor is coupled with the first end of the fifth resistor and the substrate electrode;

the second terminal of the fifth resistor is coupled to the power supply voltage terminal.

7. The ring voltage controlled oscillator of any one of claims 2-6, wherein the amplifier comprises a second transistor, a third transistor, at least one fourth transistor, and a fifth transistor; the second transistor and the fifth transistor are both N-type transistors, and the third transistor and the fourth transistor are both P-type transistors;

the grid electrode of the second transistor is coupled with the input end of the amplifier, the first electrode of the second transistor is coupled with the grid electrode and the second electrode of the third transistor, and the second electrode of the second transistor is coupled with the third voltage end;

The gate of the third transistor is further coupled to the gate of the fourth transistor, and the first pole of the third transistor is coupled to the supply voltage terminal;

a first pole of the fourth transistor is coupled to the supply voltage terminal, and a second pole of the fourth transistor is coupled to the output terminal of the amplifier and the gate and the first pole of the fifth transistor;

a second pole of the fifth transistor is coupled to the third voltage terminal.

8. The ring voltage controlled oscillator of any one of claims 1 to 7, wherein the switching tube is a P-type transistor.

9. The ring voltage controlled oscillator of any one of claims 1 to 8, wherein the oscillating circuit comprises N cascaded inverters, the output of the nth inverter being coupled to the input of the first inverter, the N inverters each being coupled to the second pole of the switching tube;

the output end of the Nth inverter is used for outputting the clock signal, and N is an odd number which is more than or equal to 3.

10. A phase locked loop comprising the ring voltage controlled oscillator of any one of claims 1-9 and a loop filter, an output of the loop filter coupled to a voltage control terminal of the ring voltage controlled oscillator for transmitting a control voltage to the voltage control terminal.

11. An electronic device comprising the phase-locked loop of claim 10 and a circuit board, the phase-locked loop disposed on the circuit board.

12. The driving method of the annular voltage-controlled oscillator is characterized in that the annular voltage-controlled oscillator comprises a switching tube, a noise amplifying circuit and an oscillating circuit;

the driving method of the annular voltage-controlled oscillator comprises the following steps:

the input end of the noise amplifying circuit receives the power supply voltage of the power supply voltage end, amplifies the power supply noise of the power supply voltage, and outputs the amplified power supply noise from the output end to the substrate electrode of the switching tube;

a first pole of the switching tube receives the power supply voltage of the power supply voltage end, and a substrate pole of the switching tube receives the amplified power supply noise; the grid electrode of the switching tube receives the control voltage of the voltage control end, and the switching tube outputs a signal to the oscillating circuit from the second pole of the switching tube under the control of the control voltage;

the oscillating circuit generates a clock signal according to the output of the second pole output of the switching tube.

13. The method according to claim 12, wherein the noise amplifying circuit includes a noise extracting circuit, an amplifier, and a dc voltage restoring circuit;

The input end of the noise amplifying circuit receives the power supply voltage of the power supply voltage end, amplifies the power supply noise of the power supply voltage and outputs the amplified power supply noise to the substrate electrode of the switching tube, and the noise amplifying circuit comprises:

the noise extraction circuit receives the power supply voltage of the power supply voltage end, and transmits the power supply noise to the amplifier after extracting the power supply noise in the power supply voltage;

the amplifier amplifies the received signal and outputs the amplified signal to the direct-current voltage reduction circuit;

the direct-current voltage reduction circuit reduces the received direct-current voltage to the direct-current voltage in the power supply voltage, and transmits the direct-current voltage in the power supply voltage and the received amplified power supply noise to the substrate electrode of the switching tube.

14. The method of driving a ring voltage controlled oscillator of claim 13, wherein the noise extraction circuit comprises a first capacitor and a first resistor;

the noise extraction circuit receives the power supply voltage of the power supply voltage end, and after extracting power supply noise in the power supply voltage, the noise extraction circuit transmits the power supply noise to the amplifier, and the noise extraction circuit comprises:

a first end of the first capacitor receives the power supply voltage of the power supply voltage end, and the power supply noise in the power supply voltage is transmitted to a second end of the first capacitor; the second end of the first resistor receives a signal of a first voltage end and transmits the signal of the first voltage end to the second end of the first capacitor; and the signal of the first voltage end and the power supply noise are used as output signals of the noise extraction circuit and are transmitted to the amplifier.

15. The method of driving a ring voltage controlled oscillator of claim 13, wherein the noise extraction circuit comprises a third resistor and a fourth resistor;

a first end of the third resistor receives the power supply voltage of the power supply voltage end, and a second end of the fourth resistor receives a signal of the first voltage end; the power supply voltage is divided according to the proportion of the third resistor and the fourth resistor; and the signal of the second end of the third resistor is used as an output signal of the noise extraction circuit and is transmitted to the amplifier.

16. The method of driving a ring voltage controlled oscillator according to any one of claims 13 to 15, wherein the dc voltage reduction circuit includes a second capacitor and a fifth resistor;

the direct-current voltage reduction circuit reduces the received direct-current voltage to the direct-current voltage in the power supply voltage, and transmits the direct-current voltage in the power supply voltage and the received amplified power supply noise to a substrate electrode of the switching tube, and the direct-current voltage reduction circuit comprises:

The first end of the second capacitor receives the direct current voltage output by the amplifier and the amplified power supply noise, and the amplified power supply noise is transmitted to the second end of the second capacitor; the second end of the fifth resistor receives the power supply voltage of the power supply voltage end and transmits the power supply voltage to the second end of the second capacitor; and the power supply voltage and the amplified power supply noise are used as output signals of the direct-current voltage reduction circuit and are transmitted to a substrate electrode of the switching tube.