CN116666437B - Shielded gate MOSFET structure, shielded gate power device and preparation method - Google Patents
Shielded gate MOSFET structure, shielded gate power device and preparation method Download PDFInfo
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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Abstract
The invention provides a shielding grid MOSFET structure, a shielding grid power device and a preparation method thereof.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a shielded gate MOSFET structure, a shielded gate power device and a preparation method.
Background
Currently, with the development of semiconductor integrated circuits, a shielded gate (Shield Gate Trench, SGT) MOSFET (Metal Oxide Semiconductor Field Efficient Transistor, MOSFET) can reduce the on-resistance of a conventional trench MOSFET by one half or even one fifth. Conventional trench MOSFETs are designed primarily to increase the trench density of the device to increase the current handling capability of the device, while SGT MOSFETs can reduce the trench density and also reduce the drift region resistance.
As shown in fig. 1, the conventional shielded gate MOSFET structure is a long strip structure having a long strip-shaped body region 4, a source doped region 5, and the like, which makes the on-resistance of the shielded gate MOSFET high.
Disclosure of Invention
The invention aims to provide a shielded gate MOSFET structure which can increase the depletion capability of a device.
Another object of the present invention is to provide a shielded gate power device and a method for manufacturing the same, which can reduce the on-resistance of a shielded gate MOSFET.
In order to solve the above-mentioned problems, the present invention provides a shielded gate MOSFET structure, which includes a source doped region and a cell trench formed in a substrate, wherein the source doped region is located outside the cell trench, a polysilicon gate and a polysilicon source are formed in the cell trench at intervals and are arranged in an insulating manner, the polysilicon gate is arranged outside the polysilicon source in a surrounding manner, and the polysilicon gate and the source doped region are arranged at intervals and are arranged in an insulating manner.
Optionally, the shape of the cellular groove is a central radiation pattern, the central radiation pattern includes a central portion and a radiation portion that are mutually communicated, the radiation portion is located outside the central portion, the central portion is circular, the radiation portion is composed of a plurality of straight line segments wound around the central portion, and the diameter of the central portion is larger than the width of each straight line segment in the radiation portion.
Further, the polysilicon source electrode is located in the central portion, one portion of the polysilicon gate electrode is located in the radiating portion, and the other portion of the polysilicon gate electrode is located in the central portion and is arranged outside the polysilicon source electrode in a surrounding mode.
Optionally, the semiconductor device further comprises a source metal, wherein the source metal is located above the source doped region and the source polysilicon, is respectively communicated with the source polysilicon and the source doped region, and is spaced from the polysilicon gate and is arranged in an insulating manner.
Further, the semiconductor device further comprises a spacing medium layer, a first medium layer and a gate oxide layer, wherein the spacing medium layer covers the surface of the polysilicon gate, the spacing medium layer is provided with a first opening above the source doping region, the first opening exposes the source doping region, the second opening above the source polysilicon is provided with a second opening, and the second opening exposes the source polysilicon, so that the source metal is communicated with the source doping region at the first opening, and is communicated with the source polysilicon at the second opening; the first dielectric layer and the gate oxide layer are formed on the inner wall of the cellular groove, the first dielectric layer is surrounded on the outer side of the polysilicon source electrode layer by layer, and the gate oxide layer is surrounded on the outer side of the polysilicon gate electrode layer by layer.
Further, the shapes of the first opening and the second opening are respectively round or rectangular.
On the other hand, the invention also provides a preparation method of the shielded gate MOSFET structure, which comprises the following steps:
providing a substrate, and forming a cell groove in the substrate;
forming a polysilicon gate and a polysilicon source which are arranged at intervals and are insulated in the cell groove, wherein the polysilicon gate is annularly arranged outside the polysilicon source;
and forming a source doped region in the substrate outside the cell groove, wherein the polysilicon gate is spaced from the source doped region and is arranged in an insulating manner.
Optionally, the shape of the cellular groove is a central radiation pattern, the central radiation pattern includes a central portion and a radiation portion that are mutually communicated, the radiation portion is located outside the central portion, the central portion is circular, the radiation portion is composed of a plurality of straight line segments, and the diameter of the central portion is larger than the width of each straight line segment in the radiation portion.
Further, the method for forming the polysilicon gate and the polysilicon source comprises the following steps:
forming a first dielectric layer, wherein the first dielectric layer fills the radiation part and is deposited on the inner wall of the central part;
forming a polysilicon source in the cell trench of the central portion;
etching the first dielectric layer and forming a gate trench, wherein one part of the gate trench is positioned in the radiation part, and the other part of the gate trench is positioned in the central part;
forming a gate oxide layer on the inner wall of the gate trench;
a polysilicon gate is formed in the gate trench.
Optionally, after forming the source doped region, further includes:
and forming source metal on the substrate, wherein the source metal is positioned above the source doped region and the source polysilicon, is respectively communicated with the source polysilicon and the source doped region, and is arranged at intervals and in an insulating manner with the polysilicon gate.
Further, the method for forming the source metal comprises the following steps:
forming a spacing medium layer on the surface of the substrate, wherein the spacing medium layer covers the polysilicon gate and the polysilicon source electrode, a first opening is formed above the source electrode doping region, the first opening exposes the source electrode doping region, a second opening is formed above the source electrode polysilicon, and the second opening exposes the source electrode polysilicon;
and forming a source metal, wherein the source metal is communicated with the source doped region at the first opening and is communicated with the source polysilicon at the second opening.
Further, the shapes of the first opening and the second opening are respectively round or rectangular.
In still another aspect, the present invention further provides a shielded gate power device, including a plurality of shielded gate MOSFET structures, where all of the shielded gate MOSFET structures are distributed in an array.
Optionally, the shielded gate power device includes a cell region and a terminal region, the terminal region is disposed around the cell region, and the shielded gate MOSFET structure is located in the cell region.
Further, a groove structure is formed in the substrate of the cellular region, the groove structure is composed of a plurality of first grooves which are arranged in parallel and a plurality of second grooves which are arranged in parallel, and the first grooves and the second grooves are vertically intersected, so that the groove structure is a cross-shaped grid structure; or the groove structure consists of a plurality of first grooves which are arranged in parallel, a plurality of second grooves which are arranged in parallel and a plurality of third grooves which are arranged in parallel, wherein the first grooves, the second grooves and the third grooves are arranged in a way of intersecting with each other at the same point, so that the groove structure is a hexagonal grid structure;
wherein, each grid node area of the grid-shaped structure forms a shielding grid MOSFET structure.
Further, the first trench, the second trench and the third trench each have an extension portion extending from the cell region to the terminal region, the terminal region being formed with a gate metal in communication with the polysilicon gate in the extension portion.
In one aspect, the invention provides a method for preparing a shielded gate power device, which comprises the following steps:
providing a substrate;
and forming a plurality of shielding grid MOSFET structures in the substrate, wherein all shielding grid MOSFET structures are distributed in an array.
Optionally, the method for forming the shielding gate MOSFET structure with a plurality of array distributions includes:
forming a groove structure in a substrate of a cellular region, wherein the groove structure consists of a plurality of first grooves which are arranged in parallel and a plurality of second grooves which are arranged in parallel, and the first grooves and the second grooves are vertically intersected, so that the groove structure is a cross-shaped grid structure; or the groove structure consists of a plurality of first grooves which are arranged in parallel, a plurality of second grooves which are arranged in parallel and a plurality of third grooves which are arranged in parallel, wherein the first grooves, the second grooves and the third grooves are arranged in a way of intersecting with each other at the same point, so that the groove structure is a hexagonal grid structure;
forming a polysilicon source electrode and a polysilicon gate electrode in the groove structure, wherein the polysilicon gate electrode is annularly arranged outside the polysilicon source electrode, and the polysilicon gate electrode and the polysilicon source electrode are arranged at intervals and in an insulating manner;
forming a source doped region in the substrate of the cellular region, wherein the source doped region is positioned in a grid surrounded by the grid-shaped structure;
and forming a source metal and a gate metal, wherein the source metal is positioned above the source doped region and the source polysilicon and is respectively communicated with the source doped region and the source polysilicon, and the gate metal is communicated with the polysilicon gate in the extension part in the terminal region.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a shielding grid MOSFET structure, a shielding grid power device and a preparation method thereof. In addition, the shielded gate power device realizes the closest packing effect of cells, increases the channel density and reduces the on-resistance.
Drawings
Fig. 1 is a layout diagram of a conventional shielded gate MOSFET structure;
FIG. 2 is a schematic cross-sectional structure of a conventional SGT;
fig. 3 to fig. 6 are schematic views of a part of a structure of a shielded gate power device according to an embodiment of the present invention;
fig. 7-8 are schematic structural diagrams of source metals with different shapes according to an embodiment of the present invention;
fig. 9 is a schematic diagram of a part of a structure of a shielded gate power device according to an embodiment of the present invention;
FIG. 10 is a schematic perspective view of a substrate according to an embodiment of the present invention;
FIG. 11 is a longitudinal cross-sectional view of a substrate along the line MM' of FIG. 3 according to one embodiment of the present invention;
FIG. 12 is a longitudinal cross-sectional view of a substrate along line MN of the cell of FIG. 3 according to one embodiment of the present invention;
FIG. 13 is a schematic perspective view illustrating a first dielectric layer according to an embodiment of the present invention;
FIG. 14 is a longitudinal cross-sectional view of the cell of FIG. 3 along the line MM' when forming a first dielectric layer according to one embodiment of the present invention;
FIG. 15 is a longitudinal cross-sectional view of the cell of FIG. 3 along line MN when forming a first dielectric layer according to one embodiment of the present invention;
FIG. 16 is a schematic perspective view illustrating a polysilicon source formed according to an embodiment of the invention;
FIG. 17 is a longitudinal cross-sectional view of the cell of FIG. 3 taken along line MM' when a polysilicon source is formed in accordance with one embodiment of the present invention;
FIG. 18 is a longitudinal cross-sectional view of the cell of FIG. 3 along line MN when forming a source of polysilicon according to one embodiment of the present invention;
FIG. 19 is a schematic diagram illustrating a gate trench formed according to an embodiment of the invention;
FIG. 20 is a longitudinal cross-sectional view of the cell of FIG. 3 along the line MM' when forming gate trenches according to one embodiment of the present invention;
FIG. 21 is a longitudinal cross-sectional view of the cell of FIG. 3 along line MN when forming a gate trench in accordance with one embodiment of the present invention;
FIG. 22 is a schematic diagram illustrating a polysilicon gate formed according to an embodiment of the present invention;
FIG. 23 is a longitudinal cross-sectional view of the cell of FIG. 3 taken along line MM' when forming a polysilicon gate in accordance with one embodiment of the present invention;
FIG. 24 is a longitudinal cross-sectional view of the cell of FIG. 3 along line MN when forming a polysilicon gate in accordance with one embodiment of the present invention;
fig. 25 is a schematic perspective view of a shielded gate MOSFET structure according to an embodiment of the invention;
FIG. 26 is a longitudinal cross-sectional view of a shielded gate MOSFET structure according to an embodiment of the present invention along the MM' line of the cell of FIG. 3;
FIG. 27 is a longitudinal cross-sectional view of a shielded gate MOSFET structure according to an embodiment of the present invention taken along line MN of the cell of FIG. 3;
fig. 28 is a graph of an Id-BV curve of a shielded gate MOSFET structure according to an embodiment of the invention.
Wherein, in fig. 1-2:
1-source metal; 2-polysilicon source; 3-polysilicon gate; 4-body region; a 5-source doped region;
fig. 3-28:
i-cell region; a II-terminal region; 10-shielded gate MOSFET structure; 11-gate metal; 100-a substrate; 101-cell grooves; 102-a first trench; 103-a second trench; 104-a third trench; 105-gate trenches; 110-body region; 120-source doped regions; 130-a first dielectric layer; 210-polysilicon source; 220-polysilicon gate; 300-a spacer dielectric layer; 310-a first opening; 400-source metal.
Detailed Description
A shielded gate MOSFET structure, a shielded gate power device, and a method of making the same of the present invention will be described in further detail below. The present invention will be described in more detail below with reference to the attached drawings, in which preferred embodiments of the present invention are shown, it being understood that one skilled in the art can modify the present invention described herein while still achieving the advantageous effects of the present invention. Accordingly, the following description is to be construed as broadly known to those skilled in the art and not as limiting the invention.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It should be appreciated that in the development of any such actual embodiment, numerous implementation details must be made to achieve the developer's specific goals, such as compliance with system-related or business-related constraints, which will vary from one implementation to another. In addition, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
In order to make the objects and features of the present invention more comprehensible, embodiments accompanied with figures are described in detail below. It is noted that the drawings are in a very simplified form and utilize non-precise ratios, and are intended to facilitate a convenient, clear, description of the embodiments of the invention.
Referring to fig. 2, referring to fig. 1, a conventional SGT (shielded gate trench field effect transistor) includes a trench formed in a substrate, a dielectric layer is deposited on a sidewall of the trench, a polysilicon source 2 is filled in the trench inside the dielectric layer, a polysilicon gate 3 is embedded in the dielectric layer, the polysilicon gate 3 is spaced apart and arranged outside the polysilicon source 2 in an insulating manner, a body region 4 and a source doped region 5 are formed in the substrate outside the polysilicon gate 3, the source doped region 5 is located in the body region 4 and is arranged close to a surface of the substrate, the dielectric layer exposes the polysilicon source 2 and the source doped region 5, a source metal 1 is formed on the substrate, and the polysilicon source metal 1 is respectively communicated with the source doped region 5 and the polysilicon source 2. The trench density of a conventional SGT is low and the on-resistance is high.
Referring to fig. 3-6, and referring to fig. 25-27, the present embodiment provides a shielded gate MOSFET structure 10, where the shielded gate MOSFET structure 10 includes a source doped region 120 and a cell trench 101 formed in a substrate 100, the source doped region 120 is located outside the cell trench 101, a polysilicon gate 220 and a polysilicon source 210 are formed in the cell trench 101, the polysilicon gate 220 is disposed around the polysilicon source 210, and the polysilicon gate 220 is disposed at a distance from the source doped region 110 and is insulated. The shielded gate MOSFET structure 10 further includes a body region 110, the source doped region 120 is located in the body region 110, and the source doped region 120 is disposed proximate to the substrate surface.
The shape of the cell groove 101 is a central radiation pattern, for example, a cross-shaped central radiation pattern (as shown in fig. 3-5), a hexagram-shaped central radiation pattern (as shown in fig. 6). The central radiation pattern comprises a central part and a radiation part which are communicated with each other, the radiation part is positioned outside the central part, the central part is round, the radiation part consists of a plurality of straight line segments wound around the central part, and the diameter of the central part is larger than the width of each straight line segment in the radiation part. The polysilicon source 210 is located at the central portion, and the polysilicon gate 220 has a portion located at the radiating portion and another portion located at the central portion and is disposed around the outside of the polysilicon source 210.
The shielded gate MOSFET structure 10 further includes a source metal 400, where the source metal 400 is located above the source doped region 120 and the source polysilicon 210, is in communication with the source polysilicon 210 and the source doped region 120, and is spaced apart from and insulated from the polysilicon gate 220.
The shielded Gate MOSFET structure 10 further includes a spacer dielectric layer 300, a first dielectric layer 130, and a Gate Oxide layer (Gate Oxide), where the spacer dielectric layer 300 covers the surface of the polysilicon Gate 220 to insulate the source metal 400 from the polysilicon Gate 220; the spacer dielectric layer 300 has a first opening 310 over the source doped region 120, the first opening 310 exposing the source doped region 120, and a second opening (not shown) over the source polysilicon 210, the second opening exposing the source polysilicon 210. The source metal 400 fills the first opening 310 and the second opening and covers a portion of the surface of the spacer dielectric layer 300 such that the source metal 400 communicates with the source doped region 120 at the first opening 310 and with the source polysilicon 210 at the second opening.
The cross-sectional shapes of the first opening 310 and the second opening may be regular patterns such as a rectangle, a circle, etc., and the cross-sectional shapes of the first opening 310 and the second opening may be the same (i.e., both rectangular and circular) or may be different (e.g., the cross-sectional shape of the first opening 310 is a circle, and the cross-sectional shape of the second opening is a square).
In this embodiment, the first opening 310 and the second opening have the same cross-sectional shape, for example, are rectangular, and are square with an inner arc chamfer as shown in fig. 3, square as shown in fig. 7, or circular as shown in fig. 8. Of course, the cross-sectional shapes of the first opening 310 and the second opening may be other regular patterns.
The first dielectric layer 130 and the gate oxide layer are formed on the inner walls (side walls and bottom wall) of the cellular trench 101, and the first dielectric layer 130 is enclosed outside the polysilicon source 210, and the gate oxide layer is enclosed outside the polysilicon gate 220, so that the polysilicon source 210 and the polysilicon gate 220 are insulated and arranged at intervals.
Compared with the conventional two-dimensional cell layout (i.e., the strip-shaped shielded gate MOSFET structure 10), the three-dimensional cell layout of the present embodiment makes use of the three-dimensional charge compensation effect, thereby enhancing the depletion capability of the shielded gate power device.
The embodiment also provides a preparation method of the shielded gate MOSFET structure 10, which comprises the following steps:
step S11: providing a substrate 100, and forming a cell trench 101 in the substrate 100;
step S12: forming a polysilicon gate 220 and a polysilicon source 210 which are arranged at intervals and are insulated in the cell groove 101, wherein the polysilicon gate 220 is arranged on the outer side of the polysilicon source 210 in a surrounding manner;
step S13: forming a source doped region 120 in the substrate 100 outside the cell trench 101, the polysilicon gate 220 being spaced apart from the source doped region 120 and being insulated;
step S14: a source metal 400 is formed on the substrate 100, the source metal 400 being located above the source doped region 120 and the polysilicon source 210 and in communication with the source doped region 120 and the polysilicon source 210, respectively, and spaced apart and insulated from the polysilicon gate 220.
A method for manufacturing the shielded gate MOSFET structure 10 according to this embodiment is described in detail below with reference to the accompanying drawings.
As shown in fig. 10 to 12, step S11 is first performed to provide a substrate 100, and a cell trench 101 is formed in the substrate 100.
The method specifically comprises the following steps:
first, a substrate 100 is provided. The substrate 100 includes a base and an epitaxial layer on the base. The material of the substrate comprises a semiconductor material including silicon, silicon carbide, silicon germanium, a multi-element semiconductor material of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). Wherein the III-V element comprises a multi-component semiconductor material comprising InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP. In this embodiment, the material of the substrate includes silicon, and the material of the epitaxial layer includes silicon.
Next, a cell trench 101 is formed in the substrate 100. In detail, a cell trench 101 is formed in the substrate 100 through an etching process.
The shape of the cell groove is a central radiation pattern, the central radiation pattern comprises a central part and a radiation part which are communicated with each other, the radiation part is positioned outside the central part, the central part is circular, the radiation part consists of a plurality of straight line segments wound around the central part, and the diameter of the central part is larger than the width of each straight line segment in the radiation part.
Next, step S12 is performed, in which a polysilicon gate 220 and a polysilicon source 210 are formed in the cell trench 101 at intervals and are arranged in an insulating manner, and the polysilicon gate 220 is arranged around the outside of the polysilicon source 210.
The method specifically comprises the following steps:
as shown in fig. 13 to 15, first, a first dielectric layer 130 is deposited on the inner walls (i.e., the side walls and the bottom wall) of the cell trench 101, the first dielectric layer 130 fills the radiation portion and is deposited on the inner wall of the central portion, and the first dielectric layer 130 also covers the surface of the substrate 100.
As shown in fig. 16-18, a polysilicon material layer is then deposited in the cell trench 101 and the polysilicon material layer and the first dielectric layer 130 are etched to expose the substrate outside the cell trench 101 to form a polysilicon source 210.
Referring to fig. 19-21, referring to fig. 3b, the first dielectric layer 130 is etched to form a gate trench 105, wherein a portion of the gate trench 105 is located in the radiation portion and another portion is located in the central portion. Wherein the depth of the gate trench 105 is smaller than the depth of the cell trench 101.
Next, a Gate Oxide layer (Gate Oxide) is formed on the inner walls (sidewalls and bottom wall) of the Gate trench 105 to avoid the polysilicon Gate 220 formed in the subsequent Gate trench 105 from communicating with the polysilicon source 210 and the source doped region 120, respectively.
As shown in fig. 22-24, a layer of polysilicon material is then deposited in the gate oxide surface and etched until the substrate outside the cell trench is exposed to form a polysilicon gate 220.
With continued reference to fig. 22-24, step S13 is performed, and step S13 is performed to form a source doped region 120 in the substrate 100 outside the cell trench 101. In detail, a body region 110 and a source doped region 120 are sequentially formed in the substrate 100 outside the cell trench 101, wherein the source doped region 120 is located in the body region 110 and is disposed close to the substrate surface.
As shown in fig. 25-27, step S14 is performed, and a source metal 400 is formed on the substrate 100, wherein the source metal 400 is located above the source doped region 120 and the polysilicon source 210, is respectively in communication with the source doped region 120 and the polysilicon source 210, and is spaced apart from and insulated from the polysilicon gate 220.
The method specifically comprises the following steps:
first, a spacer dielectric layer 300 is formed on the surface of the substrate 100, where the spacer dielectric layer 300 covers the polysilicon gate 220, the polysilicon source 210 and the source doped region 120, and has a first opening 310 above the source doped region 120, the first opening 310 exposes the source doped region 120, and a second opening above the source polysilicon 210, and the second opening exposes the source polysilicon 210.
Next, a source metal 400 is formed. In detail, the source metal 400 communicates with the source doped region 120 at the first opening 310 and communicates with the source polysilicon 210 at the second opening.
In fig. 28, a curve a is an Id-BV curve of the conventional shielded gate MOSFET structure 10 in fig. 2, and b curve b is an Id-BV curve of the shielded gate MOSFET structure 10 of the present embodiment. As can be seen from the figure, the shielded gate MOSFET structure 10 of the present embodiment has a larger current at the same voltage, that is, the on-capacitance Ron of the shielded gate MOSFET structure 10 of the present embodiment is smaller.
As shown in fig. 9, the present embodiment further provides a shielded gate power device, which includes a cell area I and a terminal area II, where the terminal area II is disposed around the cell area I. The cell region I is formed with a plurality of the shielded gate MOSFET structures 10 distributed in an array.
The termination region II is formed with a gate electrode in communication with the polysilicon gate 220 of the cell region I adjacent to the termination region II. Compared with the traditional two-dimensional cell layout (namely the strip-shaped shielding gate MOSFET structure), the three-dimensional cell layout of the embodiment enables the embodiment to utilize the three-dimensional charge compensation effect and enhances the depletion capability of the shielding gate power device. At the same time, the array of distributed cell trenches 101 achieves the closest packing effect, increasing the channel density, resulting in a decrease in on-resistance (e.g., 25%).
With continued reference to fig. 4, in the present embodiment, a trench structure is formed in the substrate 100 of the cellular region I, where the trench structure is composed of a plurality of first trenches 102 arranged in parallel and a plurality of second trenches 103 arranged in parallel, and the first trenches 102 and the second trenches 103 are vertically intersected and arranged, so that the trench structure is a cross-shaped grid structure. The groove structure may further comprise a plurality of first grooves 102 arranged in parallel, a plurality of second grooves 103 arranged in parallel, and a plurality of third grooves 104 arranged in parallel, where the first grooves 102, the second grooves 103, and the third grooves 104 are arranged to intersect at the same point, so that the groove structure is a grid structure of a hexagonal star shape. Wherein a said shielded gate MOSFET structure 10 is formed at each grid node area of said grid-like structure.
The cross sections of the first groove 102 and the second groove 103 at the intersection point are circular, and the cross sections of the first groove 102 and the second groove 103 outside the intersection point are long.
The first trench 102, the second trench 103 and the third trench 104 each have an extension extending from the cellular region I to the terminal region II, the terminal region II being formed with a gate metal in communication with the polysilicon gate in the extension.
The embodiment provides a preparation method of a shielded gate power device, which comprises the following steps:
step S21: providing a substrate 100;
step S22: a plurality of array distributed shielded gate MOSFET structures 10 are formed in the cell region I.
The step S22 specifically includes:
firstly, in a substrate 100 of a cellular region I, a groove structure is formed by a plurality of first grooves 102 which are arranged in parallel and a plurality of second grooves 103 which are arranged in parallel, wherein the first grooves 102 and the second grooves 103 are vertically intersected, so that the groove structure is a cross-shaped grid structure; or, the groove structure is formed by a plurality of first grooves 102 which are arranged in parallel, a plurality of second grooves 103 which are arranged in parallel and a plurality of third grooves 104 which are arranged in parallel, and the first grooves 102, the second grooves 103 and the third grooves 104 are arranged in a same point and intersect, so that the groove structure is a grid structure of a hexagonal star shape.
Next, a body region 110 and a source doped region 120 are sequentially formed in the substrate 100 of the cell region I, the source doped region 120 is located in the body region 110, the source doped region 120 is disposed near the surface of the substrate, and the body region 110 and the source doped region 120 are located in a grid surrounded by the grid structure.
Next, a source metal 400 and a gate metal 11 are formed, the source metal 400 being located above the source doped region 120 and the source polysilicon 210 and in communication with the source doped region 120 and the source polysilicon 210, respectively, the gate metal 11 being located in the termination region II and in communication with the extension of the polysilicon gate 220.
In summary, the present invention provides a shielded gate MOSFET structure, a shielded gate power device, and a method for manufacturing the same, where the shielded gate MOSFET structure includes a source doped region and a cell trench formed in a substrate, the source doped region is located outside the cell trench, a polysilicon gate and a polysilicon source are formed in the cell trench, the polysilicon gate is disposed around the polysilicon source, and the polysilicon gate and the source doped region are disposed at intervals and are insulated, so as to enhance the depletion capability of the device, and reduce the on-resistance. In addition, the shielded gate power device realizes the closest packing effect of cells, increases the channel density and reduces the on-resistance.
Furthermore, unless specifically stated or indicated otherwise, the description of the terms "first," "second," and the like in the specification merely serve to distinguish between various components, elements, steps, etc. in the specification, and do not necessarily represent a logical or sequential relationship between various components, elements, steps, etc.
It will be appreciated that although the invention has been described above in terms of preferred embodiments, the above embodiments are not intended to limit the invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.
Claims (17)
1. A shielded gate MOSFET structure, comprising a source doped region and a cell trench formed in a substrate, wherein the source doped region is positioned outside the cell trench, the cell trench is shaped as a central radiation pattern, the central radiation pattern comprises a central part and a radiation part which are communicated with each other, the radiation part is positioned outside the central part, the central part is circular, and the radiation part is composed of a plurality of straight line segments wound around the central part;
the cell groove is internally provided with a polysilicon gate and a polysilicon source which are arranged at intervals in an insulating manner, the polysilicon source is positioned at the central part, one part of the polysilicon gate is positioned at the radiation part, the other part of the polysilicon gate is positioned at the central part and is arranged at the outer side of the polysilicon source in a surrounding manner, and the polysilicon gate and the source doping area are arranged at intervals in an insulating manner.
2. The shielded gate MOSFET structure of claim 1 wherein said central portion has a diameter greater than a width of each straight segment in said radiating portion.
3. The shielded gate MOSFET structure of claim 1 further comprising a source metal overlying the source doped region and the polysilicon source and in communication with the polysilicon source and source doped region, respectively, and spaced apart from and insulated from the polysilicon gate.
4. The shielded gate MOSFET structure of claim 3 further comprising a spacer dielectric layer, a first dielectric layer, and a gate oxide layer, said spacer dielectric layer covering a surface of said polysilicon gate, and said spacer dielectric layer having a first opening over said source doped region, said first opening exposing said source doped region, and a second opening over said polysilicon source, said second opening exposing said polysilicon source such that said source metal communicates with said source doped region at said first opening and with said polysilicon source at said second opening; the first dielectric layer and the gate oxide layer are formed on the inner wall of the cellular groove, the first dielectric layer is surrounded on the outer side of the polysilicon source electrode layer by layer, and the gate oxide layer is surrounded on the outer side of the polysilicon gate electrode layer by layer.
5. The shielded gate MOSFET structure of claim 4 wherein the first opening and the second opening are each circular or rectangular in shape.
6. The preparation method of the shielded gate MOSFET structure is characterized by comprising the following steps of:
providing a substrate, and forming a cell groove in the substrate, wherein the cell groove is shaped as a central radiation pattern, the central radiation pattern comprises a central part and a radiation part which are mutually communicated, the radiation part is positioned outside the central part, the central part is circular, and the radiation part consists of a plurality of straight line segments;
forming a polysilicon gate and a polysilicon source which are arranged at intervals and are insulated in the cell groove, wherein the polysilicon source is positioned at the central part, one part of the polysilicon gate is positioned at the radiation part, the other part of the polysilicon gate is positioned at the central part, and the polysilicon gate is annularly arranged outside the polysilicon source;
and forming a source doped region in the substrate outside the cell groove, wherein the polysilicon gate is spaced from the source doped region and is arranged in an insulating manner.
7. The method of fabricating a shielded gate MOSFET structure of claim 6 wherein said central portion has a diameter greater than a width of each straight segment in said radiating portion.
8. The method of manufacturing a shielded gate MOSFET structure of claim 7, wherein the method of forming a polysilicon gate and a polysilicon source comprises:
forming a first dielectric layer, wherein the first dielectric layer fills the radiation part and is deposited on the inner wall of the central part;
forming a polysilicon source in the cell trench of the central portion;
etching the first dielectric layer and forming a gate trench, wherein one part of the gate trench is positioned in the radiation part, and the other part of the gate trench is positioned in the central part;
forming a gate oxide layer on the inner wall of the gate trench;
a polysilicon gate is formed in the gate trench.
9. The method of manufacturing a shielded gate MOSFET structure of claim 6, further comprising, after forming the source doped region:
and forming source metal, wherein the source metal is positioned above the source doped region and the polysilicon source, is respectively communicated with the polysilicon source and the source doped region, and is arranged at intervals and in an insulating manner with the polysilicon gate.
10. The method of manufacturing a shielded gate MOSFET structure of claim 9 wherein the method of forming the source metal comprises:
forming a spacing medium layer on the surface of the substrate, wherein the spacing medium layer covers the polysilicon gate, a first opening is formed above the source doping region, the first opening exposes the source doping region, a second opening is formed above the polysilicon source, and the second opening exposes the polysilicon source;
and forming a source metal, wherein the source metal is communicated with the source doped region at the first opening and is communicated with the polysilicon source at the second opening.
11. The method of manufacturing a shielded gate MOSFET structure of claim 10, wherein the first opening and the second opening are each circular or rectangular in shape.
12. A shielded gate power device comprising a plurality of shielded gate MOSFET structures according to any one of claims 1-5, all of said shielded gate MOSFET structure being distributed in an array.
13. The shielded gate power device of claim 12 wherein the shielded gate power device includes a cell region and a termination region, the termination region disposed around the cell region, and the shielded gate MOSFET structure is located in the cell region.
14. The shielded gate power device of claim 13, wherein a trench structure is formed in the substrate of the cell region, the trench structure being composed of a plurality of first trenches arranged in parallel and a plurality of second trenches arranged in parallel, the first trenches and the second trenches being arranged to intersect vertically such that the trench structure is a cross-shaped grid structure; or the groove structure consists of a plurality of first grooves which are arranged in parallel, a plurality of second grooves which are arranged in parallel and a plurality of third grooves which are arranged in parallel, wherein the first grooves, the second grooves and the third grooves are arranged in a way of intersecting with each other at the same point, so that the groove structure is a hexagonal grid structure;
wherein, each grid node area of the grid-shaped structure forms a shielding grid MOSFET structure.
15. The shielded gate power device of claim 14 wherein the first trench, the second trench, and the third trench each have an extension that extends from the cell region to the termination region, the termination region being formed with a gate metal that communicates with the polysilicon gate in the extension.
16. The preparation method of the shielded gate power device is characterized by comprising the following steps of:
providing a substrate;
forming a plurality of shielded gate MOSFET structures according to any one of claims 1-5 in the substrate, wherein all the shielded gate MOSFET structures are distributed in an array.
17. The method of manufacturing a shielded gate power device of claim 16, wherein the method of forming a plurality of array distributed shielded gate MOSFET structures comprises:
forming a groove structure in a substrate of a cellular region, wherein the groove structure consists of a plurality of first grooves which are arranged in parallel and a plurality of second grooves which are arranged in parallel, and the first grooves and the second grooves are vertically intersected, so that the groove structure is a cross-shaped grid structure; or the groove structure consists of a plurality of first grooves which are arranged in parallel, a plurality of second grooves which are arranged in parallel and a plurality of third grooves which are arranged in parallel, wherein the first grooves, the second grooves and the third grooves are arranged in a way of intersecting with each other at the same point, so that the groove structure is a hexagonal grid structure;
forming a polysilicon source electrode and a polysilicon gate electrode in the groove structure, wherein the polysilicon gate electrode is annularly arranged outside the polysilicon source electrode, and the polysilicon gate electrode and the polysilicon source electrode are arranged at intervals and in an insulating manner;
forming a source doped region in the substrate of the cellular region, wherein the source doped region is positioned in a grid surrounded by the grid-shaped structure;
and forming a source metal and a gate metal, wherein the source metal is positioned above the source doped region and the polysilicon source and is respectively communicated with the source doped region and the polysilicon source, the gate metal is positioned in a terminal region, and the first groove, the second groove and the third groove are respectively provided with an extension part, and the extension parts extend from the cell region to the terminal region and are communicated with the polysilicon gate in the extension parts.
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| CN106876472A (en) * | 2017-04-19 | 2017-06-20 | 无锡新洁能股份有限公司 | A kind of Charged Couple power MOSFET device and its manufacture method |
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| CN106098626A (en) * | 2015-04-30 | 2016-11-09 | 英飞凌科技奥地利有限公司 | Semiconductor device and there is the field dielectric trench field plate field-effect transistor including thermally grown part and deposition fraction |
| CN106876472A (en) * | 2017-04-19 | 2017-06-20 | 无锡新洁能股份有限公司 | A kind of Charged Couple power MOSFET device and its manufacture method |
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