CN116666352B - Back-side power supply chip packaging structure and preparation method thereof - Google Patents
Back-side power supply chip packaging structure and preparation method thereof Download PDFInfo
- Publication number
- CN116666352B CN116666352B CN202310943260.1A CN202310943260A CN116666352B CN 116666352 B CN116666352 B CN 116666352B CN 202310943260 A CN202310943260 A CN 202310943260A CN 116666352 B CN116666352 B CN 116666352B
- Authority
- CN
- China
- Prior art keywords
- layer
- chip
- power
- substrate
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 25
- 238000002360 preparation method Methods 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 93
- 230000005540 biological transmission Effects 0.000 claims abstract description 56
- 230000008054 signal transmission Effects 0.000 claims abstract description 42
- 229910052751 metal Inorganic materials 0.000 claims description 48
- 239000002184 metal Substances 0.000 claims description 48
- 238000001746 injection moulding Methods 0.000 claims description 35
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 33
- 229910052710 silicon Inorganic materials 0.000 claims description 33
- 239000010703 silicon Substances 0.000 claims description 33
- 229910000679 solder Inorganic materials 0.000 claims description 28
- 238000000151 deposition Methods 0.000 claims description 27
- 230000008021 deposition Effects 0.000 claims description 27
- 239000004033 plastic Substances 0.000 claims description 18
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 10
- 239000010949 copper Substances 0.000 claims description 10
- 230000000149 penetrating effect Effects 0.000 claims description 6
- 238000007789 sealing Methods 0.000 claims description 5
- 238000000605 extraction Methods 0.000 claims description 3
- 238000003466 welding Methods 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 229910001128 Sn alloy Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000011135 tin Substances 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
- H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Structure Of Printed Boards (AREA)
Abstract
The application provides a chip packaging structure for back power supply and a preparation method thereof. The plurality of chip units are arranged along the plane direction, the signal transmission layers of the plurality of chip units are interconnected through the first wiring layer positioned above the signal transmission layers, and the power transmission layers of the plurality of chip units are interconnected through the second wiring layer or the interconnection substrate positioned below the power transmission layers. The chip packaging structure interconnects the plurality of chip units, improves the device performance of the whole packaging structure, separates the power transmission layer and the signal transmission layer on two sides of the chip, shortens the conduction path of electric power and avoids the generation of voltage drop. Meanwhile, the size of the whole packaging structure is reduced, the stress balance effect can be achieved structurally, and the warping risk is effectively reduced.
Description
Technical Field
The application relates to the technical field of semiconductor packaging, in particular to a chip packaging structure with back power supply and a preparation method thereof.
Background
In conventional 2.5D or 3D advanced packaging, the signal lines and power lines are typically routed on the front side of the wafer, vertically stacked and connected to form a semiconductor device of two or more layers of active electronic components of an integrated circuit. The power supply network is formed by supplying power to the chips through the power lines. However, in the front area of the chip, there is a signal network formed by signal lines, as shown in fig. 1, the signal network layer 11 and the power supply network layer 12 are both located on the same surface of the chip body 10, and the power supply network is fabricated on the front area of the chip, which means that the power supply network and the signal network in the chip must share the same component space, and the power supply network often occupies a larger space, so that the volume of the whole package structure is difficult to be further reduced. Meanwhile, the power supply network layer 12 is far from the chip body 10, and for a three-dimensional package structure with increased chip density, a high IR drop may occur, which may lead to increased power consumption and reduced device performance.
In addition, when a plurality of chips are packaged along a planar arrangement, as shown in fig. 2, since the signal network layer 11 and the power supply network layer 12 are located on the same side, the signal lines and the power lines are located on the same side of the chips, so that the line density is too high, and the 2.5D adapter plate 112 is required to perform line expansion and then is attached to the substrate 111. In the whole packaging structure, a power supply is input by the substrate 111, is shunted through a power signal wiring of the 2.5D adapter plate 112, passes through the power supply network layer 12 and the signal network layer 11, and is finally conducted to a transistor of the chip main body 10, and the wiring way is too long in path, so that the voltage drop is too serious.
Therefore, the industry is beginning to explore the possibility of transferring the power supply network to the back side, making back side PDN a popular technical issue. Based on the back side power supply technology, how to further optimize the package structure and shorten the conduction path of the power supply so as to improve the performance of the device and reduce the power consumption becomes another difficulty facing the technicians.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present application is to provide a chip package structure and a method for manufacturing the same, which are used for improving chip density, shortening conductive paths of a power supply, and reducing power consumption.
In order to achieve the above object, the present application provides a back side power supply chip package structure, including:
the chip unit comprises a power supply connecting layer, a silicon deposition layer, a buried power layer, a dielectric layer and a signal connecting layer which are sequentially stacked from bottom to top; a plurality of transistors electrically connected with the embedded power layer are formed in the dielectric layer, and metal wires are formed in the signal connection layer so as to realize signal connection with the transistors; forming a plurality of penetrating metal columns in the silicon deposition layer, wherein the metal columns are electrically connected with metal wires of the power supply connecting layer; the power supply connection layer and the signal connection layer are respectively formed on the surfaces of the power supply connection layer and the signal connection layer, and a bump serving as a power supply channel is formed in the power supply transmission layer and the signal transmission layer;
the plurality of chip units are arranged along the plane direction, the signal transmission layers of the plurality of chip units are interconnected through the first wiring layer positioned above the signal transmission layers, and the power transmission layers of the plurality of chip units are interconnected through the second wiring layer or the interconnection substrate positioned below the power transmission layers.
Preferably, when the power transmission layers of the plurality of chip units are interconnected by the second wiring layer located therebelow, the chip package structure further includes:
the plastic layer is positioned on the second wiring layer and coats the side wall of the chip unit, and the first wiring layer is positioned on the upper surface of the plastic layer;
and a conductive substrate soldered to a lower surface of the second wiring layer by means of solder balls.
Preferably, when the power transmission layers of the plurality of chip units are interconnected by the interconnection substrate located thereunder, the chip package structure further includes:
the first injection molding layer is positioned on the interconnection substrate and coats the side wall of the solder ball and the side wall of the lower part of the chip unit;
the second injection molding layer is positioned on the interconnection substrate and coats the side wall of the first wiring layer, the side wall of the first injection molding layer and the side wall of the upper part of the chip unit.
Preferably, solder balls are also fixed on the lower surfaces of the conductive substrate and the interconnection substrate, respectively.
Preferably, the power connection layer and the signal connection layer are formed based on a copper damascene process.
The application also provides a preparation method of the back-side power supply chip packaging structure, which comprises the following steps:
s1: providing a chip unit, wherein the chip unit comprises a power supply connection layer, a silicon deposition layer, a buried power layer, a dielectric layer and a signal connection layer which are sequentially stacked from bottom to top, a plurality of transistors electrically connected with the buried power layer are formed in the dielectric layer, and metal wires are formed in the signal connection layer so as to realize signal connection with the transistors; forming a plurality of penetrating metal columns in the silicon deposition layer, wherein the metal columns are electrically connected with metal wires of the power supply connecting layer;
s2: forming a power transmission layer and a signal transmission layer on the surfaces of the power connection layer and the signal connection layer of the chip unit respectively, wherein a bump is formed in the power transmission layer and the signal transmission layer to serve as a power supply channel;
s3: the plurality of chip units are arranged along the plane direction, the signal transmission layers of the plurality of chip units are interconnected through the first wiring layer positioned above the signal transmission layers, and the power transmission layers of the plurality of chip units are interconnected through the second wiring layer or the interconnection substrate positioned below the power transmission layers.
Preferably, the process of preparing the chip unit in step S1 specifically includes:
s1-1: providing a first substrate, sequentially forming a power supply connecting layer and a silicon deposition layer on the first substrate, and forming a plurality of penetrating metal columns in the silicon deposition layer, wherein the metal columns are electrically connected with metal wires of the power supply connecting layer;
s1-2: forming a buried power layer and a dielectric layer on the surface of the silicon deposition layer in sequence, wherein a plurality of transistors electrically connected with the buried power layer are formed in the dielectric layer, and the buried power layer is used as a power supply channel of the transistors;
s1-3: forming a signal connection layer on the surface of the dielectric layer, which is far away from the substrate, and removing the first substrate; and metal wires are formed in the signal connection layer so as to realize signal connection with the transistors.
Preferably, when the power transmission layers of the plurality of chip units are interconnected by the second wiring layer located therebelow, S3 specifically includes:
s31: providing a supporting substrate, wherein a stripping layer and a first wiring layer are sequentially formed on the supporting substrate, a plurality of chip units are placed on the first wiring layer along the plane direction, and a signal transmission layer is electrically contacted with the first wiring layer;
s32: forming a plastic layer through an injection molding process, wherein the plastic layer is positioned on the first wiring layer and coats the side wall of the chip unit;
s33: forming a second wiring layer on the plastic sealing layer, wherein the second wiring layer is in electrical contact with the power transmission layer;
s34: forming solder balls on the second wiring layer, and then separating the support substrate based on the peeling layer;
s35: the whole structure is turned over so that the second wiring layer is located below and soldered to the conductive substrate by solder balls for electrical extraction.
Preferably, when the power transmission layers of the plurality of chip units are interconnected through the interconnection substrate located therebelow, S3 specifically includes:
s3a: fixing a power transmission layer of the chip unit to the interconnection substrate through solder balls;
s3b: forming a first injection molding layer on the interconnection substrate through an injection molding process, wherein the first injection molding layer coats the side wall of the solder ball and the side wall of the lower part of the chip unit;
s3c: arranging a first wiring layer above the chip unit signal transmission layer, and welding solder balls below the interconnection substrate;
s3d: and forming a second injection molding layer on the interconnection substrate through an injection molding process, wherein the second injection molding layer covers the side wall of the first wiring layer, the side wall of the first injection molding layer and the side wall of the upper part of the chip unit.
Preferably, the power connection layer and the signal connection layer are formed based on a copper damascene process.
As described above, the present application provides a chip package structure for backside power supply and a method for manufacturing the same, the chip package structure comprising a chip unit including a power connection layer, a silicon deposition layer, a buried power layer, a dielectric layer and a signal connection layer stacked in this order from bottom to top; a plurality of transistors electrically connected with the embedded power layer are formed in the dielectric layer, metal wires are formed in the signal connection layer so as to realize signal connection with the transistors, and a power transmission layer and a signal transmission layer are respectively formed on the surfaces of the power connection layer and the signal connection layer. The plurality of chip units are arranged along the plane direction, the signal transmission layers of the plurality of chip units are interconnected through the first wiring layer positioned above the signal transmission layers, and the power transmission layers of the plurality of chip units are interconnected through the second wiring layer or the interconnection substrate positioned below the power transmission layers.
The chip packaging structure interconnects the plurality of chip units, improves the device performance of the whole packaging structure, and simultaneously, based on the back power supply technology, the power transmission layer and the signal transmission layer are respectively arranged on two sides of the chip, so that the conduction path of electric power is shortened, and the generation of voltage drop is avoided. Meanwhile, the design of the two sides can release the design space of the front circuit, the size of the whole packaging structure is reduced, the power line and the signal line are arranged on the two sides, the stress balance effect can be achieved structurally, and the warping risk is reduced effectively.
Drawings
Fig. 1 shows a schematic diagram of a prior art chip unit.
Fig. 2 is a schematic diagram of a prior art chip package structure.
Fig. 3 is a schematic view showing a structure of forming a power connection layer.
Fig. 4 is a schematic view showing a structure of forming a silicon deposition layer.
FIG. 5 is a schematic diagram showing the structure of forming the buried power layer and the dielectric layer.
Fig. 6 is a schematic diagram showing a structure of forming a signal connection layer.
Fig. 7 is a schematic diagram showing a structure of forming a power transmission layer and a signal transmission layer.
Fig. 8 is a schematic view showing a structure in which a chip unit is placed on a first wiring layer.
Fig. 9 is a schematic structural diagram showing a molding layer formed on the first wiring layer.
Fig. 10 is a schematic structural diagram showing a second wiring layer formed on the molding layer.
Fig. 11 is a schematic view showing a structure of a conductive substrate bonded by solder balls.
Fig. 12 is a schematic view showing a structure in which a chip unit is fixed to an interconnect substrate by solder balls.
Fig. 13 is a schematic view showing a structure of forming a first injection-molded layer on an interconnection substrate.
Fig. 14 is a schematic view showing a structure in which a first wiring layer is provided over a chip unit.
Fig. 15 shows a schematic structure of forming the second injection layer.
Fig. 16 is a schematic diagram of a chip package structure according to the present application.
Description of element reference numerals
101-a first substrate; 102-a power connection layer; 103-a silicon deposition layer; 104-a buried power layer; 105-a dielectric layer; 106-a signal connection layer; 107-a signal transmission layer; 108-a power transmission layer; 201-supporting a substrate; 202-a release layer; 203-a first wiring layer; 204-a second wiring layer; 300-plastic sealing layer; 301-a first injection layer; 302-a second injection layer; 401-a conductive substrate; 402-an interconnect substrate; 17-bump; a 21-transistor; 23-solder balls; 31-metal columns.
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application.
As described in detail in the embodiments of the present application, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present. As used herein, "between … …" is meant to include both endpoints.
In the context of the present application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be changed at will, and the layout of the components may be more complex.
The application provides a preparation method of a back-side power supply chip packaging structure, which specifically comprises the following steps:
s1: providing a chip unit, as shown in fig. 6, comprising a power connection layer 102, a silicon deposition layer 103, a buried power layer 104, a dielectric layer 105 and a signal connection layer 106 which are sequentially stacked from bottom to top, wherein a plurality of transistors 21 electrically connected with the buried power layer are formed in the dielectric layer 105, and metal wires are formed in the signal connection layer 106 so as to realize signal connection with the transistors 21; a plurality of through metal pillars 31 are formed in the silicon deposition layer 103, and the metal pillars 31 are electrically connected to metal lines of the power connection layer 102.
Specifically, the step S1 specifically includes:
s1-1: providing a first substrate, as shown in fig. 3-4, forming a power connection layer 102 and a silicon deposition layer 103 on the first substrate 101 in sequence, forming a plurality of through metal pillars 31 in the silicon deposition layer 103, wherein the metal pillars 31 are electrically connected with metal wires of the power connection layer 102;
s1-2: a buried power layer 104 and a dielectric layer 105 are sequentially formed on the surface of the silicon deposition layer 103, as shown in fig. 5, a plurality of transistors 21 electrically connected to the buried power layer 104 are formed in the dielectric layer 105, and the buried power layer 104 is used as a power supply channel for the transistors 21.
Specifically, the first substrate 101 may be a semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon germanium substrate, and the like, and is preferably a silicon substrate. The power connection layer 102 may be prepared by a damascene process of copper, for example, an insulating layer such as silicon dioxide is deposited on the surface of the first substrate, then etching is performed to form a trench, then metal copper is deposited in the trench, and finally the power connection layer 102 is formed, where the metal wire in the power connection layer 102 is copper. The process for preparing the metal column 31 is as follows: a plurality of Through Silicon Vias (TSVs), more specifically, nano through silicon vias (n-TSVs), are formed in the silicon deposition layer 103, then an oxide layer is covered on the inner wall of the through silicon vias, and finally metal pillars 31 are formed by metal filling.
The buried power layer 104 and the dielectric layer 105 are sequentially formed on the silicon deposition layer 103. As an example, the transistor 21 may be a Fin FET, the transistor 21 may be formed after the buried power layer 104 is formed, and the transistor 21 is formed by covering a silicon material and then further performing etching, doping, etc., and a specific manufacturing process of the transistor 21 (Fin FET) may be referred to in the prior art, which is not specifically described herein. The dielectric layer 105 is used to electrically insulate the transistors 21 from each other and from the upper and lower layers.
S1-3: as shown in fig. 6, a signal connection layer 106 is formed on a surface of the dielectric layer 105 of the chip unit, which is far from the substrate, and the first substrate 101 is removed; metal lines are formed in the signal connection layer 106 to realize signal connection with the transistors 21. The signal connection layer 106 is prepared by a damascene process of copper.
Next, step S2 is performed: as shown in fig. 7, a power transmission layer 108 and a signal transmission layer 107 are formed on the surfaces of the power connection layer 102 and the signal connection layer 106 of the chip unit, respectively, and bumps 17 are formed in the power transmission layer 108 and the signal transmission layer 107 as power supply channels.
Specifically, bump 17 is fabricated based on bump technology (Bumping), and is widely used in advanced packages such as FC, WLP, CSP and 3D, etc., by fabricating metal bumps on the surface of the chip to provide a "point" interface for electrical interconnection of the chip. The technology is formed by links such as vacuum sputtering, yellow light, electroplating, etching and the like, is an extension of the links of wafer manufacturing, and is also a basis and a premise for implementing a Flip Chip (FC) packaging process. Compared with the traditional package adopting the lead wire as the bonding mode, the bump replaces the original lead wire, and the breakthrough of 'replacing the wire with the point' is realized. The technology can allow the chip to have higher port density, shortens the signal transmission path, reduces the signal delay, and has better heat conductivity and reliability.
Next, step S3 is performed: the plurality of chip units are arranged in the plane direction, the signal transmission layers 107 of the plurality of chip units are interconnected by the first wiring layer 203 located thereabove, and the power transmission layers 108 of the plurality of chip units are interconnected by the second wiring layer 204 or the interconnection substrate 402 located therebelow.
Alternatively, when the power transmission layers 108 of the plurality of chip units are interconnected by the second wiring layer 204 located therebelow, S3 specifically includes:
s31: as shown in fig. 8, a supporting substrate 201 is provided, a peeling layer 202 and a first wiring layer 203 are sequentially formed on the supporting substrate 201, a plurality of chip units are placed on the first wiring layer 203 in the planar direction, and a signal transmission layer 107 is in electrical contact with the first wiring layer 203;
s32: as shown in fig. 9, a plastic layer 300 is formed by an injection molding process, and the plastic layer 300 is located on the first wiring layer 203 and covers the side wall of the chip unit;
s33: as shown in fig. 10, a second wiring layer 204 is formed on the plastic sealing layer 300, and the second wiring layer 204 is in electrical contact with the power transmission layer 108;
s34: forming solder balls 23 on the second wiring layer 204, and then separating the support substrate 201 based on the peeling layer 202;
s35: as shown in fig. 11, the entire structure is flipped so that the second wiring layer 204 is located below, and is soldered to the conductive substrate 401 by solder balls for electrical extraction.
Specifically, the support substrate 201 may be any one of a glass substrate, a silicon substrate, and a metal substrate, and is preferably a glass substrate. The stripping layer can be denatured by heat or laser so as to lose viscosity and separate from the surface of the supporting substrate, so that the purpose of de-bonding is achieved, and when the stripping layer needs to be separated, the stripping layer can be heated based on laser so as to separate the supporting substrate. The stripping layer 202 is commonly used in semiconductor processing, and has the characteristics of good compatibility with semiconductor reagents, no residual stripping, and the like. The molding layer 300 is typically an epoxy resin cured material. The solder ball can be one metal material or more than two alloy materials of copper, aluminum, nickel, gold, silver, tin and titanium, preferably silver-tin alloy.
Alternatively, when the power transmission layers 108 of the plurality of chip units are interconnected through the interconnection substrate 402 located thereunder, S3 specifically includes:
s3a: as shown in fig. 12, the power transmission layer 108 of the chip unit is fixed to the interconnect substrate 402 by solder balls;
s3b: as shown in fig. 13, a first injection molding layer 301 is formed on an interconnection substrate 402 by an injection molding process, the first injection molding layer 301 covering the side walls of the solder balls 23 and the side walls of the lower portion of the chip unit;
s3c: as shown in fig. 14, a first wiring layer 203 is disposed above the chip unit signal transmission layer 107, and solder balls 23 are soldered below the interconnection substrate 402;
s3d: as shown in fig. 15, a second injection molding layer 302 is formed on an interconnection substrate 402 by an injection molding process, the second injection molding layer 302 covering the side wall of the first wiring layer 203, the side wall of the first injection molding layer 301, and the side wall of the upper portion of the chip unit;
specifically, for the interconnection substrate, the line width of the metal wire inside the interconnection substrate is thicker, and the metal wire inside the wiring layer is thinner, so that when the interconnection substrate is adopted to realize interconnection of the power transmission layers of the plurality of chip units, the wiring layer is not required to be additionally arranged on the surface of the power transmission layer for interconnection, namely, the manufacture of the second wiring layer is omitted. The interconnection substrate plays a role of interconnection and downward transmission, and high-density fine wiring is not needed for power supply, so that the interconnection substrate with a thicker line width can be used. The material of the injection molding layer is the same as the plastic sealing layer and is an epoxy resin curing material. The solder ball can be one metal material or more than two alloy materials of copper, aluminum, nickel, gold, silver, tin and titanium, preferably silver-tin alloy.
Through the preparation method, a plurality of chip units can be interconnected, the device performance of the whole packaging structure is improved, meanwhile, the power transmission layer and the signal transmission layer are respectively arranged on two sides of the chip based on the back power supply technology, the electric conduction path is shortened, and the voltage drop is avoided. Meanwhile, the design of the two sides can release the design space of the front circuit, the size of the whole packaging structure is reduced, the power line and the signal line are arranged on the two sides, the stress balance effect can be achieved structurally, and the warping risk is reduced effectively.
The present application also provides a back-side power supply chip package structure, as shown in fig. 11 and 15, which may be based on the above preparation method, but is not limited to the above preparation method, and the chip package structure includes:
the chip unit comprises a power connection layer 102, a silicon deposition layer 103, a buried power layer 104, a dielectric layer 105 and a signal connection layer 106 which are sequentially stacked from bottom to top; a plurality of transistors 21 electrically connected to the buried power layer 104 are formed in the dielectric layer 105, and metal lines are formed in the signal connection layer 106 to realize signal connection with the transistors 21; a plurality of through metal pillars 31 are formed in the silicon deposition layer 103, and the metal pillars 31 are electrically connected to metal lines of the power connection layer 102. The surfaces of the power supply connection layer 102 and the signal connection layer 106 are respectively provided with a power supply transmission layer 108 and a signal transmission layer 107, and the power supply transmission layer 108 and the signal transmission layer 107 are internally provided with a bump 17 serving as a power supply channel;
the plurality of chip units are arranged in the planar direction, the signal transmission layers 107 of the plurality of chip units are interconnected by the first wiring layer 203 located thereabove, and the power transmission layers 108 of the plurality of chip units are interconnected by the second wiring layer 204 or the interconnection substrate 402 located therebelow.
Alternatively, as shown in fig. 11, when the power transmission layers of the plurality of chip units are interconnected by the second wiring layer located therebelow, the chip package structure further includes:
a plastic layer 300, wherein the plastic layer 300 is located on the second wiring layer 204 and covers the side wall of the chip unit, and the first wiring layer 203 is located on the upper surface of the plastic layer 300;
a conductive substrate 401, the conductive substrate 401 being soldered to the lower surface of the second wiring layer 204 by means of solder balls.
Alternatively, as shown in fig. 15, when the power transmission layers 108 of the plurality of chip units are interconnected by the interconnect substrate 402 located thereunder, the chip package structure further includes:
the first injection molding layer 301 is located on the interconnection substrate 402, and coats the side wall of the solder ball and the side wall of the lower part of the chip unit;
a second injection molding layer 302, wherein the second injection molding layer 302 is located on the interconnection substrate 402 and coats the side wall of the first wiring layer 203, the side wall of the first injection molding layer 301, and the side wall of the upper part of the chip unit;
in contrast, as shown in fig. 16, which is a schematic diagram of the chip packaging structure, compared with the packaging structure in fig. 2 in the prior art, the chip packaging structure provided by the application has the advantages that the power supply network layer 12 (corresponding to the power supply transmission layer and the power supply connection layer) and the signal network layer 11 (corresponding to the signal transmission layer and the signal connection layer) are respectively arranged at two sides of the chip, so that the conduction path of electric power is shortened, the circuit density is reduced, the space is saved, and the 2.5D adapter plate is not required to be arranged for circuit switching, so that the packaging cost is saved.
For specific details of the chip package structure, reference may be made to the related descriptions in the above preparation method, which are not repeated here.
In summary, the present application provides a back-side power chip package structure and a method for manufacturing the same, the back-side power chip package structure includes a chip unit, the chip unit includes a power connection layer, a silicon deposition layer, a buried power layer, a dielectric layer and a signal connection layer stacked in sequence from bottom to top; a plurality of transistors electrically connected with the embedded power layer are formed in the dielectric layer, metal wires are formed in the signal connection layer so as to realize signal connection with the transistors, and a power transmission layer and a signal transmission layer are respectively formed on the surfaces of the power connection layer and the signal connection layer. The plurality of chip units are arranged along the plane direction, the signal transmission layers of the plurality of chip units are interconnected through the first wiring layer positioned above the signal transmission layers, and the power transmission layers of the plurality of chip units are interconnected through the second wiring layer or the interconnection substrate positioned below the power transmission layers.
The chip packaging structure interconnects the plurality of chip units, improves the device performance of the whole packaging structure, and simultaneously, based on the back power supply technology, the power transmission layer and the signal transmission layer are respectively arranged on two sides of the chip, so that the conduction path of electric power is shortened, and the generation of voltage drop is avoided. Meanwhile, the design of the two sides can release the design space of the front circuit, the size of the whole packaging structure is reduced, the power line and the signal line are arranged on the two sides, the stress balance effect can be achieved structurally, and the warping risk is reduced effectively.
The above embodiments are merely illustrative of the principles of the present application and its effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the application. Accordingly, it is intended that all equivalent modifications and variations of the application be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. A back side powered chip package structure, the chip package structure comprising:
the chip unit comprises a power supply connecting layer, a silicon deposition layer, a buried power layer, a dielectric layer and a signal connecting layer which are sequentially stacked from bottom to top; a plurality of transistors electrically connected with the embedded power layer are formed in the dielectric layer, and metal wires are formed in the signal connection layer so as to realize signal connection with the transistors; forming a plurality of penetrating metal columns in the silicon deposition layer, wherein the metal columns are electrically connected with metal wires of the power supply connecting layer; the power supply connection layer and the signal connection layer are respectively formed on the surfaces of the power supply connection layer and the signal connection layer, and a bump serving as a power supply channel is formed in the power supply transmission layer and the signal transmission layer;
the plurality of chip units are arranged along the plane direction, the signal transmission layers of the plurality of chip units are interconnected through the first wiring layer positioned above the signal transmission layers, and the power transmission layers of the plurality of chip units are interconnected through the second wiring layer or the interconnection substrate positioned below the power transmission layers.
2. The chip package structure according to claim 1, wherein when the power transmission layers of the plurality of chip units are interconnected by the second wiring layer located therebelow, the chip package structure further comprises:
the plastic layer is positioned on the second wiring layer and coats the side wall of the chip unit, and the first wiring layer is positioned on the upper surface of the plastic layer;
and a conductive substrate soldered to a lower surface of the second wiring layer by means of solder balls.
3. The chip package structure according to claim 2, wherein when the power transmission layers of the plurality of chip units are interconnected by the interconnect substrate located thereunder, the chip package structure further comprises:
the first injection molding layer is positioned on the interconnection substrate and coats the side wall of the solder ball and the side wall of the lower part of the chip unit;
the second injection molding layer is positioned on the interconnection substrate and coats the side wall of the first wiring layer, the side wall of the first injection molding layer and the side wall of the upper part of the chip unit.
4. A chip package structure according to claim 3, wherein: solder balls are also respectively fixed on the lower surfaces of the conductive substrate and the interconnection substrate.
5. The chip package structure according to claim 1, wherein: the power connection layer and the signal connection layer are formed based on a copper Damascus process.
6. The preparation method of the back-side power supply chip packaging structure is characterized by comprising the following steps of:
s1: providing a chip unit, wherein the chip unit comprises a power supply connection layer, a silicon deposition layer, a buried power layer, a dielectric layer and a signal connection layer which are sequentially stacked from bottom to top, a plurality of transistors electrically connected with the buried power layer are formed in the dielectric layer, and metal wires are formed in the signal connection layer so as to realize signal connection with the transistors; forming a plurality of penetrating metal columns in the silicon deposition layer, wherein the metal columns are electrically connected with metal wires of the power supply connecting layer;
s2: forming a power transmission layer and a signal transmission layer on the surfaces of the power connection layer and the signal connection layer of the chip unit respectively, wherein a bump is formed in the power transmission layer and the signal transmission layer to serve as a power supply channel;
s3: the plurality of chip units are arranged along the plane direction, the signal transmission layers of the plurality of chip units are interconnected through the first wiring layer positioned above the signal transmission layers, and the power transmission layers of the plurality of chip units are interconnected through the second wiring layer or the interconnection substrate positioned below the power transmission layers.
7. The method according to claim 6, wherein the step S1 of preparing the chip unit specifically comprises:
s1-1: providing a first substrate, sequentially forming a power supply connecting layer and a silicon deposition layer on the first substrate, and forming a plurality of penetrating metal columns in the silicon deposition layer, wherein the metal columns are electrically connected with metal wires of the power supply connecting layer;
s1-2: forming a buried power layer and a dielectric layer on the surface of the silicon deposition layer in sequence, wherein a plurality of transistors electrically connected with the buried power layer are formed in the dielectric layer, and the buried power layer is used as a power supply channel of the transistors;
s1-3: forming a signal connection layer on the surface of the dielectric layer, which is far away from the substrate, and removing the first substrate; and metal wires are formed in the signal connection layer so as to realize signal connection with the transistors.
8. The method of manufacturing according to claim 6, wherein when the power transmission layers of the plurality of chip units are interconnected by the second wiring layer located therebelow, S3 specifically comprises:
s31: providing a supporting substrate, wherein a stripping layer and a first wiring layer are sequentially formed on the supporting substrate, a plurality of chip units are placed on the first wiring layer along the plane direction, and a signal transmission layer is electrically contacted with the first wiring layer;
s32: forming a plastic layer through an injection molding process, wherein the plastic layer is positioned on the first wiring layer and coats the side wall of the chip unit;
s33: forming a second wiring layer on the plastic sealing layer, wherein the second wiring layer is in electrical contact with the power transmission layer;
s34: forming solder balls on the second wiring layer, and then separating the support substrate based on the peeling layer;
s35: the whole structure is turned over so that the second wiring layer is located below and soldered to the conductive substrate by solder balls for electrical extraction.
9. The method of manufacturing according to claim 6, wherein when the power transmission layers of the plurality of chip units are interconnected by the interconnect substrate located therebelow, S3 specifically comprises:
s3a: fixing a power transmission layer of the chip unit to the interconnection substrate through solder balls;
s3b: forming a first injection molding layer on the interconnection substrate through an injection molding process, wherein the first injection molding layer coats the side wall of the solder ball and the side wall of the lower part of the chip unit;
s3c: arranging a first wiring layer above the chip unit signal transmission layer, and welding solder balls below the interconnection substrate;
s3d: and forming a second injection molding layer on the interconnection substrate through an injection molding process, wherein the second injection molding layer covers the side wall of the first wiring layer, the side wall of the first injection molding layer and the side wall of the upper part of the chip unit.
10. The method of manufacturing according to claim 6, wherein: the power connection layer and the signal connection layer are formed based on a copper Damascus process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310943260.1A CN116666352B (en) | 2023-07-31 | 2023-07-31 | Back-side power supply chip packaging structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310943260.1A CN116666352B (en) | 2023-07-31 | 2023-07-31 | Back-side power supply chip packaging structure and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116666352A CN116666352A (en) | 2023-08-29 |
| CN116666352B true CN116666352B (en) | 2023-09-22 |
Family
ID=87710059
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310943260.1A Active CN116666352B (en) | 2023-07-31 | 2023-07-31 | Back-side power supply chip packaging structure and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116666352B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005223166A (en) * | 2004-02-06 | 2005-08-18 | Hitachi Ltd | Semiconductor package |
| CN112117262A (en) * | 2019-06-21 | 2020-12-22 | 三星电子株式会社 | Semiconductor package |
| CN113824456A (en) * | 2021-09-14 | 2021-12-21 | 重庆两江卫星移动通信有限公司 | Active multi-beam tile-type phased array receiving assembly |
| CN115440702A (en) * | 2021-06-01 | 2022-12-06 | 三星电子株式会社 | Semiconductor device and method for manufacturing the same |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI443789B (en) * | 2008-07-04 | 2014-07-01 | Unimicron Technology Corp | Substrate having semiconductor chip embedded therein and fabrication method thereof |
| US10594019B2 (en) * | 2016-12-03 | 2020-03-17 | International Business Machines Corporation | Wireless communications package with integrated antenna array |
-
2023
- 2023-07-31 CN CN202310943260.1A patent/CN116666352B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005223166A (en) * | 2004-02-06 | 2005-08-18 | Hitachi Ltd | Semiconductor package |
| CN112117262A (en) * | 2019-06-21 | 2020-12-22 | 三星电子株式会社 | Semiconductor package |
| CN115440702A (en) * | 2021-06-01 | 2022-12-06 | 三星电子株式会社 | Semiconductor device and method for manufacturing the same |
| CN113824456A (en) * | 2021-09-14 | 2021-12-21 | 重庆两江卫星移动通信有限公司 | Active multi-beam tile-type phased array receiving assembly |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116666352A (en) | 2023-08-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107452725B (en) | Method of manufacturing semiconductor package | |
| TWI613740B (en) | Structure and method for integrated circuits packaging with increased density | |
| US9698080B2 (en) | Conductor structure for three-dimensional semiconductor device | |
| KR101201087B1 (en) | 3d integration structure and method using bonded metal planes | |
| KR100772604B1 (en) | Integrated Electronic Chip and Interconnect Device and Process for Making the Same | |
| US7807512B2 (en) | Semiconductor packages and methods of fabricating the same | |
| US9735101B2 (en) | Semiconductor device with through-substrate via covered by a solder ball | |
| US20240088123A1 (en) | Integrated Circuit Package and Method | |
| CN110335859B (en) | Multi-chip packaging structure based on TSV and preparation method thereof | |
| CN106684006B (en) | Double-sided fan-out type wafer level packaging method and packaging structure | |
| KR102469446B1 (en) | Semiconductor structure and method forming same | |
| WO2009146588A1 (en) | Bonding method for through-silicon-via based 3d wafer stacking | |
| CN111128914A (en) | Low-warpage multi-chip packaging structure and manufacturing method thereof | |
| US9818724B2 (en) | Interposer-chip-arrangement for dense packaging of chips | |
| US10373929B2 (en) | Method of manufacturing a semiconductor device | |
| US20090321958A1 (en) | Semiconductor device having a simplified stack and method for manufacturing thereof | |
| CN112509991A (en) | Integrated circuit package structure, integrated circuit package unit and related manufacturing method | |
| US10529693B2 (en) | 3D stacked dies with disparate interconnect footprints | |
| KR20100065785A (en) | A method of chip interconnection using a capillary motion | |
| CN116666352B (en) | Back-side power supply chip packaging structure and preparation method thereof | |
| CN117038588A (en) | Packaging structure and packaging method | |
| CN116114396A (en) | Previous process interconnect structures and associated systems and methods | |
| CN113496901A (en) | Chip embedded substrate structure, chip packaging structure and manufacturing method thereof | |
| CN116759406A (en) | Back-side power supply chip packaging structure and preparation method thereof | |
| CN218827086U (en) | Semiconductor packaging structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |