CN116665595A

CN116665595A - Array substrate, display panel and display device

Info

Publication number: CN116665595A
Application number: CN202310664671.7A
Authority: CN
Inventors: 张蒙蒙
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2023-06-05
Filing date: 2023-06-05
Publication date: 2023-08-29

Abstract

The application discloses an array substrate, a display panel and a display device. The array substrate has a display area and a non-display area at least partially surrounding the display area, and the array substrate includes: the grid driving circuit is positioned in the non-display area and comprises a plurality of cascaded shift register units; a clock signal line electrically connected to the plurality of shift register units; a trigger signal line electrically connected with at least one shift register unit; at least one of the clock signal line and the trigger signal line is located in the display area. According to the embodiment of the application, the narrow frame is beneficial to realizing.

Description

Array substrate, display panel and display device

Technical Field

The application relates to the technical field of display, in particular to an array substrate, a display panel and a display device.

Background

With the continuous update of display panel technology, display panels are gradually developing towards light and thin, high screen occupation ratio and ultra-narrow frame.

The display panel generally includes a driving circuit and a signal line supplying a signal to the driving circuit. How to arrange the signal lines to realize a narrow frame is a technical problem facing the person skilled in the art.

Disclosure of Invention

The embodiment of the application provides an array substrate, a display panel and a display device, which are beneficial to realizing a narrow frame.

In a first aspect, an embodiment of the present application provides an array substrate having a display area and a non-display area at least partially surrounding the display area, the array substrate including: the grid driving circuit is positioned in the non-display area and comprises a plurality of cascaded shift register units; a clock signal line electrically connected to the plurality of shift register units; a trigger signal line electrically connected with at least one shift register unit; at least one of the clock signal line and the trigger signal line is located in the display area.

Based on the same inventive concept, in a second aspect, an embodiment of the present application provides a display panel, including an array substrate as described in the embodiment of the first aspect.

Based on the same inventive concept, in a third aspect, an embodiment of the present application provides a display device including the display panel according to the embodiment of the second aspect.

According to the display panel and the display device provided by the embodiment of the application, the clock signal line and/or the trigger signal line are/is positioned in the display area, so that the left and right frames can be reduced, and the lower frame can be reduced.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar features, and in which the figures are not to scale.

Fig. 1 shows a schematic top view of an array substrate according to an embodiment of the present application;

fig. 2 is a schematic top view of another embodiment of an array substrate according to the present disclosure;

fig. 3 is a schematic structural diagram of a winding in an array substrate according to an embodiment of the present application;

fig. 4 is a schematic top view of another embodiment of an array substrate according to the present disclosure;

fig. 5 is a schematic top view of a partial area of an array substrate according to an embodiment of the present application;

fig. 6 shows a timing diagram of an array substrate according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of a shift register unit in an array substrate according to an embodiment of the present application;

fig. 8 is a schematic top view of another partial area of an array substrate according to an embodiment of the present disclosure;

fig. 9 is a schematic diagram of a film structure of an array substrate according to an embodiment of the present application;

fig. 10 is a schematic top view of another embodiment of an array substrate according to the present disclosure;

FIG. 11 is a schematic top view of an array substrate according to an embodiment of the present disclosure;

fig. 12 is a schematic top view of a partial area of an array substrate according to an embodiment of the present disclosure;

fig. 13 is a schematic top view of a partial area of an array substrate according to an embodiment of the present disclosure;

fig. 14 is a schematic structural diagram of a pixel circuit in an array substrate according to an embodiment of the present application;

fig. 15 is a schematic top view of a display device according to an embodiment of the application.

Reference numerals illustrate:

100. an array substrate;

AA. A display area; NA, non-display area; BA. A step region;

10. a gate driving circuit; 11. a first gate driving circuit; 12. a second gate driving circuit;

VSR, shift register unit; VSR1, a first shift register unit; VSR2, second shift register unit

21. A clock signal line; 21a, a first type clock signal line; 21b, a second type clock signal line;

211. a first clock signal line; 212. a second clock signal line;

22. a trigger signal line; 221. a first trigger signal line; 222. a second trigger signal line;

31. a lead wire; 32. an electrostatic protection line;

41. a first winding; 42. a second winding; 43. a third winding; 44. connecting winding wires;

50. a connecting wire; 51. a first connecting line; 52. a second connecting line; 53. a third connecting line; 54. a fourth connecting line;

60. a gate trace;

71. a pixel circuit; 72. a dummy pixel circuit; 711. a connection part;

80. a data line;

90. a shielding structure; 91. a first shielding structure; 92. a second shielding structure;

1000. a display device.

Detailed Description

Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail below with reference to the accompanying drawings and the detailed embodiments. It should be understood that the specific embodiments described herein are merely configured to illustrate the application and are not configured to limit the application. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the application by showing examples of the application.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.

It will be understood that when a layer, an area, or a structure is described as being "on" or "over" another layer, another area, it can be referred to as being directly on the other layer, another area, or another layer or area can be included between the layer and the other layer, another area. And if the component is turned over, that layer, one region, will be "under" or "beneath" the other layer, another region.

It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

In embodiments of the present application, the term "electrically connected" may refer to two components being directly electrically connected, or may refer to two components being electrically connected via one or more other components.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Accordingly, it is intended that the present application covers the modifications and variations of this application provided they come within the scope of the appended claims (the claims) and their equivalents. The embodiments provided by the embodiments of the present application may be combined with each other without contradiction.

The embodiment of the application provides an array substrate, a display panel and a display device, and various embodiments of the array substrate, the display panel and the display device are described below with reference to the accompanying drawings.

As shown in fig. 1, the array substrate 100 has a display area AA and a non-display area NA at least partially surrounding the display area AA. The array substrate 100 may include a gate driving circuit 10, a clock signal line 21, and a trigger signal line 22.

The gate driving circuit 10 is located in the non-display area NA, and the gate driving circuit 10 may include a plurality of shift register units VSR cascaded. For example, the display area AA of the array substrate 100 may include a plurality of rows of pixel circuits (not shown in fig. 1), and the scan signal output from the shift register unit VSR may be used to control on or off of at least some of the transistors in the pixel circuits. The plurality of cascaded shift register units VSR can output the scan signals step by step to scan the pixel circuits line by line.

The clock signal line 21 is electrically connected to each shift register cell VSR, and the clock signal line 21 may be used to transmit a clock signal to each shift register cell VSR.

The trigger signal line 22 is electrically connected to at least one shift register cell VSR, and the trigger signal line 22 is used to transmit a trigger signal to the shift register cell VSR to which it is electrically connected. For example, the trigger signal line 22 is electrically connected to the first stage shift register unit VSR. The signal output by the i-th shift register unit VSR may be used as a trigger signal of the i+1th shift register unit VSR, i is greater than or equal to 1, and i is an integer, for example, i=1.

At least one of the clock signal line 21 and the trigger signal line 22 may be located in the display area AA. Fig. 1 illustrates that both are located in the display area AA, which is not intended to limit the present application.

For example, the clock signal line 21 and the trigger signal line 22 may each extend in the first direction X, and the clock signal line 21 and the trigger signal line 22 may be arranged in the second direction Y, which intersects. For example, the first direction X may be a column direction and the second direction Y may be a row direction.

For example, the non-display area NA may include a stepped area BA, the stepped area BA may include a plurality of signal terminals pad, the clock signal line 21 and the trigger signal line 22 may be connected to different signal terminals pad through different leads 31, and the signal terminals pad may be electrically connected to a driving chip (not shown in fig. 1). It is understood that in the case where the clock signal line 21 and/or the trigger signal line 22 are located in the display area AA, the lead 31 to which they are connected may directly extend in the first direction X. If the clock signal line 21 and the trigger signal line 22 are both located in the non-display area NA, the lead line 31 needs to detour to the edge area to be connectable to the clock signal line 21 and the trigger signal line 22, which requires an increase in the width of the lower frame in the first direction X. Accordingly, the clock signal line 21 and/or the trigger signal line 22 are located in the display area AA, which is advantageous for reducing not only the left and right frames but also the lower frame.

In the preparation process of the array substrate or when the array substrate is used for a display panel, static electricity may be generated during the display process, and in order to release or evacuate static electricity, as shown in fig. 1, a static electricity protection line 32 may be disposed, where the static electricity protection line 32 is located in the non-display area NA and is located at a side of the gate driving circuit 10 away from the display area AA. The electrostatic protection line 32 may be grounded GND. The electrostatic discharge protection wire 32 may be used for electrostatic discharge (ESD).

To avoid electrostatic breakdown of the electrostatic protection line 32, the trace width of the electrostatic protection line 32 may be relatively thick.

It is understood that the clock signal line 21 and the trigger signal line 22 are traces having relatively long trace lengths, and that the clock signal line 21 and the trigger signal line 22 are liable to accumulate static electricity, and that in the case where the static electricity polarity on the clock signal line 21 and the trigger signal line 22 is different from the static electricity polarity on the static electricity protection line 32, the thinner clock signal line 21 and the trigger signal line 22 are liable to break down.

In the embodiment of the present application, the clock signal line 21 and/or the trigger signal line 22 are located in the display area AA, so that the gate driving circuit 10 is spaced between the clock signal line 21 and/or the trigger signal line 22 and the electrostatic protection line 32, which is beneficial to avoiding the clock signal line 21 and/or the trigger signal line 22 from being broken down by static electricity.

In some embodiments, as shown in fig. 2, at least the clock signal line 21 is located in the display area AA, and the non-display area NA includes the step area BA, for example, the array substrate 100 may further include a first winding 41 and a second winding 42, and the clock signal line 21 is electrically connected to the plurality of shift register units VSR through the first winding 41 and the second winding 42. The first wire 41 is connected between the clock signal line 21 and the second wire 42, and the second wire 42 is connected to the shift register unit VSR. The first wire 41 and the second wire 42 are both located in the non-display area NA, and the display area AA is spaced between the first wire 41 and the step area BA.

Taking the case that the step area BA is located in the lower frame, more fan-out lines need to be set in the lower frame, in the embodiment of the present application, the number of wires that need to be set in the upper frame is relatively smaller than that of the lower frame, and the space of the lower frame can be saved by setting the first wires 41 in the upper frame, so that the lower frame is more beneficial to being reduced.

For example, as shown in fig. 2, the trigger signal line 22 may be connected to the first stage shift register unit VSR through the third wire 43. The third wire 43 is located in the non-display area NA, and the display area AA is spaced between the third wire 43 and the step area BA. In this way, the third wire 43 is also disposed on the upper frame, so as to save space of the lower frame.

For example, as shown in fig. 2, the second wire 42 may be connected to the shift register unit VSR through the connection wire 44, and the connection wire 44 may be located in the non-display area NA.

In some embodiments, as described above, the extending direction of the clock signal line 21 is the first direction X. Referring to fig. 2, in the second direction Y, the second wire 42 extends along the first direction X, and the gate driving circuit 10 may be located between the second wire 42 and the display area AA.

As shown in fig. 3, the second wire 42 may include a plurality of wire segments connected to one another, with at least two wire segments being located in different film layers.

For example, the second winding 42 may include a first winding segment 421 and a second winding segment 422 connected to each other, where the first winding segment 421 and the second winding segment 422 are located in different metal layers, and the first winding segment 421 and the second winding segment 422 may be connected through a first via h 1. The first wire segments 421 and the second wire segments 422 may be alternately distributed in the first direction X.

The second wire 42 needs to be connected to each shift register cell VSR, so that the overall trace length of the second wire 42 is also relatively long. In the embodiment of the present application, dividing the second winding 42 into a plurality of winding segments is equivalent to dividing the longer second winding 42 into a plurality of shorter winding segments, so that the possibility of accumulating static charges on the second winding 42 can be reduced, and the reliability of the second winding 42 can be improved.

In some embodiments, as shown in fig. 1, the gate driving circuit 10 may include a first gate driving circuit 11 and a second gate driving circuit 12, where the first gate driving circuit 11 includes a plurality of first shift register units VSR1 in cascade, and the second gate driving circuit 12 includes a plurality of second shift register units VSR2 in cascade.

The first shift register unit VSR1 and the second shift register unit VSR2 are located at both sides of the display area AA in the second direction Y, that is, the first shift register unit VSR1 and the second shift register unit VSR2 are spaced apart from the display area AA in the second direction Y.

The clock signal lines 21 may include a first type clock signal line 21a and a second type clock signal line 21b, the first type clock signal line 21a being adjacent to and electrically connected to the first shift register unit VSR1, and the second type clock signal line 21b being adjacent to and electrically connected to the second shift register unit VSR2.

In the embodiment of the application, various clock signal lines are arranged close to the shift register units electrically connected with the clock signal lines, so that the length of connecting lines between the clock signal lines and the shift register units electrically connected with the clock signal lines can be shortened.

As one example, the first shift register unit VSR1 and the second shift register unit VSR2 may be used to output different gate control signals. For example, the first shift register unit VSR1 may output a scan signal, which may be used to control whether the data signal is written into the pixel circuit. The second shift register unit VSR2 may be used to output a light emission control signal, which may be used to control whether the pixel circuit enters a light emission stage.

As another example, the first shift register unit VSR1 and the second shift register unit VSR2 may also be used to output the same gate control signal, and the first shift register unit VSR1 and the second shift register unit VSR2 may be connected to both ends of the same gate wiring, thereby implementing double-ended driving to reduce the influence of signal delay.

In other embodiments, as shown in fig. 4, taking the clock signal line 21 located in the display area AA and extending along the first direction X as an example, the array substrate 100 may further include a connection line 50, and the clock signal line 21 may be electrically connected to the plurality of shift register units VSR through the connection line 50. In the second direction Y, the connection line 50 is located between the clock signal line 21 and the shift register unit VSR.

In the embodiment of the application, the windings for connecting the clock signal line 21 and the shift register unit VSR are not arranged on the left and right frames, but the connection line is directly arranged between the clock signal line 21 and the shift register unit VSR, so that the left and right frames can be further saved.

In some embodiments, as shown in fig. 5, the clock signal line 21 may include a first clock signal line 211 and a second clock signal line 212. The clock signals provided on the first clock signal line 211 and the second clock signal line 212 may be different. Illustratively, as shown in fig. 6, taking a low level as an example of the on level, the on levels of the clock signals provided on the first clock signal line 211 and the second clock signal line 212 may be staggered in time.

As shown in fig. 5, the connection line 50 may include a first connection line 51, a second connection line 52, a third connection line 53, and a fourth connection line 54. Wherein, the first connection line 51 may be connected between the first clock signal line 211 and the i-th stage shift register unit VSR (i), the second connection line 52 is connected between the second clock signal line 212 and the i+1th stage shift register unit VSR (i+1), and the third connection line 53 is connected between the second connection line 52 and the i-th stage shift register unit VSR (i), and the fourth connection line 54 is connected between the first connection line 51 and the i+1th stage shift register unit VSR (i+1), wherein i is an odd number. For example, i=1.

It is understood that the i-th stage shift register unit VSR (i) is directly connected to the first clock signal line 211 through the first connection line 51, and the i-th stage shift register unit VSR (i) is connected to the second clock signal line 212 through the third connection line 53 and the second connection line 52 in sequence. The third connection line 53 corresponds to a transfer connection line between the i-th shift register unit VSR (i) and the second clock signal line 212.

The i+1th stage shift register unit VSR (i+1) is directly connected to the second clock signal line 212 through the second connection line 52, and the i+1th stage shift register unit VSR (i+1) is connected to the first clock signal line 211 through the fourth connection line 54, the first connection line 51 in this order. The fourth connection line 54 corresponds to a transfer connection line between the i+1th stage shift register unit VSR (i+1) and the first clock signal line 211.

In the embodiment of the present application, the shift register unit is connected to one of the first clock signal line 211 and the second clock signal line 212 through the third connection line 53 or the fourth connection line 54, so that the positions of the third connection line 53 and the fourth connection line 54 can be flexibly arranged.

As an example, as shown in fig. 5, the third connection line 53 and the fourth connection line 54 may be located in the non-display area NA. Since the signal on the clock signal line is frequently switched between high and low levels, in the case where the third connection line 53 and the fourth connection line 54 are located in the non-display area, the coupling between the third connection line 53 and the fourth connection line 54 and the pixel circuit 71 in the display area AA can be reduced, which can be advantageous for improving the display quality.

In addition, the first connecting line 51 and the second connecting line 52 may extend along the second direction Y, at least a portion of the first connecting line 51 is located in the display area AA, and at least a portion of the second connecting line 52 is located in the display area AA.

In some embodiments, as shown in fig. 5, the display area AA of the array substrate 100 may include a plurality of gate wires 60, and the gate wires 60 may be scan lines or light emitting control signal lines.

The output terminal out of the i-th stage shift register unit VSR (i) is electrically connected to the i-th gate trace 60 (i), and the output terminal of the i+1-th stage shift register unit VSR (i+1) is electrically connected to the i+1-th gate trace 60 (i+1).

As shown in fig. 6, the i-th stage shift register unit VSR (i) may generate a gate control signal based on a signal on the second clock signal line 212, and the i+1-th stage shift register unit VSR (i+1) may generate a gate control signal based on a signal on the first clock signal line 211.

For example, taking a low level as an on level, a low level output from the i-th stage shift register unit VSR (i) is generated based on a low level on the second clock signal line 212, and a low level output from the i+1-th stage shift register unit VSR (i+1) is generated based on a low level on the first clock signal line 211.

As shown in fig. 5, in the first direction X, the distance between the first connection line 51 connected to the i-th stage shift register unit VSR (i) and the i-th gate line 60 (i) is d1, and the distance between the second connection line 52 connected to the i+1-th stage shift register unit VSR (i+1) and the i-th gate line 60 (i) is d2, where d1 < d2.

The distance between the first connection line 51 connected to the i-th stage shift register unit VSR (i) and the i+1th gate trace 60 (i+1) is d3, and the distance between the second connection line 52 connected to the i+1th stage shift register unit VSR (i+1) and the i+1th gate trace 60 (i+1) is d4, where d3 > d4.

Since the i-th stage shift register unit VSR (i) generates the gate control signal based on the signal on the second clock signal line 212, in the case where d1 < d2, it is advantageous to avoid that the output signal of the i-th stage shift register unit VSR (i) is further coupled by the signal on the second clock signal line 212, for example, that the output signal of the i-th stage shift register unit VSR (i) is further coupled and pulled high by the signal on the second clock signal line 212. Similarly, the i+1 stage shift register unit VSR (i+1) generates the gate control signal based on the signal on the first clock signal line 211, and in the case where d3 > d4, it is advantageous to avoid that the output signal of the i+1 stage shift register unit VSR (i+1) is further coupled by the signal on the first clock signal line 211.

For example, the circuit structure of the shift register unit may be as shown IN fig. 7, where VGH represents a high level signal terminal, VGL represents a low level signal terminal, IN represents a trigger signal terminal, and ck and xck represent two clock signal terminals IN fig. 7. Fig. 7 is merely an example, and is not intended to limit the specific circuit configuration of the shift register unit.

In some embodiments, as shown in fig. 5, the display area AA of the array substrate further includes a plurality of rows of pixel circuits 71, and the ith gate wire 60 (i) is electrically connected to the ith row of pixel circuits 71. For example, the signal on the ith gate trace 60 (i) may be used to control whether the data signal is written to the ith row of pixel circuits 71.

The (i+1) th gate wire 60 (i+1) may be connected to the (i+1) th row of pixel circuits 71. For example, the signal on the i+1th gate trace 60 (i+1) may be used to control whether the data signal is written to the i+1th row pixel circuit 71.

The first connection line 51 connected to the i-th stage shift register unit VSR (i) may overlap with the orthographic projection of the i-th row pixel circuit 71 on the plane of the array substrate, and the first connection line 51 connected to the i-th stage shift register unit VSR (i) may not overlap with the orthographic projection of the i+1-th row pixel circuit 71 on the plane of the array substrate.

The second connection line 52 connected to the i+1-th stage shift register unit VSR (i+1) may not overlap with the orthographic projection of the i-th row pixel circuit 71 on the plane of the array substrate, and the second connection line 52 connected to the i+1-th stage shift register unit VSR (i+1) may overlap with the orthographic projection of the i+1-th row pixel circuit 71 on the plane of the array substrate.

In this way, the first connection line 51 and the second connection line 52 may overlap only one of the two adjacent rows of pixel circuits, and the coupling effect of the first connection line 51 and the second connection line 52 on the pixel circuits may be reduced.

In some embodiments, as shown in fig. 8, the display area AA of the array substrate further includes a data line 80, and the clock signal line 21 and/or the trigger signal line 22 and the data line 80 in the display area AA may be located in different layers. In this way, the coupling between the clock signal line 21 and/or the trigger signal line 22 and the data line 80 in the display area AA can be reduced.

As illustrated in fig. 9, the array substrate may include a stacked semiconductor layer b, a first metal layer M1, a second metal layer M2, a third metal layer M3, a fourth metal layer M4, and an anode layer RE. The clock signal line 21 and/or the trigger signal line 22 in the display area AA may be located at the fourth metal layer M4, and the data line 80 may be located at the third metal layer M3.

The array substrate may further include a substrate 01, a gate insulating layer GI, a capacitor insulating layer IMD, an interlayer dielectric layer ILD, a first planarization layer PLN1, a second planarization layer PLN2, a pixel defining layer PDL, and a support PS.

As illustrated in fig. 10, the array substrate 100 includes a pixel circuit 71 and a dummy pixel circuit 72. The pixel circuit 71 is located in the display area AA. The pixel circuit 71 may be used to drive a light emitting element of a display panel to emit light. The dummy pixel circuit 72 is not used to drive the light emitting element to emit light.

In the second direction Y, the dummy pixel circuit 72 may be located between the gate driving circuit 10 and the pixel circuit 71. Still taking the extending direction of the clock signal line 21 as the first direction X as an example, the second direction Y intersects with the first direction X.

The front projection of the clock signal line 21 and/or the trigger signal line 22 on the plane of the array substrate in the display area AA may at least partially overlap with the front projection of the dummy pixel circuit 72 on the plane of the array substrate.

Since the dummy pixel circuit 72 is not used to drive the light emitting element, in the case where the clock signal line 21 and/or the trigger signal line 22 overlap with the dummy pixel circuit 72, the coupling of the clock signal line 21 and/or the trigger signal line 22 to the pixel circuit 71 can be reduced, and thus the display effect can be advantageously improved.

In other embodiments, as shown in fig. 11, the front projection of the clock signal line 21 and/or the trigger signal line 22 on the plane of the array substrate in the display area AA may at least partially overlap with the front projection of the pixel circuit 71 on the plane of the array substrate.

Since the dummy pixel circuit 72 is disposed near the edge of the display area, in the case where the clock signal line 21 and/or the trigger signal line 22 overlap the pixel circuit 71, it is more advantageous for the clock signal line 21 and/or the trigger signal line 22 to be near the signal terminal pad to which it is connected, and thus it is more advantageous for the lead 31 to extend directly in the first direction X. Thereby being more beneficial to reducing the lower frame.

In some embodiments, as shown in fig. 12, the display area AA of the array substrate further includes a data line 80 and a shielding structure 90, and the shielding structure 90 includes a first shielding structure 91, the first shielding structure 91 being located between the data line 80 and the clock signal line 21 or the trigger signal line 22 in the display area AA. The first shielding structure 91 may be advantageous in avoiding coupling between the clock signal line 21 or the trigger signal line 22 of the display area AA and the data line 80.

For example, in the case where the front projection of the clock signal line 21 or the trigger signal line 22 on the plane of the array substrate in the display area does not overlap with the front projection of the data line 80 on the plane of the array substrate, the front projection of the first shielding structure 91 on the plane of the array substrate may be located between the front projection of the clock signal line 21 or the trigger signal line 22 on the plane of the array substrate in the display area and the front projection of the data line 80 on the plane of the array substrate.

For another example, in the case where the front projection of the clock signal line 21 or the trigger signal line 22 on the plane of the array substrate in the display area overlaps with the front projection of the data line 80 on the plane of the array substrate, the film layer where the first shielding structure 91 is located may be located between the film layer where the clock signal line 21 or the trigger signal line 22 and the film layer where the data line 80 is located, and the front projection of the first shielding structure 91 on the plane of the array substrate, the front projection of the clock signal line 21 or the trigger signal line 22 on the plane of the array substrate in the display area, and the front projection of the data line 80 on the plane of the array substrate may overlap.

The first shielding structure 91 may be in a floating (floating) state, or the first shielding structure 91 may be used to connect a fixed signal terminal.

In fig. 12, the data line 80 is shown by a thick solid line, the clock signal line 21 and the trigger signal line 22 are shown by a thin solid line, and the first shielding structure 91 is shown by a broken line for the sake of clarity in distinguishing different signal lines or structures, which are not intended to limit the thickness or continuity of the signal lines or structures.

In some embodiments, as shown in fig. 13, the pixel circuit 71 may include a driving transistor M13 and a connection part 711, the connection part 711 being connected to a gate g3 of the driving transistor M13. For example, the connection part 711 may be connected to the gate g3 of the driving transistor M13 through the via hole h 2.

The display area of the array substrate may further include a shielding structure 90, and the shielding structure 90 may include a second shielding structure 92, and the second shielding structure 92 may be located between the connection part 711 and the clock signal line 21 or the trigger signal line 22 in the display area. Similarly, the second shielding structure 92 can be beneficial to avoid coupling between the clock signal line 21 or the trigger signal line 22 of the display area AA and the connection portion 711, and thus can be beneficial to avoid the influence of the potential jump of the clock signal line 21 or the trigger signal line 22 on the gate potential of the driving transistor M13.

For example, in the case where the front projection of the clock signal line 21 or the trigger signal line 22 on the plane of the array substrate in the display area and the front projection of the connection portion 711 on the plane of the array substrate do not overlap, the front projection of the second shielding structure 92 on the plane of the array substrate may be located between the front projection of the clock signal line 21 or the trigger signal line 22 on the plane of the array substrate in the display area and the front projection of the connection portion 711 on the plane of the array substrate.

For another example, in the case where the front projection of the clock signal line 21 or the trigger signal line 22 in the display area on the plane of the array substrate overlaps with the front projection of the connection portion 711 on the plane of the array substrate, the film layer where the second shielding structure 92 is located may be located between the film layer where the clock signal line 21 or the trigger signal line 22 is located and the film layer where the connection portion 711 is located, and the front projection of the clock signal line 21 or the trigger signal line 22 in the display area on the plane of the array substrate, and the front projection of the connection portion 711 on the plane of the array substrate may overlap.

The second shielding structure 92 may be in a floating (floating) state, or the first shielding structure 91 may be used to connect the fixed signal terminals.

In some embodiments, the display region of the array substrate may further include a reset signal line and a power signal line. For example, as shown in fig. 14, the reset signal lines may include a first reset signal line Vref1 and a second reset signal line Vref2. The first reset signal line Vref1 may be used to transmit a first reset signal to the gate of the driving transistor M13 in the pixel circuit, and the second reset signal line Vref2 may be used to transmit a second reset signal to the anode of the light emitting element D.

The power supply signal line PVDD may be used to boost the positive supply voltage.

For example, at least one of the first reset signal line Vref1 and the second reset signal line Vref2 may be multiplexed as the shielding structure 90 in the above example. For another example, the power supply signal line PVDD may be multiplexed as the shielding structure 90 in the above example. In this way, the structure of the array substrate can be simplified.

Note that the structure of the pixel circuit 71 shown in fig. 14 is merely an example, and is not intended to limit the present application.

Based on the same inventive concept, the application further provides a display panel. The display panel provided by the embodiment of the application can comprise the array substrate in any embodiment. The display panel provided by the embodiment of the application can be an Organic Light-Emitting Diode (OLED) display panel.

Those skilled in the art will appreciate that in other implementations of the application, the display panel may also be a Micro light emitting diode (Micro LED) display panel, a quantum dot display panel, or the like.

The display panel provided by the embodiment of the application has the beneficial effects of the array substrate provided by the embodiment of the application, and the specific description of the array substrate by referring to the embodiments can be referred to, and the embodiment is not repeated here.

The application also provides a display device comprising the display panel provided by the application. Referring to fig. 15, fig. 15 is a schematic structural diagram of a display device according to an embodiment of the application. Fig. 15 provides a display device 1000 including a display panel according to any of the above embodiments of the present application. The embodiment of fig. 15 is only an example of a mobile phone, and the display device 1000 is described, and it is to be understood that the display device provided in the embodiment of the present application may be a wearable product, a computer, a television, a vehicle-mounted display device, or other display devices with display functions, which is not particularly limited in the present application. The display device provided by the embodiment of the present application has the beneficial effects of the display panel provided by the embodiment of the present application, and the specific description of the display panel in the above embodiments may be referred to specifically, and this embodiment is not repeated here.

These embodiments are not exhaustive of all details, nor are they intended to limit the application to the precise embodiments disclosed, in accordance with the application. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and the practical application, to thereby enable others skilled in the art to best utilize the application and various modifications as are suited to the particular use contemplated. The application is limited only by the claims and the full scope and equivalents thereof.

Claims

1. An array substrate having a display region and a non-display region at least partially surrounding the display region, the array substrate comprising:

the grid driving circuit is positioned in the non-display area and comprises a plurality of cascaded shift register units;

a clock signal line electrically connected to the plurality of shift register units;

a trigger signal line electrically connected to at least one of the shift register units;

at least one of the clock signal line and the trigger signal line is located in the display region.

2. The array substrate of claim 1, wherein at least the clock signal line is located in the display region, and the non-display region includes a step region;

the array substrate further comprises a first winding and a second winding, the clock signal wire is electrically connected with the plurality of shift register units through the first winding and the second winding, the first winding is connected between the clock signal wire and the second winding, the second winding is connected with the shift register units, the first winding and the second winding are both located in the non-display area, and the first winding and the step area are spaced apart from each other by the display area.

3. The array substrate of claim 2, wherein the clock signal line extends along a first direction, the gate driving circuit is located between the second wire and the display area in a second direction, the second wire includes a plurality of wire segments connected to each other, at least two of the wire segments are located in different film layers, and the second direction intersects the first direction.

4. The array substrate of claim 1, wherein,

the grid driving circuit comprises a first grid driving circuit and a second grid driving circuit, the first grid driving circuit comprises a plurality of cascaded first shift register units, and the second grid driving circuit comprises a plurality of cascaded second shift register units;

the first shift register unit and the second shift register unit are positioned at two sides of the display area, the clock signal lines comprise a first type clock signal line and a second type clock signal line, the first type clock signal line is close to and electrically connected with the first shift register unit, and the second type clock signal line is close to and electrically connected with the second shift register unit.

5. The array substrate of claim 1, wherein the clock signal line is located in the display area and extends in a first direction, the array substrate further comprising a connection line through which the clock signal line is electrically connected to the plurality of shift register units, the connection line being located between the clock signal line and the shift register units in a second direction, the second direction intersecting the first direction.

6. The array substrate according to claim 5, wherein the clock signal lines include a first clock signal line and a second clock signal line, the connection lines include a first connection line connected between the first clock signal line and the i-th stage of the shift register unit, a second connection line connected between the second clock signal line and the i+1-th stage of the shift register unit, and a third connection line connected between the second connection line and the i-th stage of the shift register unit, and a fourth connection line connected between the first connection line and the i+1-th stage of the shift register unit, i being an odd number.

7. The array substrate of claim 6, wherein at least a portion of the first connection line is located in the display area, at least a portion of the second connection line is located in the display area, and the third connection line and the fourth connection line are located in the non-display area.

8. The array substrate of claim 7, wherein the display area of the array substrate further comprises a plurality of gate wires, the output end of the i-th stage of the shift register unit is electrically connected with the i-th gate wire, and the output end of the i+1-th stage of the shift register unit is electrically connected with the i+1-th gate wire;

the ith-stage shift register unit generates a gate control signal based on a signal on the second clock signal line, and the (i+1) -th-stage shift register unit generates a gate control signal based on a signal on the first clock signal line;

in the extending direction of the clock signal line, the distance between the first connecting line connected with the ith level of shift register unit and the ith grid electrode wiring is d1, the distance between the second connecting line connected with the (i+1) th level of shift register unit and the ith grid electrode wiring is d2, and d1 is smaller than d2;

the distance between the first connecting wire connected with the i-th level shift register unit and the i+1th grid electrode wiring is d3, the distance between the second connecting wire connected with the i+1th level shift register unit and the i+1th grid electrode wiring is d4, and d3 is more than d4.

9. The array substrate of claim 8, wherein the display area of the array substrate further comprises a plurality of rows of pixel circuits, an ith of the gate wires is electrically connected to an ith row of the pixel circuits, and an (i+1) th of the gate wires is electrically connected to an (i+1) th row of the pixel circuits;

the first connecting wire connected with the i-th level shift register unit is overlapped with the orthographic projection of the pixel circuit of the i-th line on the plane of the array substrate, and the first connecting wire connected with the i-th level shift register unit is not overlapped with the orthographic projection of the pixel circuit of the i+1-th line on the plane of the array substrate;

the second connection line connected with the i+1 level shift register unit is not overlapped with the orthographic projection of the pixel circuit of the i line on the plane of the array substrate, and the second connection line connected with the i+1 level shift register unit is overlapped with the orthographic projection of the pixel circuit of the i+1 line on the plane of the array substrate.

10. The array substrate according to claim 1, wherein the display area of the array substrate further comprises a data line, and the clock signal line and/or the trigger signal line and the data line in the display area are located in different film layers.

11. The array substrate of claim 1, further comprising:

a pixel circuit located in the display area;

a dummy pixel circuit located between the gate driving circuit and the pixel circuit in a second direction, the extension direction of the clock signal line being a first direction, the second direction intersecting the first direction;

and the orthographic projection of the clock signal line and/or the trigger signal line on the plane of the array substrate in the display area is at least partially overlapped with the orthographic projection of the virtual pixel circuit on the plane of the array substrate.

12. The array substrate of claim 1, further comprising:

a pixel circuit located in the display area;

a dummy pixel circuit located between the gate driving circuit and the pixel circuit in the second direction;

and the orthographic projection of the clock signal line and/or the trigger signal line on the plane of the array substrate in the display area is at least partially overlapped with the orthographic projection of the pixel circuit on the plane of the array substrate.

13. The array substrate of claim 12, wherein the display area of the array substrate further comprises a data line and a shielding structure, the shielding structure comprising a first shielding structure between the data line and the clock signal line or the trigger signal line in the display area.

14. The array substrate according to claim 12, wherein the pixel circuit includes a driving transistor and a connection portion connected to a gate electrode of the driving transistor, the display region of the array substrate further includes a shielding structure including a second shielding structure between the connection portion and the clock signal line or the trigger signal line in the display region.

15. The array substrate of claim 13 or 14, wherein the display area further comprises a reset signal line multiplexed into the shielding structure;

or, the display area further includes a power signal line, and the power signal line is multiplexed into the shielding structure.

16. A display panel comprising an array substrate according to any one of claims 1 to 15.

17. A display device comprising the display panel of claim 16.