CN116660590A - Programmable adapter plate, chip testing system and method - Google Patents

Abstract

The application relates to the field of chip testing, and discloses a programmable adapter plate, a chip testing system and a method. The programmable adapter plate comprises a circuit board, a plurality of analog switch chips and a chip socket, wherein the analog switch chips and the chip socket are arranged on the circuit board; the chip socket is used for fixing the chip to be tested; the analog switch chip is used for receiving the connection point control information from the test platform, and controlling the pins of the analog switch chip to be connected with the target pins of the chip to be tested in a preset mode according to the connection point control information so that the test platform tests the chip to be tested; the target pins are pins to be tested. According to the embodiment of the application, the programmable adapter plate is programmed to correspondingly control the programmable adapter plate to be connected with the target pin of the chip to be tested in any preset mode, so that the chips in different packaging modes can be connected and tested, one-board multi-purpose is realized, the testing flexibility and the testing efficiency are improved, and the method has good practicability.

Description

Programmable adapter plate, chip testing system and method

Technical Field

The present application relates to the field of chip testing, and in particular, to a programmable interposer, a chip testing system and a method.

Background

The existing chip testing method basically adopts a mode of fixedly connecting a testing connecting plate, and the testing connecting plate is manufactured by one-time board punching aiming at the packaging modes of different chips to be tested; that is, different types of test patch panels need to be individually customized for each type of chip test; the general test adapter plate is only compatible with the connection of chips to be tested in one or more packaging modes, after the chip test is completed, the test adapter plate is basically scrapped, and a new test connection plate is required to be manufactured by re-plating during the subsequent test of other chips. Furthermore, the chip testing method is extremely troublesome and has high manufacturing cost, so that the chip testing flexibility is poor and the testing efficiency is low.

Disclosure of Invention

In view of the above, in order to solve the defects existing in the prior art, the embodiment of the application provides a programmable adapter plate, a chip testing system and a method.

In a first aspect, the present application provides a programmable interposer, where the programmable interposer includes a circuit board, and a plurality of analog switch chips and chip sockets disposed on the circuit board;

the chip socket is used for fixing a chip to be tested;

the analog switch chip is used for receiving connection point control information from the test platform, and controlling the pins of the analog switch chip to be connected with the target pins of the chip to be tested in a preset mode according to the connection point control information so that the test platform tests the chip to be tested; the target pins are pins to be tested.

In an alternative embodiment, the chip socket includes a lock socket;

both sides of the locking socket are provided with dial switches; the dial switch is used for switching on or switching off the connection between the locking socket and the analog switch chip so as to switch on or switching off the connection between the chip to be tested and the test platform.

In an alternative embodiment, two groups of analog switch chips are symmetrically arranged on two sides of the chip socket respectively, and each group of analog switch chips comprises two analog switch chips arranged side by side.

In an alternative embodiment, each of the analog switch chips includes a plurality of input connection points and a plurality of output connection points;

each output connection point is used for switching connection or simultaneously connecting at most eight pins of the chip to be tested; each input connection point is correspondingly connected with a corresponding pin of the test platform.

In an alternative embodiment, the chip to be tested is disposed in the middle of the plurality of analog switch chips, and pins on two sides of the chip to be tested are respectively connected with input connection points of the analog switch chips on the same side in a nearby manner.

In an alternative embodiment, a programming interface is provided on the programmable adapter board, the programmable adapter board is connected to the test platform through the programming interface, and the programming interface is used for receiving connection point control information from the test platform.

In an alternative embodiment, the locking socket is a DIP32 encapsulated locking socket.

In an alternative embodiment, the chip socket includes a round hole chip socket.

In a second aspect, the present application provides a chip test system, comprising a test platform and a programmable interposer according to any of the preceding embodiments;

the test platform is used for performing program setting on the programmable adapter plate and generating connection point control information;

the programmable adapter plate is used for fixing a chip to be tested through the chip socket, and controlling the pins of the analog switch chip on the programmable adapter plate to be connected with the target pins of the chip to be tested in a preset mode according to the connection point control information so that the test platform tests the chip to be tested; the target pins are pins to be tested.

In a third aspect, the present application provides a chip testing method, applied to a chip testing system as described above; the method comprises the following steps:

the test platform performs program setting on the programmable adapter plate to generate connection point control information;

the programmable adapter plate is used for fixing a chip to be tested through a chip socket, and controlling pins of an analog switch chip on the programmable adapter plate to be connected with target pins of the chip to be tested in a preset mode according to the connection point control information so that the test platform can test the chip to be tested; the target pins are pins to be tested.

The embodiment of the application has the following beneficial effects:

the embodiment of the application provides a programmable adapter plate, which particularly comprises a circuit board, a plurality of analog switch chips and chip sockets, wherein the analog switch chips and the chip sockets are arranged on the circuit board; the chip socket is used for fixing the chip to be tested; the analog switch chip is used for receiving the connection point control information from the test platform, and controlling the pins of the analog switch chip to be connected with the target pins of the chip to be tested in a preset mode according to the connection point control information so that the test platform tests the chip to be tested. According to the embodiment of the application, the programmable adapter plate is correspondingly controlled to be connected with the target pin of the chip to be tested in a preset mode by programming the programmable adapter plate, so that the automatic connection control between the programmable adapter plate and the chip to be tested is realized, and the testing flexibility and the testing efficiency are improved. And the programmable adapter plate can be expanded, and the programmable adapter plate can be connected with pins corresponding to the chips to be tested by programming the programmable adapter plate aiming at the chips to be tested in different packaging modes, so that the chips in different packaging modes are connected and tested, one-board multi-purpose is realized, the additional manufacture of the adapter plate is not needed, the cost is reduced, and the programmable adapter plate has good practicability.

Drawings

In order to more clearly illustrate the technical solutions of the present application, the drawings that are required for the embodiments will be briefly described, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope of the present application. Like elements are numbered alike in the various figures.

FIG. 1 is a schematic diagram of a chip test system according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a programmable interposer according to an embodiment of the present application;

FIG. 3 is a schematic diagram showing interaction between a programmable interposer and a test platform in an embodiment of the present application;

FIG. 4 is a schematic diagram showing a connection relationship of a chip test system according to an embodiment of the present application;

fig. 5 is a schematic diagram of a chip testing method according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments.

The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present application.

The terms "comprises," "comprising," "including," or any other variation thereof, are intended to cover a specific feature, number, step, operation, element, component, or combination of the foregoing, which may be used in various embodiments of the present application, and are not intended to first exclude the presence of or increase the likelihood of one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.

Furthermore, the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the application belong. The terms (such as those defined in commonly used dictionaries) will be interpreted as having a meaning that is the same as the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in connection with the various embodiments of the application.

Because the existing chip testing method basically adopts a mode of fixedly connecting a testing connecting plate, and each type of chip test needs to independently customize different types of testing adapter plates, the testing flexibility is poor; in addition, if the number of pins of the chip to be tested is larger, the corresponding wires are larger, the testing steps are more complicated, and the testing error rate is higher and the testing efficiency is low.

Referring to fig. 1, a chip testing system is provided according to an embodiment of the present application, and the system includes a testing platform 100 and a programmable interposer 200. The programmable adapter board 200 is programmed to correspondingly control the programmable adapter board 200 to be arbitrarily connected with the target pin of the chip 300 to be tested in a preset mode, so that automatic connection control between the programmable adapter board 200 and the chip 300 to be tested is realized, and the testing flexibility and the testing efficiency are improved. In addition, the programmable adapter plate 200 can be expanded to realize connection and test of chips in different packaging modes, so that one-plate multi-purpose is realized, the adapter plate does not need to be additionally manufactured, the cost is reduced, and the programmable adapter plate has good practicability.

In this embodiment, the programmable interposer 200 is an intermediate layer connected between the test platform 100 and the chip 300 to be tested, and the programmable interposer 200 is respectively connected to the test platform 100 and the chip 300 to be tested.

Illustratively, the programmable interposer 200 is used to secure the chip 300 under test through the chip socket 230; the test platform 100 is configured to perform program setting on the programmable interposer 200 when it is determined that the programmable interposer 200 is connected with the chip 300 to be tested and the corresponding pins of the chip 300 to be tested are required to be tested, generate connection point control information, and send the connection point control information to the programmable interposer 200.

Furthermore, the programmable adapter board 200 is configured to control, according to the connection point control information, the connection between the pins of the analog switch chip 220 on the programmable adapter board 200 and the target pins of the chip 300 to be tested in a predetermined manner, so that the test platform 100 tests the chip 300 to be tested; the target pins are pins to be tested in the chip 300 to be tested.

It can be understood that, by programming the programmable interposer 200, the test platform 100 correspondingly adjusts the connection mode between the programmable interposer 200 and the pins of the chip 300 to be tested, and further, the programmable interposer 200 can be adapted to connect with the chips 300 to be tested in different package forms, so as to realize the test of the test platform 100 on the chips 300 to be tested in different package forms. In addition, in the testing process, according to different testing items, the connection mode between the programmable adapter board 200 and the pins of the chip 300 to be tested can be correspondingly adjusted, and then the connection relation between the testing platform 100 and the chip 300 to be tested is correspondingly adjusted, so that different tests on the chip 300 to be tested are realized, the flexibility and the automation degree of the test are improved, and the testing efficiency is further improved.

Further, as shown in fig. 2 and 3, the present application further provides a programmable patch panel 200, where the programmable patch panel 200 includes a circuit board 210, and a plurality of analog switch chips 220 and chip sockets 230 disposed on the circuit board 210.

Illustratively, the chip socket 230 is used for fixing the chip 300 to be tested; the analog switch chip 220 is configured to receive connection point control information from the test platform 100, and control, according to the connection point control information, a pin of the analog switch chip 220 to be connected with a target pin of the chip 300 to be tested in a predetermined manner, so that the test platform 100 tests the chip 300 to be tested; the target pins are pins to be tested.

In short, the chip 300 to be tested is placed on the chip socket 230 of the programmable interposer 200, and the target pins of the chip 300 to be tested are determined according to the pin row sequence of the chip 300 to be tested, and then the programmable interposer 200 is programmed by the test platform 100, so that the target pins of the chip 300 to be tested are connected with the test platform 100, thereby realizing communication between the test platform 100 and the chip 300 to be tested.

In this embodiment, the programmable patch panel 200 is provided with a programming interface, and the programmable patch panel 200 is connected to the test platform 100 through the programming interface, and the programming interface is used for receiving the connection point control information from the test platform 100. That is, the test platform 100 adjusts the connection between the pins of the analog switch chip 220 and the corresponding pins of the chip 300 to be tested in the programmable adapter board 200 through the programming interface, so as to control the programmable adapter board 200 to be connected with the pins of one side of the chip 300 to be tested in any mode.

It can be understood that, by performing communication between the test platform 100 and the programmable adapter board 200, the test platform 100 writes corresponding connection point control information into the programming interface of the programmable adapter board, so as to control the corresponding pins of the corresponding module switch chip of the programmable multifunctional board to be connected with the chip 300 to be tested.

In one embodiment, two groups of analog switch chips 220 are symmetrically arranged on two sides of the chip socket 230 of the programmable interposer 200, and each group of analog switch chips 220 includes two analog switch chips 220 arranged side by side. Alternatively, the analog switch chip 220 may be a MT8808 type chip.

Further, each analog switch chip 220 includes a plurality of input connection points and a plurality of output connection points; each output connection point is used for switching connection or simultaneously connecting at most eight pins of the chip 300 to be tested; each input connection point is respectively and correspondingly connected with a corresponding pin of the test platform 100. That is, one output pin of each analog switch chip 220 is connected to at most eight pins of the chip 300 under test.

The chip 300 to be tested is disposed in the middle of the plurality of analog switch chips 220, and pins on two sides of the chip 300 to be tested are respectively connected with input connection points of the analog switch chips 220 on the same side nearby.

As an alternative embodiment, chip receptacle 230 includes a snap-lock receptacle and/or a round hole chip receptacle 230. If the chip socket 230 is a locking socket, both sides of the locking socket are provided with dial switches; the dial switch is used for switching on or off the connection between the locking socket and each analog switch chip 220, and further switching on or off the connection between the chip 300 to be tested and the test platform 100. Alternatively, the locking socket may be a locking socket packaged in the DIP32 format.

It can be understood that the dial switches on two sides of the locking socket are disposed between the locking socket and the analog switch chip 220, and if communication between the analog switch chip 220 and the locking socket is not required, the chip 300 to be tested and the test platform 100 can be physically isolated by the dial switches, so as to ensure that the chip 300 to be tested is not affected by the output signal of the test platform 100.

Further, a dial switch may control communication between the two analog switch chips 220 and the lock socket, respectively. The connection manner between the dial switch and the analog switch chip 220 can be set according to the requirement, and is not limited herein.

For example, an input connection point and eight output connection points can be arbitrarily programmed in each analog switch chip 220, and it is understood that it is equivalent to that one pin of the analog switch chip 220 can be arbitrarily connected with eight pins of the chip 300 to be tested.

Referring to fig. 3 and 4 together, the programmable interposer of an embodiment of the present application includes eight analog switch chips 220 (i.e., analog switch chips 1# through 8# as shown in fig. 4). The IO pin on one side of the analog switch chip 1# is connected with the 1-8 pins of the test platform 100, the IO pin on the other side of the analog switch chip 1# is connected with the 1-8 pins of the test platform 100, the IO pin on one side of the analog switch chip 2# is connected with the 1-8 pins of the test platform 100, and the IO pin on the other side of the analog switch chip 2# is connected with the 9-16 pins of the test platform 300, so that the 1-8 pins of the test platform 100 can be randomly connected with the 1-16 pins of the test platform 300 through the analog switch chip 1# and the analog switch chip 2#.

In the same way, the analog switch chip 3# and the analog switch chip 4# can be connected with pins 9-16 of the test platform 100, and then pins 9-16 of the test platform 100 can be connected with pins 1-16 of the chip 300 to be tested at will. Therefore, the connection mode of pins 17 to 32 on the other side of the chip 300 to be tested is similar to the above.

It should be noted that, in the chip test system of the embodiment of the present application, the test platform 100 may program the programmable adapter board 200 according to the pin sequence of the programmable adapter board 200 and the pin sequence of the chip 300 to be tested, so as to control the pins of the programmable adapter board 200 and the pins to be tested on the chip 300 to be tested to be connected in a predetermined manner, so as to correspondingly change the connection relationship between each connection point of the test platform 100 and the pins of the chip 300 to be tested, and further, in the test process, the connection relationship with the chip 300 to be tested may be correspondingly adjusted according to different test items, so that the degree of automation of the test platform 100 is higher, the flexibility of the test process is higher, the labor is saved, the test cost is reduced, and the problem that the connection is tedious and the connection is easy to be misplaced when the chip is tested by a tester is avoided.

Furthermore, as shown in fig. 4, the chip test system provided by the embodiment of the present application can realize that 16 pins on any side of the chip 300 to be tested are connected with any pin of the test platform 100 in a programming manner without changing the hardware connection line, and if the connection is a full connection manner, 16×16 connection manners can be realized.

That is, the programmable adapter board 200 provided in the embodiment of the present application realizes a switching circuit capable of freely selecting and connecting with 16 circuits on one side of the chip 300 to be tested and a circuit capable of freely selecting and switching with 32 circuits on two sides of the chip 300 to be tested by carrying eight programmable analog switch chips 220.

In addition, according to the programmable adapter board 200 provided by the embodiment of the application, one programmable adapter board 200 can be arbitrarily connected with a chip 300 to be tested with 32 pins or less; the programmable adapter board 200 can also be expanded to realize connection with the chip 300 to be tested with multiple pins (more than 32 pins); furthermore, the programmable adapter board 200 can be infinitely expanded in theory, so that the connection with the chip 300 to be tested with any pin number is realized, the application scene of chip test is correspondingly enlarged, and the practicability of the chip test is improved.

Further, compared with the conditions that the test adapter plate in the prior art is inflexible, single in function, not universal and waste resources are not environment-friendly, the programmable multifunctional adapter plate provided by the embodiment of the application can greatly improve the test efficiency, and the programmable adapter plate 200 can be suitable for being connected with the chips 300 to be tested in different packaging modes through an expansion mode, so that one-board multi-purpose is realized, the adapter plate adapting to different packaging modes is prevented from being manufactured again, and the environment is protected and saved. Under the condition of not changing a hardware circuit, the connection relation between each pin of the test platform 100 and the target pin of the chip 300 to be tested can be changed by programming the analog switch chip 220, so that the connection relation between the test platform 100 and the chip 300 to be tested can be set at will according to different test items, the automation control degree of the test platform 100 is higher, the labor cost is saved, and the test cost is reduced.

As shown in fig. 5, the embodiment of the present application further provides a chip testing method, which can be applied to a chip testing system including the programmable interposer 200 of the foregoing embodiment; the method will be described in detail below.

S10, the test platform 100 performs program setting on the programmable adapter board 200 to generate connection point control information.

S20, the programmable adapter board 200 fixes the chip 300 to be tested through the chip socket, and according to the control information of the connection point, the pins of the analog switch chip 220 on the programmable adapter board 200 are controlled to be connected with the target pins of the chip 300 to be tested in a preset mode, so that the test platform 100 tests the chip 300 to be tested; the target pins are pins to be tested.

Based on the system test system and the programmable adapter board 200, after determining the pin arrangement sequence of the programmable adapter board 200 and the pin arrangement sequence of the chip 300 to be tested, the test platform 100 further performs program setting on the programmable adapter board 200 to generate connection point control information, and the programmable adapter board 200 enables corresponding pins of the corresponding analog switch chip 220 to be connected with target pins of the chip 300 to be tested according to the connection point control information; thus, the test platform 100 can be arbitrarily connected with the target pins of the chip 300 to be tested, so as to realize communication, and the test platform 100 can test the chip 300 to be tested in the connection mode.

According to the embodiment of the application, through the test platform 100, the connection point control information of the pin connection corresponding to the programmable adapter plate 200 and the chip 300 to be tested is written into the analog switch chip 220 of the programmable adapter plate 200 in a programming mode, so that the free connection of the corresponding pins between the programmable adapter plate 200 and the chip 300 to be tested is realized, the free connection between the test platform 100 and the chip 300 to be tested is further realized, the connection control is unified control in a programming mode, namely, the automatic control and connection are realized, the manual repeated wiring and wire replacement are not needed, the labor cost is saved, and the test efficiency is improved.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application.

Claims (10)

1. The programmable adapter plate is characterized by comprising a circuit board, a plurality of analog switch chips and chip sockets, wherein the analog switch chips and the chip sockets are arranged on the circuit board;

the chip socket is used for fixing a chip to be tested;

the analog switch chip is used for receiving connection point control information from the test platform, and controlling the pins of the analog switch chip to be connected with the target pins of the chip to be tested in a preset mode according to the connection point control information so that the test platform tests the chip to be tested; the target pins are pins to be tested.

2. The programmable interposer of claim 1, wherein the chip socket comprises a lock socket;

both sides of the locking socket are provided with dial switches; the dial switch is used for switching on or switching off the connection between the locking socket and the analog switch chip so as to switch on or switching off the connection between the chip to be tested and the test platform.

3. The programmable interposer of claim 1 or 2, wherein two groups of said analog switch chips are symmetrically arranged on each side of said chip socket, each group of said analog switch chips comprising two of said analog switch chips arranged side-by-side.

4. The programmable interposer of claim 1, wherein each of the analog switch chips comprises a plurality of input connection points and a plurality of output connection points;

each output connection point is used for switching connection or simultaneously connecting at most eight pins of the chip to be tested; each input connection point is correspondingly connected with a corresponding pin of the test platform.

5. The programmable interposer of claim 1 or 4, wherein the chip to be tested is disposed in the middle of the plurality of analog switch chips, and pins on two sides of the chip to be tested are respectively connected with input connection points of the analog switch chips on the same side nearby.

6. The programmable interposer of claim 1, wherein a programming interface is provided on the programmable interposer, the programmable interposer being connected to the test platform through the programming interface, the programming interface being configured to receive connection point control information from the test platform.

7. The programmable interposer of claim 2, wherein the locking socket is a DIP32 style packaged locking socket.

8. The programmable interposer of claim 1 or 2, wherein the chip socket comprises a round hole chip socket.

9. A chip testing system comprising a test platform and a programmable interposer according to any one of claims 1-8;

the test platform is used for performing program setting on the programmable adapter plate and generating connection point control information;

the programmable adapter plate is used for fixing a chip to be tested through the chip socket, and controlling the pins of the analog switch chip on the programmable adapter plate to be connected with the target pins of the chip to be tested in a preset mode according to the connection point control information so that the test platform tests the chip to be tested; the target pins are pins to be tested.

10. A chip testing method, characterized by being applied to the chip testing system according to claim 9; the method comprises the following steps:

the test platform performs program setting on the programmable adapter plate to generate connection point control information;

the programmable adapter plate is used for fixing a chip to be tested through a chip socket, and controlling pins of an analog switch chip on the programmable adapter plate to be connected with target pins of the chip to be tested in a preset mode according to the connection point control information so that the test platform can test the chip to be tested; the target pins are pins to be tested.