CN116648843A - DC-DC Converter with Improved Line Transient Suppression - Google Patents
DC-DC Converter with Improved Line Transient Suppression Download PDFInfo
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- CN116648843A CN116648843A CN202180086271.1A CN202180086271A CN116648843A CN 116648843 A CN116648843 A CN 116648843A CN 202180086271 A CN202180086271 A CN 202180086271A CN 116648843 A CN116648843 A CN 116648843A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The present application provides a simulated peak current mode control (EPCMC) synchronous buck converter apparatus, which may include: a converter having an inductor, a high side switch and a low side switch, and an EPCM controller. The controller may include: a PWM latch for alternately turning on and off the high-side switch and the low-side switch; a current sensing element for outputting a current sensing voltage based on the inductor current; and a feedforward circuit for generating a feedforward voltage. The current sensing element outputs a first current sense voltage when the low side switch is on and outputs a second current sense voltage when the low side switch is off. The feed-forward voltage is generated based on a voltage difference representing a difference between the first current sense voltage and the second current sense voltage, and the PWM latch alternately turns on and off the high-side switch and the low-side switch based on the feed-forward voltage.
Description
Cross-reference to related patent applications
The present application claims the benefit of U.S. provisional patent application No. 63/129,867, filed on 12/23 in 2020, which is incorporated herein by reference in its entirety.
Technical Field
The present disclosure relates generally to DC-DC power converters, and more particularly to DC-DC power converters that use an emulated peak current mode control architecture to provide a power supply output that is less susceptible to power line voltage disturbances.
Background
Many automotive and industrial applications of DC-DC power converters are characterized by severe mains voltage disturbances. When the DC-DC converter is powering a noise sensitive system, it is highly desirable that power line transients not propagate to the power supply output. Peak Current Mode Control (PCMC) is known for its good power supply rejection due to inherent input voltage feed forward.
FIG. 1 shows a DC input voltage V configured to be received from an input voltage source 101 IN And adjusts the output voltage V at the load 112 O Is described herein) a PCMC synchronous buck converter device. The PCMC synchronous buck converter device of fig. 1 includes a converter 100B that includes a high-side switch 108, a low-side switch 109, an inductor 110, and a smoothing capacitor 111. The converter device further comprises a controller 100A comprising a gate driver 107, a Pulse Width Modulation (PWM) latch 106 implemented as an RS flip-flop, an oscillator circuit 104 configured to generate a series of clock pulses, a current sense comparator 105, a differential circuit 105B, a current sense element 103, a current control command voltage V CONT Source 102 and slope compensation ramp voltage V RAMP A generator 113. When high-side switch 108 is on, current sense element 103 monitors current I in inductor 110 L . When the PWM latch 106 receives the clock signal from the oscillator circuit 104, the low-side switch 109 is turned off and the high-side switch 108 is turned on, thereby charging the inductor 110. The current sense element 103 outputs a current sense voltage that is provided to a non-inverting input of the current sense comparator 105. Differential circuit 105B receivesSlope compensation ramp voltage V RAMP And a current control command voltage V CONT And outputs a difference therebetween, which is a threshold voltage provided to an inverting input of the current sense comparator 105. When the current sense voltage exceeds the threshold voltage, the current sense comparator 105 outputs a control signal that resets the PWM latch 106, which causes the high side switch 108 to turn off and the low side switch 109 to turn on.
As is well known, the slope compensates for the ramp voltage V RAMP The optimal choice of slew rate of (c) may achieve substantially zero sensitivity to input power disturbances. However, this approach has been shown to be extremely sensitive to variations in the values of the inductor 110 and the current sensing element 103, and thus may not be practical. Furthermore, a slope compensation ramp voltage V is selected based on the criteria RAMP May create underdamping performance of the current loop.
With a wide range of supply voltages (i.e. a wide range of DC input voltages V IN ) The application of features sometimes uses a simulated current mode control in which the current sense voltage is replaced by an artificial ramp. In such a converter, the current sense voltage is sampled in the previous switching cycle and used as an initial condition for the emulated ramp in the next cycle. The simulated peak current mode control (EPCMC) with valley current sampling is characterized by the same inherent power supply rejection characteristics as PCMC.
Fig. 2 shows a prior art EPCMC synchronous buck converter device. Unlike the PCMC synchronous buck converter device of fig. 1, the controller 100A of the EPCMC synchronous buck converter device of fig. 2 includes a dc converter having a gain R i Current sensing element 123, first sample-and-hold circuit 115, ramp voltage V RAMP Generator 114 and summing circuit 105A, and does not include current sensing element 103. The current sensing element 123 is configured to monitor the current I in the inductor 110 when the low side switch 109 is on L . The current sensing element 123 outputs a current sensing voltage that is sampled by the first sample-and-hold circuit 115 at the end of the on-time interval of the low-side switch 109. The summing circuit 105A senses the voltage from the sampled current and a voltage V from the ramp RAMP Ramp generated by generator 114Voltage V RAMP Summed, and the current sense comparator 105 will sample the current sense voltage and the ramp voltage V RAMP And control command voltage V CONT A comparison is made.
Similar to the PCMC synchronous buck converter device of fig. 1, the ramp voltage V may be selected RAMP To achieve a conversion rate to the input power supply voltage V IN Is substantially zero sensitivity. However, this approach suffers from the same drawbacks as the converter of fig. 1, in particular depending on the gain R of the current sensing element 123 i And the value of inductor 110. Considering that the EPCMC synchronous buck converter device of fig. 2 is targeted for applications characterized by a wide input voltage range and severe power line disturbances, it is desirable to be able to overcome these drawbacks and create a controller for a practical EPCMC synchronous buck converter device.
Disclosure of Invention
In accordance with an aspect of one or more exemplary embodiments, an Emulated Peak Current Mode Control (EPCMC) synchronous buck converter device is provided that may include a converter configured to receive an input voltage and generate an output voltage. The converter may include an inductor, a high-side switch, and a low-side switch, wherein the high-side switch and the low-side switch may be coupled to the inductor and configured to control an inductor current through the inductor. The EPCMC synchronous buck converter device may also include an Emulated Peak Current Mode (EPCM) controller having a Pulse Width Modulation (PWM) latch configured to alternately turn on and off the high side switch and the low side switch, a current sensing element configured to output a current sense voltage based on an inductor current through the inductor, and a feed forward circuit configured to generate a feed forward voltage. The current sensing element may output a first current sense voltage at a first time when the low side switch is on and may output a second current sense voltage at a second time delayed from the first time but still during an on period of the low side switch. The feedforward circuit may generate the feedforward voltage based on a voltage difference representing a difference between the first current sense voltage and the second current sense voltage. The PWM latch may be configured to alternately turn on and off the high side switch and the low side switch, respectively, based on the feed forward voltage.
The EPCM controller may further include: a ramp voltage generator configured to generate a ramp voltage; a current control command voltage source configured to generate a current control command voltage; and a current sense comparator comparing a sum of the ramp voltage and the second current sense voltage with a sum of the feedforward voltage and the current control command voltage, and outputting a control signal to the PWM latch based on the comparison. The PWM latch may be configured to alternately turn on and off the high-side switch and the low-side switch, respectively, based on a control signal output by the current sense comparator.
The EPCM controller may further include: a multiplier-divider circuit configured to multiply the voltage difference by a ratio of the output voltage to the input voltage; and a gain stage configured to amplify the output of the multiplier-divider circuit to generate a feedforward voltage.
The EPCM controller may further include a feed-forward differential circuit configured to be a difference between the output voltage difference and a voltage difference multiplied by a ratio of the output voltage and the input voltage. The gain stage may be configured to amplify a difference between the voltage difference and an output of the multiplier-divider circuit to generate a feedforward voltage.
The EPCM controller may further include: a first sample-and-hold circuit configured to sample a first current sense voltage at a first time and output a first sampled current sense voltage; a second sample-and-hold circuit configured to sample a second current sense voltage at a second time and output a second sampled current sense voltage; a current sense differential circuit configured to output a voltage difference that is a difference between a first sampled current sense voltage and a second sampled current sense voltage; and a delay circuit configured to delay sampling of the second current sense voltage by a time delay period after sampling of the first current sense voltage.
According to an exemplary embodiment, the EPCM controller may include: a multiplier-divider circuit configured to multiply the voltage difference by a ratio of the output voltage to the input voltage; a feed-forward differential circuit configured to subtract a voltage difference from an output of the multiplier-divider circuit; and a gain stage configured to amplify a difference between the voltage difference and an output of the multiplier-divider circuit to generate a feedforward voltage.
The EPCM controller may further include an oscillator circuit configured to generate a series of clock pulses, and the delay circuit may include a frequency divider configured to receive the series of clock pulses and generate a first frequency tap signal corresponding to a first clock pulse of the series of clock pulses and a second frequency tap signal corresponding to a second clock pulse of the series of clock pulses. The first sample-and-hold circuit may be configured to sample a first current sense voltage in response to a first frequency tap signal and the second sample-and-hold circuit may be configured to sample a second current sense voltage in response to a second frequency tap signal.
In accordance with an aspect of one or more exemplary embodiments, there is provided a simulated peak current mode (EPCM) controller for controlling a synchronous buck converter configured to receive an input voltage and generate an output voltage, the synchronous buck converter having an inductor, a high side switch, and a low side switch. The EPCM controller may include: a Pulse Width Modulation (PWM) latch configured to alternately turn on and off the high side switch and the low side switch; a current sensing element configured to output a current sensing voltage based on an inductor current through the inductor; and a feedforward circuit configured to generate a feedforward voltage. The current sensing element may output a first current sense voltage at a first time when the low side switch is on and may output a second current sense voltage at a second time delayed from the first time but still during an on period of the low side switch. The feedforward circuit may generate the feedforward voltage based on a voltage difference representing a difference between the first current sense voltage and the second current sense voltage. The PWM latch may be configured to alternately turn on and off the high side switch and the low side switch based on the feed forward voltage.
The EPCM controller may further include: a ramp voltage generator configured to generate a ramp voltage; a current control command voltage source configured to generate a current control command voltage; and a current sense comparator comparing a sum of the ramp voltage and the second current sense voltage with a sum of the feedforward voltage and the current control command voltage, and outputting a control signal to the PWM latch based on the comparison. The PWM latch may be configured to alternately turn on and off the high-side switch and the low-side switch based on a control signal output by the current sense comparator.
The EPCM controller may further include: a multiplier-divider circuit configured to multiply the voltage difference by a ratio of the output voltage to the input voltage; and a gain stage configured to amplify the output of the multiplier-divider circuit to generate a feedforward voltage.
The EPCM controller may further include: a first sample-and-hold circuit configured to sample a first current sense voltage at a first time and output a first sampled current sense voltage; a second sample-and-hold circuit configured to sample a second current sense voltage at a second time and output a second sampled current sense voltage; a current sense differential circuit configured to output a voltage difference that is a difference between a first sampled current sense voltage and a second sampled current sense voltage; and a delay circuit configured to delay sampling of the second current sense voltage by a time delay period after sampling of the first current sense voltage.
According to an exemplary embodiment, the EPCM controller may include: a multiplier-divider circuit configured to multiply the voltage difference by a ratio of the output voltage to the input voltage; a feed-forward differential circuit configured to subtract a voltage difference from an output of the multiplier-divider circuit; and a gain stage configured to amplify a difference between the voltage difference and an output of the multiplier-divider circuit to generate a feedforward voltage.
The EPCM controller may further include an oscillator circuit configured to generate a series of clock pulses, and the delay circuit may include a frequency divider configured to receive the series of clock pulses and generate a first frequency tap signal corresponding to a first clock pulse of the series of clock pulses and a second frequency tap signal corresponding to a second clock pulse of the series of clock pulses. The first sample-and-hold circuit may be configured to sample a first current sense voltage in response to a first frequency tap signal and the second sample-and-hold circuit may be configured to sample a second current sense voltage in response to a second frequency tap signal.
According to an aspect of one or more exemplary embodiments, there is provided a simulated peak current mode control (EPCMC) method of controlling a synchronous buck converter configured to receive an input voltage and generate an output voltage, and having an inductor, a high side switch, and a low side switch. The method may include: generating Pulse Width Modulation (PWM) signals to alternately turn on and off the high side switch and the low side switch, respectively; outputting a first current sense voltage based on an inductor current through the inductor at a first time when the low side switch is on; outputting a second current sense voltage based on an inductor current through the inductor at a second time delayed from the first time but still during the on period of the low side switch; and generating a feed-forward voltage based on a voltage difference representing a difference between the first current sense voltage and the second current sense voltage. The PWM signal may be generated based on the feed forward voltage.
The method may further comprise: generating a ramp voltage, generating a current control command voltage, comparing a sum of the ramp voltage and the second current sensing voltage with a sum of the feedforward voltage and the current control command voltage, and outputting a control signal based on the comparison. The PWM signal may be generated based on the control signal.
The method may further include multiplying the voltage difference by a ratio of the output voltage to the input voltage, and amplifying a result of the multiplying step to generate the feedforward voltage.
The method may further comprise: the first current sense voltage is sampled and a first sampled current sense voltage is output at a first time, and the second current sense voltage is sampled and a second sampled current sense voltage is output at a second time. The method may include outputting a voltage difference as a difference between the first sampled current sense voltage and the second sampled current sense voltage. Sampling the second current sense voltage may be delayed by a time delay period after sampling the first current sense voltage.
According to an exemplary embodiment, the method may include multiplying the voltage difference by a ratio of the output voltage to the input voltage, subtracting the voltage difference from a result of the multiplying step, and amplifying the subtracted result to generate the feedforward voltage.
The method may further comprise: a series of clock pulses is generated, a first frequency tap signal corresponding to a first clock pulse in the series of clock pulses is generated, and a second frequency tap signal corresponding to a second clock pulse in the series of clock pulses is generated. Sampling the first current sense voltage may include sampling the first current sense voltage in response to a first frequency tap signal, and sampling the second current sense voltage may include sampling the second current sense voltage in response to a second frequency tap signal.
Drawings
Fig. 1 shows a PCMC synchronous buck converter device according to the prior art.
Fig. 2 shows an EPCMC synchronous buck converter device according to the prior art.
Fig. 3 shows an EPCMC synchronous buck converter device according to an example embodiment.
Fig. 4 shows an EPCMC synchronous buck converter device according to another example embodiment.
Fig. 5 shows a waveform diagram of an EPCMC synchronous buck converter device according to the exemplary embodiment of fig. 4.
Fig. 6 shows an EPCMC synchronous buck converter device according to yet another exemplary embodiment.
Fig. 7 shows a waveform diagram of an EPCMC synchronous buck converter device according to the exemplary embodiment of fig. 6.
FIG. 8 illustrates an EPCMC synchronous buck converter device in accordance with an example embodiment;
fig. 9 shows a waveform diagram of an EPCMC synchronous buck converter device according to the exemplary embodiment of fig. 8.
Detailed Description
Reference will now be made in detail to the following exemplary embodiments, which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. The exemplary embodiments may be embodied in various forms and are not limited to the exemplary embodiments set forth herein. Descriptions of well-known parts are omitted for clarity.
Fig. 3 illustrates an EPCMC synchronous buck converter device according to an example embodiment that may address the deficiencies of the prior art described above. In addition to the components of the EPCMC synchronous buck converter device shown in fig. 2, EPCM controller 300A of the exemplary converter device of fig. 3 may additionally include a feed forward circuit 300C that includes multiplier-divider circuit 118, gain stage 119, summing circuit 119A, and current sense differential circuit 121. EPCM controller 300A of fig. 3 may also include a second sample and hold circuit 116 and a delay circuit 117 configured to introduce a time delay period t prior to setting PWM latch 106 implemented as an SR flip-flop DEL . In operation, the oscillator circuit 104 outputs a signal that causes the second sample-and-hold circuit 116 to delay time period t before the low-side switch 109 turns off DEL Is sampling and holding a first current sense voltage generated by the current sense element 123. Specifically, the delay circuit 117 also receives the signal output by the oscillator circuit 104, but delays the signal output by the oscillator circuit 104 to the PWM latch 106 for the time delay period t DEL . In response to the delay circuit 117 passing the signal output by the oscillator circuit 104 to the PWM latch 106, the PWM latch 106 outputs the signal to the gate driver 107 and to the first sample-and-hold circuit 115, which causes the high-side switch108 are on, the low side switch 109 is off, and the first sample-and-hold circuit 115 samples and holds the second current sense voltage generated by the current sense element 123 at a second time delayed from the first time but still during the on period of the low side switch 109. According to an exemplary embodiment, the second time may correspond to an end of the on period of the low side switch 109. The second sample-and-hold circuit 116 outputs a first sampled current sense voltage corresponding to a first current sense voltage generated by the current sense element 123 at a first time. The first sample-and-hold circuit 115 outputs a second sampled current sense voltage corresponding to a second current sense voltage generated by the current sense element 123 at a second time. The difference between the first and second sampled current sense voltages sampled by the second and first sample-and-hold circuits 116 and 115, respectively, is output as a voltage difference Δv by the current sense differential circuit 121 S And reflects the inductor current I L The slew rate of the downslope is represented by the following equation 1.
Wherein R is i Is the gain of the current sensing element 123.
The voltage difference Δv output by the current-sense differential circuit 121 S Is further fed into the input a of the multiplier-divider circuit 118 and multiplied by the ratio of its input voltages B and C. Input B of multiplier-divider circuit 118 receives output voltage V O While input C of multiplier-divider circuit 118 receives input voltage V IN . The output of the multiplier-divider circuit 118 is further divided by a gain of k=1/(2 f) SW ·t DEL ) Where f is amplified by gain stage 119 of (2) SW Is the switching frequency. The obtained feedforward voltage V FF Is output by gain stage 119 and added to current control command voltage V by summing circuit 119A CONT To generate a threshold voltage that may be provided to an inverting input of comparator 105. The summing circuit 105A samples and holds the signal that is sampled and held by the first sample-and-hold circuit 115A second current sense voltage and a voltage ramp V RAMP Ramp voltage V generated by generator 114 RAMP And (5) summing. The current sense comparator 105 senses the second current and the ramp voltage V RAMP And the feedforward voltage V output by the gain stage 119 FF And a current control command voltage V CONT And comparing. When the sum output by the summing circuit 105A exceeds the sum output by the summing circuit 119A, the current sense comparator 105 outputs a control signal that resets the PWM latch 106, which causes the high side switch 108 to turn off and the low side switch 109 to turn on.
Can realize V IN The feedforward voltage V of the converter device of fig. 3 with a substantially zero sensitivity to disturbances FF Can be represented as shown in equation 2 below:
wherein t=1/f SW I.e. the switching period of the oscillator circuit 104. Peak-to-average current sensing error can be expressed as 1/2T (1-D) dv/dt, where d=v O /V IN . Because dVs/dt=vo R i /L＝const(V IN ) So that only the term proportional to D affects dV O /dV IN . Thus, the current control command is shifted by 1/2T (V O /V IN ) dVs/dt eliminates the pair V IN Is dependent on the (c) of the (c).
Will feed forward voltage V FF Shifting any constant voltage also produces the same feed forward characteristics. By an interval time delay period t DEL Sampling the current sense voltage twice may reduce or eliminate R i Dependence of the/L ratio. Voltage difference Δv between two sampled current sensing voltages S Is R i A measure of/L which allows the use of a feed-forward voltage V which is not affected by component tolerances FF 。
According to an exemplary embodiment, from a circuit implementation point of view, V is obtained under all operating conditions FF <0 may be more convenient. Thus, the voltage may be subtracted from the output voltage of the multiplier-divider circuit 118Difference DeltaV S Without any substantial sacrifice in performance which affects the feedforward voltage V FF As represented by the following equation 3.
The embodiment of equation 3 is shown in fig. 4, which illustrates an EPCMC synchronous buck converter device according to an example embodiment, including a controller 400A with a feed forward circuit 400C. In the feedforward circuit 400C, the voltage difference Δv supplied to the input a of the multiplier-divider circuit 118 is subtracted from the output voltage of the multiplier-divider circuit 118 by the feedforward differential circuit 118A S . The voltage difference DeltaV between the output voltage of the multiplier-divider circuit 118 and the output voltage of the feedforward differential circuit 118A S The difference between them is input to a gain stage 119 where it is amplified and provided to a summing circuit 119A for use with a current control command voltage V CONT Summing to generate a threshold voltage for the current sense comparator 105.
Fig. 5 illustrates the principle of operation of the exemplary EPCMC synchronous buck converter device of fig. 4. In fig. 5, waveform 202 represents inductor current I L Is multiplied by the rising slope of the current sensing element 123 by the gain R i While high side switch 108 is on and low side switch 109 is off. Waveform 203 is the current sense voltage output by current sense element 123 when low side switch 109 is on and high side switch 108 is off. Waveform 201 represents the emulated ramp signal output by summing circuit 105A and provided to the non-inverting input of current sense comparator 105. Voltage level 206 is current control command voltage V CONT . The voltage level 207 is the resulting threshold voltage generated by the summing circuit 119A fed to the inverting input of the current sense comparator 105, which is configured as the current control command voltage V CONT And the feedforward voltage V given by equation (3) FF A kind of electronic device. Signal 204 is shown at switching frequency f SW The clock pulse of the oscillator circuit 104 generated below. Voltage difference DeltaV S Is generated to be within a time delay period t DEL Previously and subsequently acquired current sense signal 203.
Time delay period t DEL Can be accurately generated as a fraction 1/n of the switching period T. Fig. 6 shows an EPCMC synchronous buck converter device with EPCM controller 600A, according to an exemplary embodiment, wherein the oscillator circuit 104 is at a frequency n×f SW Operation, where n is an integer that may be much greater than 1. In the EPCMC synchronous buck converter device of FIG. 6, delay circuit 117 is implemented as a frequency divider 120 configured to generate taps f substantially coincident with the (n-1) th and nth clocks, respectively, of oscillator circuit 104 SW(n-1) And f SW(n) . Thus, the feedforward voltage V FF Can be obtained by the following
Formula 4:
fig. 7 illustrates the operation of the EPCMC synchronous buck converter device of fig. 6. In fig. 7, waveform 202 represents inductor current I L Is multiplied by the rising slope of the current sensing element 123 by the gain R i While high side switch 108 is on and low side switch 109 is off. Waveform 203 is the current sense voltage generated by current sense element 123 when low side switch 109 is on and high side switch 108 is off. Waveform 201 is a simulated ramp signal output by summing circuit 105A and provided to the non-inverting input of current sense comparator 105. Voltage level 206 is current control command voltage V CONT . The voltage level 207 is the resulting threshold voltage fed to the inverting input of the current sense comparator 105, which is configured as the current control command voltage V CONT And the feedforward voltage V given by equation (4) FF A kind of electronic device. Signal 205 is represented at a frequency n x f SW The clock pulse of the oscillator circuit 104 generated below. Signals 208 and 209 represent tap f of divider 120, respectively SW(n-1) And f SW(n) 。
Fig. 8 depicts an EPCM synchronous buck converter device according to an example embodiment, including EPCM controller 800A and synchronous buck converter 100B from fig. 1. The EPCM controller 800A includes an inductor-based 110Inductor current I in (a) L A current sensing element 123 that outputs a current sensing voltage. The oscillator circuit 104 outputs a signal that causes the second sample-and-hold circuit 116 to delay for a period of time t before the low-side switch 109 turns off DEL The first current sense voltage generated by the current sense element 123 is sampled and held, and the first sampled current sense voltage is output. The delay circuit 117 also receives the signal output by the oscillator circuit 104, but delays the signal output by the oscillator circuit 104 to the first sample hold circuit 115. In response to the delay circuit 117 passing the signal output by the oscillator circuit 104 to the first sample-and-hold circuit 115, the first sample-and-hold circuit 115 samples and holds the second current sense voltage generated by the current sense element 123 at a second time during the on period from the first time delay but still at the low side switch 109 and outputs the second sampled current sense voltage.
The EPCM controller 800A includes a feed-forward circuit 900 that receives a first sampled-current sensing voltage output by the second sample-and-hold circuit 116 and a second sampled-current sensing voltage output by the first sample-and-hold circuit 115, and is based on a voltage difference Δv representing a difference between the first current sensing voltage and the second current sensing voltage S To generate the feedforward voltage V FF . In this exemplary embodiment, the first current sense voltage is a first sampled current sense voltage and the second current sense voltage is a second sampled current sense voltage. The controller 800A also includes a Pulse Width Modulation (PWM) latch 901 that receives a feed forward voltage V FF And based on the feedforward voltage V FF The high-side switch 108 and the low-side switch 109 are alternately turned on and off, respectively. Fig. 9 illustrates the principle of operation of the exemplary EPCMC synchronous buck converter device of fig. 8. In fig. 9, waveform 202 represents inductor current I L Is multiplied by the rising slope of the current sensing element 123 by the gain R i While high side switch 108 is on and low side switch 109 is off. Waveform 203 is the current sense voltage output by current sense element 123 when low side switch 109 is on and high side switch 108 is off. Signal 204 is shown at switching frequency f SW Down generationIs provided for the clock pulses of the oscillator circuit 104. Voltage difference DeltaV S Is generated to be within a time delay period t DEL Before (V) S&H1 ) And thereafter (V) S&H2 ) The difference of the current sense signal 203 is obtained.
While the exemplary embodiments discussed above have been described in the context of automotive or industrial applications, the exemplary embodiments are not limited to such applications and may be applicable to many other applications.
Many different embodiments have been disclosed herein in connection with the above description and the accompanying drawings. It will be understood that each combination and sub-combination of these embodiments described and shown literally will be unduly repeated. Thus, all embodiments can be combined in any manner and/or combination, and the specification (including the drawings) should be interpreted as constituting a complete written description of all combinations and subcombinations of the embodiments described herein, as well as of the manner and process of making and using them, and should support requirements for any such combination or subcombination.
It will be appreciated by persons skilled in the art that the embodiments described herein are not limited to what has been particularly shown and described hereinabove. Furthermore, unless mentioned to the contrary above, it should be noted that all drawings are not to scale. Many modifications and variations are possible in light of the above teaching.
Claims (21)
1. An Emulated Peak Current Mode Control (EPCMC) synchronous buck converter device, comprising:
a converter configured to receive an input voltage and generate an output voltage, the converter comprising an inductor, a high side switch, and a low side switch, wherein the high side switch and the low side switch are coupled to the inductor and configured to control an inductor current through the inductor; and
an Emulated Peak Current Mode (EPCM) controller, the EPCM controller comprising:
a Pulse Width Modulation (PWM) latch configured to alternately turn on and off the high side switch and the low side switch, respectively;
a current sensing element configured to output a current sensing voltage based on the inductor current through the inductor; and
a feed-forward circuit configured to generate a feed-forward voltage;
wherein the current sensing element is configured to output a first current sensing voltage at a first time when the low side switch is on, and to output a second current sensing voltage at a second time when the low side switch is on, the second time being delayed from the first time;
wherein the feed-forward circuit is configured to generate the feed-forward voltage based on a voltage difference representing a difference between the first current sense voltage and the second current sense voltage; and is also provided with
Wherein the PWM latch is configured to alternately turn on and off the high side switch and the low side switch, respectively, based on the feedforward voltage.
2. The EPCMC synchronous buck converter device of claim 1, wherein the EPCM controller further comprises:
a ramp voltage generator configured to generate a ramp voltage;
a current control command voltage source configured to generate a current control command voltage; and
a current sense comparator that compares a sum of the ramp voltage and the second current sense voltage with a sum of the feedforward voltage and the current control command voltage, and outputs a control signal to the PWM latch based on the comparison;
wherein the PWM latch is configured to alternately turn on and off the high-side switch and the low-side switch based on the control signal output by the current sense comparator.
3. The EPCMC synchronous buck converter device of claim 2, wherein the EPCM controller further comprises:
a multiplier-divider circuit configured to output a signal representative of the voltage difference multiplied by a ratio of the output voltage to the input voltage; and
a gain stage configured to amplify the output of the multiplier-divider circuit to generate the feedforward voltage.
4. The EPCMC synchronous buck converter apparatus of claim 2 wherein the controller further comprises:
a multiplier-divider circuit configured to output a signal representative of the voltage difference multiplied by a ratio of the output voltage to the input voltage;
a feed-forward differential circuit configured to output a difference between the voltage difference and the output of the multiplier-divider circuit; and
a gain stage configured to amplify the difference between the voltage difference and the output of the multiplier-divider circuit to generate the feedforward voltage.
5. The EPCMC synchronous buck converter device of claim 1, wherein the EPCM controller further comprises:
a multiplier-divider circuit configured to output a signal representative of the voltage difference multiplied by a ratio of the output voltage to the input voltage; and
a gain stage configured to amplify the output of the multiplier-divider circuit to generate the feedforward voltage.
6. The EPCMC synchronous buck converter device of claim 1, wherein the EPCM controller further comprises:
a first sample-and-hold circuit configured to sample the first current sense voltage at the first time and output a first sampled current sense voltage;
a second sample-and-hold circuit configured to sample the second current sense voltage at the second time and output a second sampled current sense voltage;
a current sense differential circuit configured to output the voltage difference as a difference between the first sampled current sense voltage and the second sampled current sense voltage; and
a delay circuit configured to delay the sampling of the second current sense voltage by a time delay period after the sampling of the first current sense voltage.
7. The EPCMC synchronous buck converter device of claim 6, further comprising:
an oscillator circuit configured to generate a series of clock pulses;
wherein the delay circuit comprises a frequency divider configured to receive the series of clock pulses and to generate a first frequency tap signal corresponding to a first clock pulse of the series of clock pulses and a second frequency tap signal corresponding to a second clock pulse of the series of clock pulses;
wherein the first sample-and-hold circuit is configured to sample the first current sense voltage in response to the first frequency tap signal; and is also provided with
Wherein the second sample-and-hold circuit is configured to sample the second current sense voltage in response to the second frequency tap signal.
8. An Emulated Peak Current Mode (EPCM) controller for controlling a synchronous buck converter configured to receive an input voltage and generate an output voltage, and having an inductor, a high side switch, and a low side switch, the EPCM controller comprising: a Pulse Width Modulation (PWM) latch configured to alternately turn on and off the high side switch and the low side switch, respectively;
a current sensing element configured to output a current sensing voltage based on an inductor current through the inductor; and
a feed-forward circuit configured to generate a feed-forward voltage;
wherein the current sensing element is configured to output a first current sensing voltage at a first time when the low side switch is on, and to output a second current sensing voltage at a second time when the low side switch is on, the second time being delayed from the first time;
wherein the feed-forward circuit is configured to generate the feed-forward voltage based on a voltage difference representing a difference between the first current sense voltage and the second current sense voltage; and is also provided with
Wherein the PWM latch is configured to alternately turn on and off the high side switch and the low side switch based on the feedforward voltage.
9. The EPCM controller of claim 8 further comprising:
a ramp voltage generator configured to generate a ramp voltage;
a current control command voltage source configured to generate a current control command voltage; and
a current sense comparator that compares a sum of the ramp voltage and the second current sense voltage with a sum of the feedforward voltage and the current control command voltage, and outputs a control signal to the PWM latch based on the comparison;
wherein the PWM latch is configured to turn on and off the high-side switch and the low-side switch based on the control signal output by the current sense comparator.
10. The EPCM controller of claim 9 further comprising:
a multiplier-divider circuit configured to output a signal representative of the voltage difference multiplied by a ratio of the output voltage to the input voltage; and
a gain stage configured to amplify the output of the multiplier-divider circuit to generate the feedforward voltage.
11. The EPCM controller of claim 9 further comprising:
a multiplier-divider circuit configured to output a signal representative of the voltage difference multiplied by a ratio of the output voltage to the input voltage;
a feed-forward differential circuit configured to output a difference between the voltage difference and the output of the multiplier-divider circuit; and
a gain stage configured to amplify the difference between the voltage difference and the output of the multiplier-divider circuit to generate the feedforward voltage.
12. The EPCM controller of claim 8 further comprising:
a multiplier-divider circuit configured to output a signal representative of the voltage difference multiplied by a ratio of the output voltage to the input voltage; and
a gain stage configured to amplify the output of the multiplier-divider circuit to generate the feedforward voltage.
13. The EPCM controller of claim 8 further comprising:
a first sample-and-hold circuit configured to sample the first current sense voltage at the first time and output a first sampled current sense voltage;
a second sample-and-hold circuit configured to sample the second current sense voltage at the second time and output a second sampled current sense voltage;
a current sense differential circuit configured to output the voltage difference as a difference between the first sampled current sense voltage and the second sampled current sense voltage; and
a delay circuit configured to delay the sampling of the second current sense voltage by a time delay period after the sampling of the first current sense voltage.
14. The EPCM controller of claim 13 further comprising:
an oscillator circuit configured to generate a series of clock pulses;
wherein the delay circuit comprises a frequency divider configured to receive the series of clock pulses and to generate a first frequency tap signal corresponding to a first clock pulse of the series of clock pulses and a second frequency tap signal corresponding to a second clock pulse of the series of clock pulses;
wherein the first sample-and-hold circuit is configured to sample the first current sense voltage in response to the first frequency tap signal; and is also provided with
Wherein the second sample-and-hold circuit is configured to sample the second current sense voltage in response to the second frequency tap signal.
15. A simulated peak current mode control (EPCMC) method of controlling a synchronous buck converter configured to receive an input voltage and generate an output voltage, and having an inductor, a high side switch, and a low side switch, the EPCMC method comprising:
generating a Pulse Width Modulation (PWM) signal to alternately turn on and off the high side switch and the low side switch;
outputting a first current sense voltage based on an inductor current through the inductor at a first time when the low side switch is on;
outputting a second current sense voltage based on an inductor current through the inductor at a second time when the low-side switch is on, the second time delayed from the first time; and
a feed-forward voltage is generated based on a voltage difference representing a difference between the first current sense voltage and the second current sense voltage,
wherein the PWM signal is generated based on the feed-forward voltage.
16. The EPCMC method of claim 15 further comprising:
generating a ramp voltage;
generating a current control command voltage;
comparing a sum of the ramp voltage and the second current sensing voltage with a sum of the feedforward voltage and the current control command voltage; and
outputting a control signal based on the comparison;
wherein the PWM signal is generated based on the control signal.
17. The EPCMC method of claim 16 further comprising:
multiplying the voltage difference by a ratio of the output voltage to the input voltage; and
amplifying the multiplied result to generate the feedforward voltage.
18. The EPCMC method of claim 16 further comprising:
multiplying the voltage difference by a ratio of the output voltage to the input voltage;
subtracting the voltage difference from the multiplied result; and
amplifying the result of the subtraction to generate the feedforward voltage.
19. The EPCMC method of claim 15 further comprising:
multiplying the voltage difference by a ratio of the output voltage to the input voltage; and
amplifying the multiplied result to generate the feedforward voltage.
20. The EPCMC method of claim 15 further comprising:
sampling the first current sense voltage at the first time and outputting a first sampled current sense voltage; and
sampling the second current sense voltage at the second time and outputting a second sampled current sense voltage;
outputting the voltage difference as a difference between the first sampled current sense voltage and the second sampled current sense voltage,
wherein the sampling of the second current sense voltage is delayed by a time delay period after the sampling of the first current sense voltage.
21. The EPCMC method of claim 20 further comprising:
generating a series of clock pulses;
generating a first frequency tap signal corresponding to a first clock pulse in the series of clock pulses; and
generating a second frequency tap signal corresponding to a second clock pulse of the series of clock pulses,
wherein the sampling the first current sense voltage comprises sampling the first current sense voltage in response to the first frequency tap signal; and is also provided with
Wherein the sampling the second current sense voltage includes sampling the second current sense voltage in response to the second frequency tap signal.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US63/129,867 | 2020-12-23 | ||
| US17/198,911 US11444535B2 (en) | 2020-12-23 | 2021-03-11 | DC-DC converter with improved line transient rejection |
| US17/198,911 | 2021-03-11 | ||
| PCT/US2021/030152 WO2022139868A1 (en) | 2020-12-23 | 2021-04-30 | Dc-dc converter with improved line transient rejection |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116648843A true CN116648843A (en) | 2023-08-25 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202180086271.1A Pending CN116648843A (en) | 2020-12-23 | 2021-04-30 | DC-DC Converter with Improved Line Transient Suppression |
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| Country | Link |
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| CN (1) | CN116648843A (en) |
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