CN116648780A - Chip packaging structure, preparation method thereof and terminal equipment - Google Patents
Chip packaging structure, preparation method thereof and terminal equipment Download PDFInfo
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- CN116648780A CN116648780A CN202180086852.5A CN202180086852A CN116648780A CN 116648780 A CN116648780 A CN 116648780A CN 202180086852 A CN202180086852 A CN 202180086852A CN 116648780 A CN116648780 A CN 116648780A
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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Abstract
The application discloses a chip packaging structure, a preparation method thereof and terminal equipment. The chip packaging structure comprises a first chip, a second chip, a first rewiring layer, a second rewiring layer and a vertical silicon bridge; the first chip and the vertical silicon bridge are arranged on the first redistribution layer side by side, the second redistribution layer is arranged on the vertical silicon bridge and the first chip, and the second chip is arranged on the second redistribution layer; the first chip is coupled with the first rewiring layer, and the second chip is coupled with the second rewiring layer; the vertical silicon bridge is provided with silicon through holes, a large number of silicon through holes are prepared on the passive wafer by the vertical silicon bridge to finish high-density wiring, the process is mature and stable, the reliability is high, and the risks of disconnection and short circuit yield are avoided. The second chip is vertically interconnected with the first chip sequentially through the second redistribution layer, the silicon through hole and the first redistribution layer, and the size of the silicon through hole in the vertical silicon bridge can be matched with the physical channel size of the second chip to realize high-density signal interconnection.
Description
The present application relates to the field of chip packaging technologies, and in particular, to a chip packaging structure, a method for manufacturing the same, and a terminal device.
With the rapid increase of popularity of electronic devices and the vigorous development of the electronic device market, electronic products are increasingly required to be miniaturized and thinned while having high performance, multiple functions, high reliability and convenience. Such demands place demands on the packaging of chips for better, lighter, thinner, higher packing density, better electrical and thermal performance, higher reliability, and higher cost performance.
To meet the ever-increasing electronic device development requirements, different packaging forms have been proposed. The three-dimensional integrated circuit (3-Dimentional Integrated Circuit,3D IC) packaging technology is to vertically integrate a plurality of chips in three-dimensional space by using the stacking of different chips, so as to cope with the limitation of the semiconductor manufacturing process in the physical limits of electronics and materials.
Typically, the chip stack requires wire bonding (wirebond) or through silicon vias (through silicon via, TSV), which is commonly used in multi-layer flash memory (NAND flash), and TSVs which are commonly used in high bandwidth memory (high bandwidth memory, HBM) and silicon interposer (silicon interposer) and the like. Compared with wirebond, the TSV has smaller parasitic capacitance, inductance and resistance and short power supply path, has better electrical performance, higher interconnection bandwidth and wider application.
Generally, if chip stacking by TSV is required, TSV preparation on the bottom chip (bottom die) is required. Referring to fig. 1a, when a passive chip is used in the bottom die 01, i.e., the bottom die has no function, only mechanical processes and signal extraction are provided, for example, the method is applied to wafer level packaging (chip on wafer on substrate, COWOS), and the TSV of the bottom die is mainly used for horizontal interconnection between upper chips 02 (top die), and the horizontal interconnection cannot meet the severe requirement of part of products on area. Referring to fig. 1b, when an active chip is used by the bottom die, i.e., the bottom die has a certain function, for example, the bottom die is applied to a high bandwidth memory (high bandwidth memory, HBM), the structure of the bottom die is a memory (memory), TSVs are formed in each layer of chip, the layers of chips are interconnected through micro bumps (uBump), the area occupied by the TSVs prepared in the active chip is not only occupied, but also the difficulty in preparing the TSVs is high, the requirements on the avoidance area (KOZ) of the TSVs in each generation of technology are different, the long-time verification is required, the risk is high, the cost is high, and the bottom die is not suitable for advanced logic manufacturing.
Disclosure of Invention
The embodiment of the application provides a chip packaging structure, a preparation method thereof and terminal equipment, which are used for reducing the process complexity, the technical difficulty and the packaging cost.
In a first aspect, the present application provides a chip package structure, including: the semiconductor device comprises a first chip, a second chip, a first rewiring layer, a second rewiring layer and a vertical silicon bridge; the first chip and the vertical silicon bridge are arranged on the first redistribution layer side by side, the second redistribution layer is arranged on the vertical silicon bridge and the first chip, and the second chip is arranged on the second redistribution layer; the first chip is coupled with the first rewiring layer, and the second chip is coupled with the second rewiring layer; the vertical silicon bridge is provided with silicon through holes which are respectively coupled with the first rewiring layer and the second rewiring layer, so that the second chip is vertically interconnected with the first chip through the second rewiring layer, the silicon through holes and the first rewiring layer in sequence.
According to the chip packaging structure provided by the embodiment of the application, the independent vertical silicon bridge and the first chip are placed side by side, the second chip is vertically stacked above the vertical silicon bridge and the first chip, signals between the first chip and the second chip are conducted in the vertical direction through the vertical silicon bridge, and the signals are conducted in the horizontal direction through the first rewiring layer and the second rewiring layer. Vertical silicon bridges produce through silicon vias on passive wafers (wafer), which are well-established and stable in process and high in reliability, without the risk of open/short yield. The size of the silicon through holes in the vertical silicon bridge can be less than 100um, and the size of 20um or even smaller can be realized very easily so as to match the physical channel size of the second chip and realize high-density signal interconnection. The vertical silicon bridge completes high-density wiring by etching a large number of silicon through holes on the silicon substrate, so that stacked packaging of the second chip and the first chip is realized, and the vertical silicon bridge, the first chip and the second chip jointly form a packaging body.
In one possible implementation manner of the present application, the chip packaging structure may further include a vertical interconnection coupled between the first redistribution layer and the second redistribution layer, where the vertical interconnection and the vertical silicon bridge are disposed independently of each other, and the vertical interconnection may implement low-density vertical interconnection between the first redistribution layer and the second redistribution layer.
In one possible implementation of the present application, the chip package structure may further include a third chip disposed on the second redistribution layer side by side with the second chip, and the third chip is coupled to the second redistribution layer. Through setting up first chip and perpendicular silicon bridge side by side at first layer, second chip and third chip set up side by side at the second floor, realize the two-layer vertical stack of chip, but the integrated level is high, and occupation area after vertical stack is little, and is with low costs, is the integrated important technology of high density system level package (system in a package, SIP) in future.
In one possible implementation manner of the present application, the chip packaging structure may further include a first insulating material and a second insulating material; the first insulating material wraps the first chip and the vertical silicon bridge to form a plastic package structure, and the second insulating material wraps the second chip to form the plastic package structure. When the third chip is present, the second insulating material also wraps the third chip to form a plastic package structure.
In one possible implementation of the present application, the chip package structure may further include a first solder ball (solder ball) disposed on a side surface of the first redistribution layer facing away from the first chip and the vertical silicon bridge, and the first solder ball is coupled to the first redistribution layer. The first solder balls are used for realizing interconnection between the first chip and the second chip and the outside (such as a PCB (printed Circuit Board), other chips and the like), so that the chip packaging structure can be directly interconnected with the outside through the first solder balls, signals and power supply can be directly output from the first solder balls, the performance of signal integrity and power integrity (signal integrity power integrity, SIPI) is optimal, a substrate is not needed, the packaging thickness of the chip packaging structure is reduced, and meanwhile, the heat dissipation performance is improved.
In one possible implementation of the present application, a third redistribution layer coupled to the through silicon via is disposed on one side of the vertical silicon bridge, and a second solder ball coupled to the third redistribution layer; the other side of the vertical silicon bridge is provided with a first micro-bump coupled with the silicon through hole. Vertical silicon bridges produce through silicon vias on passive wafers (wafer), which are well-established and stable in process and high in reliability, without the risk of open/short yield. The size of the silicon through holes in the vertical silicon bridge can be less than 100um, so that high-density signal interconnection is realized. The third wiring layer arranged in the vertical silicon bridge contains metal wiring, so that wiring functions can be enriched.
In one possible implementation of the application, the chip and the redistribution layer may be fixedly connected by soldering, and the vertical silicon bridge may be disposed face down. Specifically, the active surface of the first chip faces the first rewiring layer, and a third solder ball welded with the first rewiring layer is arranged on one side of the active surface of the first chip; the active surface of the second chip faces the second redistribution layer, and a fourth solder ball welded with the second redistribution layer is arranged on one side of the active surface of the second chip; the vertical silicon bridge is soldered with the first redistribution layer through the second solder ball and coupled with the second redistribution layer through the first micro bump.
In one possible implementation of the present application, the chip may be fixed first, and then the redistribution layer may be directly fabricated on the upper surface of the chip to achieve connection, and the vertical silicon bridge may be disposed face up. Specifically, the active surface of the first chip faces the first rewiring layer, and the first chip is provided with a second micro-bump coupled with the first rewiring layer at one side of the active surface; the active surface of the second chip faces the second redistribution layer, and a third micro-bump coupled with the second redistribution layer is arranged on one side of the active surface of the second chip; the vertical silicon bridge is soldered with the second redistribution layer through the second solder ball and coupled with the first redistribution layer through the first micro bump.
In one possible implementation of the present application, the second chip may be fixed first, and then the second redistribution layer may be fabricated on the active surface side of the second chip, so that a side of the second chip facing away from the second redistribution layer may have a second connection film (DAF).
In one possible implementation of the present application, after the second redistribution layer is prepared, the first chip may be fixed to a surface of the second redistribution layer facing the first chip through the first connection film, so as to fabricate the first redistribution layer on the active surface side of the first chip.
In a second aspect, the present application provides a method for manufacturing a chip package structure, including: firstly, forming a vertical silicon bridge, wherein the vertical silicon bridge is provided with a silicon through hole, one side of the vertical silicon bridge is provided with a third wiring layer coupled with the silicon through hole, and a second solder ball coupled with the third wiring layer, and the other side of the vertical silicon bridge is provided with a first micro-bump coupled with the silicon through hole; then forming a first rewiring layer on the first carrier plate; then welding the first chip on the first rewiring layer through the third solder ball of the first chip, and welding the vertical silicon bridge through the second solder ball of the vertical silicon bridge; then adopting a first insulating material to mold the first chip and the vertical silicon bridge, and exposing a first micro bump of the vertical silicon bridge; then forming a second redistribution layer coupled to the first microbump of the vertical silicon bridge; then welding the second chip on the second redistribution layer through the fourth solder ball of the second chip; then adopting a second insulating material to plastic package a second chip; and forming a first solder ball on one side of the first rewiring layer after removing the first carrier plate.
In one possible implementation of the present application, after forming the first redistribution layer and before molding the first chip and the vertical silicon bridge with the first insulating material, the method may further include: vertical interconnects are formed on the first redistribution layer.
In a third aspect, the present application provides another method for manufacturing a chip package structure, including: firstly, forming a vertical silicon bridge, wherein the vertical silicon bridge is provided with a silicon through hole, one side of the vertical silicon bridge is provided with a third wiring layer coupled with the silicon through hole, and a second solder ball coupled with the third wiring layer, and the other side of the vertical silicon bridge is provided with a first micro-bump coupled with the silicon through hole; then fixing a second chip on the first carrier plate through a second connecting film, wherein a third micro-bump of the second chip is positioned at one side away from the first carrier plate; then, the second chip is encapsulated by adopting a second insulating material, and a third micro-bump of the second chip is exposed; forming a second redistribution layer coupled to the third microbump of the second chip; then fixing a first chip on the second redistribution layer through a first connection film, and welding a vertical silicon bridge through a second solder ball of the vertical silicon bridge, wherein a second micro-bump of the first chip is positioned at one side far away from the first carrier plate; then adopting a first insulating material to mold the first chip and the vertical silicon bridge, and exposing the second micro-bump of the first chip and the first micro-bump of the vertical silicon bridge; forming a first rewiring layer coupled with the second micro-bump of the first chip and the first micro-bump of the vertical silicon bridge; and forming a first solder ball on the first rewiring layer and removing the first carrier plate.
In one possible implementation of the present application, after forming the second redistribution layer and before molding the first chip and the vertical silicon bridge with the first insulating material, the method may further include: vertical interconnects are formed on the second redistribution layer.
In a fourth aspect, the present application further provides a terminal device, where the terminal device includes a circuit board and a chip package structure provided by each implementation manner of the first aspect of the present application and disposed on the circuit board.
FIG. 1a is a schematic cross-sectional view of a chip stacking structure according to the prior art;
FIG. 1b is a schematic cross-sectional view of another chip stacking structure according to the prior art;
FIG. 2 is a schematic cross-sectional view of a chip package structure according to an embodiment of the application;
FIG. 3 is a schematic cross-sectional view of a vertical silicon bridge in a chip package structure according to an embodiment of the present application;
FIG. 4 is a schematic cross-sectional view illustrating a process of fabricating a vertical silicon bridge in a chip package structure according to an embodiment of the present application;
FIG. 5 is a schematic cross-sectional view of a chip package structure according to another embodiment of the present application;
FIG. 6 is a schematic flow chart of a method for manufacturing a chip package structure according to an embodiment of the present application;
FIG. 7 is a schematic cross-sectional view illustrating a process for manufacturing a chip package according to an embodiment of the present application;
FIG. 8 is a schematic cross-sectional view of a chip package structure according to another embodiment of the present application;
fig. 9 is a flowchart illustrating a method for manufacturing a chip package structure according to another embodiment of the present application;
fig. 10 is a schematic cross-sectional structure of a process for manufacturing a chip package structure according to another embodiment of the application.
Reference numerals:
01-an underlying chip; 02-upper chip; 11-a first chip; 12-a second chip; 13-a third chip; 21-a first rewiring layer; 22-a second redistribution layer; 30-vertical silicon bridges; 31-through silicon vias; 32-first microbumps; 33-a third rewiring layer; 34-second solder balls; 40-vertical interconnects; 60-first solder balls; 51-a first insulating material; 52-a second insulating material; 71-a first connection film; 72-a second tie film; 100-a first carrier plate; 200-a second carrier plate; 111-second microbumps; 121-third microbumps; 112-third solder balls; 122-fourth solder balls; 21 a-a dielectric layer; 21 b-a conductive layer; 301-silicon-based; 321-an insulating layer; 322-a protective layer; 323-oxide layer; s-active surface.
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings.
The terminology used in the following examples is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the specification of the application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include, for example, "one or more" such forms of expression, unless the context clearly indicates to the contrary.
Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.
In addition, the same reference numerals in the drawings denote the same or similar structures, and thus a repetitive description thereof will be omitted. The words expressing the positions and directions described in the present application are described by taking the drawings as an example, but can be changed according to the needs, and all the changes are included in the protection scope of the present application. The drawings of the present application are merely schematic representations of relative positional relationships and are not intended to represent true proportions.
The chip packaging structure provided by the embodiment of the application can be applied to various terminal devices, such as smart phones, smart televisions, smart television set-top boxes, personal computers (personal computer, PCs), wearable devices, smart broadband and other terminal devices. It should be noted that the chip package structure proposed by the embodiments of the present application is intended to include, but not be limited to, application in these and any other suitable types of terminal devices. The chip packaging structure, the preparation method and the terminal equipment provided by the application are described in detail below with reference to the accompanying drawings.
Fig. 2 schematically illustrates a cross-sectional structure of a chip package structure according to an embodiment of the present application. In one embodiment of the present application with reference to fig. 2, a chip package structure may include: a first chip 11, a second chip 12, a first rewiring layer 21, a second rewiring layer 22, and a vertical silicon bridge 30; wherein the first chip 11 and the vertical silicon bridge 30 are arranged side by side on the first redistribution layer 21, the second redistribution layer 22 is arranged on the vertical silicon bridge 30 and the first chip 11, and the second chip 12 is arranged on the second redistribution layer 22; the first chip 11 is coupled with the first redistribution layer 21, and the second chip 12 is coupled with the second redistribution layer 22; the vertical silicon bridge 30 has a through silicon via 31, and the through silicon via 31 is coupled to the first redistribution layer 21 and the second redistribution layer 22, respectively, so that the second chip 12 is vertically interconnected with the first chip 11 through the second redistribution layer 22, the through silicon via 31, and the first redistribution layer 21 in sequence. Note that, the vertical interconnection referred to in the present application means that electrical communication is achieved in the vertical direction (thickness direction of the chip).
In the chip packaging structure provided by the embodiment of the application, by arranging the independent vertical silicon bridge 30 and the first chip 11 side by side, and vertically stacking the second chip 12 above the vertical silicon bridge 30 and the first chip 11, signals between the first chip 11 and the second chip 12 realize conduction in the vertical direction through the vertical silicon bridge 30, and realize conduction in the horizontal direction through the first redistribution layer 21 and the second redistribution layer 22. The vertical silicon bridge 30 prepares through silicon vias 31 on a passive wafer (wafer), which is well-established and stable in process, high in reliability, and free from the risk of open/short yield. The size of the through silicon vias 31 in the vertical silicon bridge 30 can be 100um or less, and can be very easily realized in a size of 20um or less to match the physical channel size of the second chip 12 to realize high-density signal interconnection. The vertical silicon bridge 30 provided by the application completes high-density wiring by etching a large number of through silicon holes 31 on silicon substrate, thereby realizing the stack package of the second chip 12 and the first chip 11, and the vertical silicon bridge 30, the first chip 11 and the second chip 12 together form a package body.
With continued reference to fig. 2, in this embodiment of the present application, a vertical interconnect 40 coupled between the first and second redistribution layers 21 and 22 may be further included, the vertical interconnect 40 and the vertical silicon bridge 30 being disposed independently of each other, the vertical interconnect 40 may enable a low density vertical interconnection between the first and second redistribution layers 21 and 22. In particular implementations, the vertical interconnects 40 may be insulating layer vias (through insulator via, TIVs) filled with conductive material such as copper pillars to effect signal transmission. The Aspect Ratio (AR) of the vertical interconnect 40 is high, the difficulty of the fabrication process is relatively high, the feature size of the vertical interconnect 40 is large, the interconnect density is low, and the density of the vertical interconnect 40 is lower than the density of the through silicon vias 31 in the vertical silicon bridge 30, so that the vertical interconnect 40 can be used for the vertical interconnect between the chips with low bandwidth requirements.
With continued reference to fig. 2, in this embodiment of the application, a third chip 13 may be further included, disposed on the second redistribution layer 22 side-by-side with the second chip 12, the third chip 13 being coupled to the second redistribution layer 22. The third chip 13 may be vertically interconnected with the first chip 11 through the vertical silicon bridge 30, or may be vertically interconnected with the first chip 11 through the vertical interconnection 40, depending on the desired interconnection density of the third chip 13, which is not limited herein. By arranging the first chip 11 and the vertical silicon bridge 30 side by side on the first layer, and arranging the second chip 12 and the third chip 13 side by side on the second layer, two layers of chips are vertically stacked, so that the integration level is high, the occupied area after vertical stacking is small, the cost is low, and the method is an important technology for future integration of high-density system-in-package (system in a package, SIP).
The first chip 11, the second chip 12 and the third chip 13 mentioned in the present application are typically die (die), which are dies before the chip is unpackaged, each die being an unpackaged chip with independent functions, which may be composed of one or more circuits. Specific die include, but are not limited to, application specific integrated circuits (application specific integrated circuit, ASIC), memory die, analog die, and the like. The die is typically composed of a silicon substrate and a circuit layer disposed on the silicon substrate, in which semiconductor devices such as transistors and various functional circuits are typically formed. The surface of the die on which the circuit layer is located is generally referred to as the active surface, and the surface of the die on which the silicon substrate is located is referred to as the passive surface. In this embodiment of the application, the first chip 11 may be, for example, a sensor-on-one processor (sensor edge processor, SEP), and the second chip 12 may be, for exampleMay be a bandwidth I/O standard memory (WIO), and the third chip 13 may be, for example, a power management unit (power management unit, PMU) and a passive device having a motherboard area of about 40mm 2 Left and right.
With continued reference to fig. 2, in this embodiment of the application, a first insulating material 51 and a second insulating material 52 may also be included; the first insulating material 51 wraps the first chip 11 and the vertical silicon bridge 30 to form a plastic package structure, and the second insulating material 52 wraps the second chip 12 to form a plastic package structure. When the third chip 13 is present, the second insulating material 52 also wraps the third chip 13 to form a plastic package structure. It should be noted that, in the present application, the first insulating material 51 wraps the first chip 11 and the vertical silicon bridge 30, and the first insulating material 51 wraps the side surface of the first chip 11 and the side surface of the vertical silicon bridge 30, and in some embodiments described below, the first insulating material 51 also covers the upper surface of the first chip 11, so that the first chip 11 and the vertical silicon bridge 30 are in a sealed state. Likewise, the second insulating material 52 wrapping the second chip 12 means that the second insulating material 52 wraps around the side surface of the second chip 12, and in some embodiments described below, the second insulating material 52 also covers the upper surface of the second chip 12, so that the second chip 12 is in a sealed state.
With continued reference to fig. 2, in this embodiment of the present application, a first solder ball 60 (solder ball) may be further included on a side surface of the first redistribution layer 21 facing away from the first chip 11 and the vertical silicon bridge 30, and the first solder ball 60 is coupled to the first redistribution layer 21. The first solder balls 60 are used to realize the interconnection between the first chip 11 and the second chip 12 and the outside (such as PCB, other chips, etc.), so that the chip package structure can directly interconnect with the outside through the first solder balls 60, signals and power can be directly output from the first solder balls 60, the performance of signal integrity and power integrity (signal integrity power integrity, SIPI) is optimal, and no substrate is required, thereby reducing the package thickness of the chip package structure and improving the heat dissipation performance.
In particular implementations, the first and second redistribution layers 21 and 22 as redistribution layers (redistribution layer, RDL) may also be referred to as redistribution layers. With continued reference to fig. 2, in this embodiment of the present application, the first redistribution layer 21 may be composed of a dielectric layer 21a and at least one conductive layer 21b, where the conductive layer 21b is provided with circuit wiring, and where the dielectric layer 21a is provided with dielectric perforations for connecting the circuit wiring on different layers. The material of the dielectric layer 21a is typically polyimide, and the material of the conductive layer 21b is typically metal. The number of layers of the conductive layer 21b included in the first re-wiring layer 21 is not limited in the present application, and may be designed according to actual requirements. Fig. 2 is only schematically illustrated by way of example in which the first redistribution layer 21 comprises a conductive layer 21 b. Similarly, the second redistribution layer 22 may be the same as the first redistribution layer 21, or may be composed of a dielectric layer and at least one conductive layer, and the internal structure of the second redistribution layer 22 may refer to the description of the first redistribution layer 21, which is not repeated herein.
Fig. 3 schematically illustrates a cross-sectional structure of a vertical silicon bridge according to an embodiment of the present application. Referring to fig. 3, in this embodiment of the present application, a specific structure of the vertical silicon bridge 30 may include: the silicon substrate 301 penetrates through a through silicon via 31 in the thickness direction of the silicon substrate 301, a metal layer is plated in the through silicon via 31 or a metal pillar such as a copper pillar (copper pillar) is filled in the through silicon via 31, and a first micro bump 32 is formed on one side protruding from the surface of the silicon substrate 301, a third wiring layer 33 is disposed on the other side of the silicon substrate 301 and coupled to the through silicon via 31, and a second solder ball 34 coupled to the third wiring layer 33.
The vertical silicon bridge 30 prepares through silicon vias 31 on a passive wafer (wafer), which is well-established and stable in process, high in reliability, and free from the risk of open/short yield. The size of the through silicon vias 31 in the vertical silicon bridge 30 can be less than 100um, and high-density signal interconnection is realized. The third wiring layer 33 provided in the vertical silicon bridge 30 contains metal wirings, and thus the wiring function can be enriched.
With continued reference to fig. 3, in this embodiment of the present application, deep trench capacitors (deep trench capacitor, DTC) may be integrated into the vertical silicon bridge 30 to improve the performance of the power integrity, and further, integrated voltage regulators (integrated voltage regular, IVR) and the like may be provided in the vertical silicon bridge 30.
Fig. 4 is a schematic structural diagram illustrating each manufacturing process in the method for manufacturing a vertical silicon bridge according to an embodiment of the present application. Referring to fig. 4, in this embodiment of the present application, a specific process for fabricating the vertical silicon bridge 30 may include the following steps:
1. a large number of through silicon vias 31 are fabricated on the silicon substrate 301, and first micro bumps 32 are fabricated on the surface of the silicon substrate 301, an insulating layer 321 is formed on the first micro bumps 32 by using silicon oxide or silicon nitride, a protective layer 322 is formed on the insulating layer 321 by using Polyimide (PI), and the protective layer 322 plays roles of increasing thickness and protecting.
2. An epoxy (epoxy) is used to add the first carrier 100 to one side of the protective layer 322.
3. The silicon substrate 301 is inverted 180 ° with the first carrier 100 located below.
4. The surface of the silicon substrate 301 is etched to expose the first micro bump 32 on the side of the through silicon via 31.
5. An oxide layer 323 is formed on the surface of the silicon substrate 301, and the oxide layer 323 encapsulates the exposed first micro bump 32.
6. The surface of the oxide layer 323 is polished by a chemical-mechanical polishing (CMP) process (chemical-mechanical polishing), exposing the surface of the first microbump 32 at the end of the through-silicon via 31.
7. A third wiring layer 33 and a second solder ball 34 are formed on the surface of the oxide layer 323.
8. The first carrier 100 is removed and the completed vertical silicon bridge 30 is inverted 180 ° with the second solder balls 34 underneath.
For convenience of the following description, a side of the vertical silicon bridge 30 having the third triple wiring layer 33 may be taken as an active surface of the vertical silicon bridge 30, and a side having the first micro bump 32 may be taken as a passive surface of the vertical silicon bridge 30. In connection with the different manufacturing processes of the chip package structure provided by the present application, the active surface of the vertical silicon bridge 30 may be disposed face up (face up) or face down (face down) in the chip package structure. Correspondingly, in combination with different manufacturing procedures of the chip packaging structure provided by the application, the rewiring layer and the chip can be fixedly connected in a welding mode, and also can be fixedly connected in a laminated film layer manufacturing mode, and the detailed description is carried out in combination with specific manufacturing procedures.
Fig. 5 schematically illustrates a specific structure of a chip package structure according to an embodiment of the present application. Referring to fig. 5, in one embodiment of the present application, the die and the redistribution layer may be fixedly connected by soldering, and the vertical silicon bridge 30 may be disposed face down. Specifically, the active surface S of the first chip 11 faces the first redistribution layer 21, and the first chip 11 is provided with third solder balls 112 soldered to the first redistribution layer 21 on the active surface S side; the active surface S of the second chip 12 faces the second redistribution layer 22, and the second chip 12 is provided with fourth solder balls 122 soldered to the second redistribution layer 22 on the active surface S side; the vertical silicon bridge 30 is soldered to the first redistribution layer 21 by the second solder ball 34 and coupled to the second redistribution layer 22 by the first micro bump 32.
Fig. 6 is a schematic flow chart illustrating a method for manufacturing a chip package structure according to an embodiment of the present application; fig. 7 schematically shows the structure of each preparation process in the preparation method of fig. 6. Referring to fig. 6 and 7, the preparation method mainly includes the steps of:
s101, referring to the steps shown in fig. 4, a vertical silicon bridge 30 is formed, the vertical silicon bridge 30 has a through silicon via 31, one side of the vertical silicon bridge 30 is provided with a third redistribution layer 33 coupled with the through silicon via 31, and a second solder ball 34 coupled with the third redistribution layer 33, and the other side of the vertical silicon bridge 30 is provided with a first microbump 32 coupled with the through silicon via 31.
S102, the first redistribution layer 21 is formed on the first carrier 100.
S103, the first chip 11 is soldered on the first redistribution layer 21 through the third solder ball 112 of the first chip 11, and the vertical silicon bridge 30 is soldered through the second solder ball 34 of the vertical silicon bridge 30. Specifically, the first chip 11 and the vertical silicon bridge 30 are both placed face down.
S104, the first chip 11 and the vertical silicon bridge 30 are encapsulated by the first insulating material 51, and the first micro bump 32 of the vertical silicon bridge 30 is exposed. Specifically, the first micro bump 32 exposed on the surface of the vertical silicon bridge 30 may be polished by CMP.
S105, forming a second redistribution layer 22 coupled to the first micro bump 32 of the vertical silicon bridge 30. Specifically, each film layer constituting the second redistribution layer 22 may be directly fabricated on the upper surfaces of the first chip 11 and the vertical silicon bridge 30 after plastic packaging.
S106, the second chip 12 is soldered on the second redistribution layer 22 through the fourth solder balls 122 of the second chip 12. Optionally, the third chip 13 may also be soldered on the second redistribution layer 22 as required. Specifically, the second chip 12 and the third chip 13 are each placed face down.
And S107, the second chip 12 is molded by adopting the second insulating material 52.
S108, after the first carrier 100 is removed, the first solder balls 60 are formed on one side of the first redistribution layer 21.
Optionally, with continued reference to fig. 6 and 7, in this embodiment of the present application, it may further include:
s109, stacking the second carrier 200 on the first solder ball 60 side. The second carrier 200 may have any structure of a wiring provided in a redistribution layer, a substrate, or a silicon interposer (interposer), and is not limited herein.
Alternatively, in this embodiment of the present application, after the first redistribution layer 21 is formed in the step S102, and before the first chip 11 and the vertical silicon bridge 30 are encapsulated with the first insulating material 51 in the step S103, referring to fig. 7, the method may further include: a step of forming a vertical interconnect 40 on the first re-wiring layer 21. In particular, the vertical interconnect 40 may be an insulating via (through insulator via, TIV).
Fig. 8 is a schematic diagram schematically illustrating another specific structure of the chip package structure according to the embodiment of the present application. Referring to fig. 8, in another embodiment of the present application, the chip may be fixed first, and then the re-wiring layer may be directly formed on the upper surface of the chip to achieve connection, and the vertical silicon bridge 30 may be disposed face up. Specifically, the active surface S of the first chip 11 faces the first redistribution layer 21, and the first chip 11 is provided with the second microbump 111 coupled to the first redistribution layer 21 on the active surface S side; the active surface S of the second chip 12 faces the second redistribution layer 22, and the second chip 12 is provided with a third microbump 121 coupled to the second redistribution layer 22 on the active surface S side; the vertical silicon bridge 30 is soldered to the second redistribution layer 34 through the second solder ball 34 and coupled to the first redistribution layer 21 through the first micro bump 32.
With continued reference to fig. 8, in this embodiment of the present application, the second chip 12 may be fixed first, and then the second redistribution layer 22 may be fabricated on the active surface side of the second chip 12, so that a side of the second chip 12 facing away from the second redistribution layer 22 may have a second connection film 72 (DAF). Alternatively, the second tie film 72 may be optionally removed after the final preparation is completed.
With continued reference to fig. 8, in this embodiment of the present application, after the second redistribution layer 22 is prepared, the first chip 11 may be fixed to the surface of the second redistribution layer 22 facing the first chip 11 through the first connection film 71, so as to fabricate the first redistribution layer 21 on the active surface side of the first chip 11.
Fig. 9 is a schematic flow chart illustrating a method for manufacturing another chip package structure according to an embodiment of the present application; fig. 10 is a schematic diagram schematically showing the structure of each production process in the production method of fig. 9. Referring to fig. 9 and 10, the preparation method mainly comprises the following steps:
s201, referring to the steps shown in fig. 4, a vertical silicon bridge 30 is formed, the vertical silicon bridge 30 has a through silicon via 31, one side of the vertical silicon bridge 30 is provided with a third redistribution layer 33 coupled with the through silicon via 31, and a second solder ball 34 coupled with the third redistribution layer 33, and the other side of the vertical silicon bridge 30 is provided with a first microbump 32 coupled with the through silicon via 31.
S202, fixing the second chip 12 on the first carrier 100 through the second connection film 72, wherein the third micro bump 121 of the second chip 12 is located at a side facing away from the first carrier 100. Specifically, a layer of second connection film 72 may be covered on the first carrier 100, and then another layer of second connection film 72 is fixed at the position where the second chip 12 is required to be fixed, where the materials of the two layers of second connection films 72 may be different, so as to facilitate the subsequent peeling of the first carrier 100.
Optionally, the third chip 13 may also be fixed on the first carrier plate 100 as needed. The second chip 12 and the third chip 13 are each placed face up.
S203, the second chip 12 is molded by the second insulating material 52, and the third micro bump 121 of the second chip 12 is exposed. The third micro bump 121 exposing the second chip 12 may be polished by CMP.
S204, forming a second redistribution layer 22 coupled to the third microbump 121 of the second chip 12. Specifically, each film layer constituting the second redistribution layer 22 may be directly fabricated on the upper surface of the second chip 12 after plastic encapsulation.
S205, the first chip 11 is fixed on the second redistribution layer 22 through the first connection film 71, and the vertical silicon bridge 30 is soldered through the second solder ball 34 of the vertical silicon bridge 30, where the second micro bump 111 of the first chip 11 is located at a side far from the first carrier 100. Specifically, the first chip 11 is placed face up and the vertical silicon bridge 30 is placed face down.
S206, the first chip 11 and the vertical silicon bridge 30 are encapsulated by the first insulating material 51, and the second micro bump 111 of the first chip 11 and the first micro bump 32 of the vertical silicon bridge 30 are exposed. Specifically, the second micro bump 111 of the first chip 11 and the first micro bump 32 of the vertical silicon bridge 30 may be polished in a CMP manner.
S207, a first rewiring layer 21 coupled with the second micro-bump 111 of the first chip 11 and the first micro-bump 32 of the vertical silicon bridge 30 is formed. Specifically, each film layer constituting the first redistribution layer 21 may be directly fabricated on the upper surfaces of the first chip 11 and the vertical silicon bridge 30 after plastic packaging.
S208, forming the first solder balls 60 on the first redistribution layer 21, and removing the first carrier 100.
Optionally, with continued reference to fig. 9 and 10, in this embodiment of the present application, it may further include:
s209, removing the second connection film 72.
Alternatively, in this embodiment of the present application, after the second redistribution layer is formed in the step S204 and before the first chip and the vertical silicon bridge are encapsulated with the first insulating material in the step S206, referring to fig. 10, the method may further include: a step of forming a vertical interconnect 40 on the second redistribution layer 22. In particular, the vertical interconnect 40 may be an insulating via (through insulator via, TIV).
Based on the same technical conception, the application also provides a terminal device, which comprises a circuit board and the chip packaging structure arranged on the circuit board in any technical scheme. The terminal device provided by the embodiment of the application includes, but is not limited to, a smart phone, a smart television set-top box, a personal computer (personal computer, PC), a wearable device, a smart broadband and the like, which are not listed here. Since the principle of the terminal device for solving the problem is similar to that of the chip packaging structure, the implementation of the terminal device can be referred to the implementation of the chip packaging structure, and the repetition is omitted.
It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present application without departing from the scope of the embodiments of the application. Thus, if such modifications and variations of the embodiments of the present application fall within the scope of the claims and the equivalents thereof, the present application is also intended to include such modifications and variations.
Claims (15)
- A chip package structure, comprising:a first rewiring layer;a first chip disposed on the first redistribution layer and coupled to the first redistribution layer;a vertical silicon bridge disposed on the first redistribution layer side-by-side with the first chip, the vertical silicon bridge having a through silicon via coupled to the first redistribution layer;a second redistribution layer disposed on the vertical silicon bridge and the first chip and coupled with the through silicon via;a second chip disposed on the second redistribution layer and coupled with the second redistribution layer;the second chip is vertically interconnected with the first chip through the second redistribution layer, the through silicon via and the first redistribution layer in sequence.
- The chip package structure of claim 1, further comprising a vertical interconnect coupled between the first redistribution layer and the second redistribution layer.
- The chip package structure of claim 1, further comprising a third chip disposed on the second redistribution layer side-by-side with the second chip and coupled with the second redistribution layer.
- The chip package structure of claim 1, further comprising a first solder ball disposed on a surface of the first redistribution layer facing away from the first chip and the vertical silicon bridge, and coupled to the first redistribution layer.
- The chip package structure of claim 1, further comprising a first insulating material and a second insulating material;the first insulating material wraps the first chip and the vertical silicon bridge, and the second insulating material wraps the second chip.
- The chip package structure of any of claims 1-5, wherein a side of the vertical silicon bridge is provided with a third redistribution layer coupled to the through silicon via and a second solder ball coupled to the third redistribution layer;the other side of the vertical silicon bridge is provided with a first micro-bump coupled with the silicon through hole.
- The chip package structure of claim 6, wherein the vertical silicon bridge is soldered to the first redistribution layer through the second solder ball, the vertical silicon bridge being coupled to the second redistribution layer through the first micro bump;the active surface of the first chip faces the first rewiring layer, and a third solder ball welded with the first rewiring layer is arranged on one side of the active surface of the first chip;the active surface of the second chip faces the second redistribution layer, and a fourth solder ball welded with the second redistribution layer is arranged on one side of the active surface of the second chip.
- The chip package structure of claim 6, wherein the vertical silicon bridge is soldered to the second redistribution layer through the second solder ball, the vertical silicon bridge being coupled to the first redistribution layer through the first micro-bump;the active surface of the first chip faces the first rewiring layer, and a second micro-bump coupled with the first rewiring layer is arranged on one side of the active surface of the first chip;the active surface of the second chip faces the second redistribution layer, and a third micro-bump coupled with the second redistribution layer is arranged on one side of the active surface of the second chip.
- The chip package structure of claim 8, wherein the first chip is fixed to a surface of the second redistribution layer facing the first chip through a first connection film.
- The chip package structure of claim 9, wherein a side of the second chip facing away from the second redistribution layer has a second connection film.
- A terminal device, comprising: a circuit board and a chip package structure as claimed in any one of claims 1 to 10 disposed on said circuit board.
- The preparation method of the chip packaging structure is characterized by comprising the following steps:forming a vertical silicon bridge, wherein the vertical silicon bridge is provided with a silicon through hole, one side of the vertical silicon bridge is provided with a third wiring layer coupled with the silicon through hole, and a second solder ball coupled with the third wiring layer, and the other side of the vertical silicon bridge is provided with a first micro-bump coupled with the silicon through hole;forming a first rewiring layer on a first carrier plate;soldering the first chip on the first rewiring layer through a third solder ball of the first chip, and soldering the vertical silicon bridge through a second solder ball of the vertical silicon bridge;plastic packaging the first chip and the vertical silicon bridge by adopting a first insulating material, and exposing a first micro bump of the vertical silicon bridge;forming a second redistribution layer coupled to the first micro bump of the vertical silicon bridge;soldering the second chip on the second redistribution layer through fourth solder balls of the second chip;adopting a second insulating material to plastic package the second chip;and removing the first carrier plate and forming a first solder ball on one side of the first rewiring layer.
- The method of manufacturing of claim 12, further comprising, after forming the first redistribution layer and before plastic packaging the first chip and the vertical silicon bridge with a first insulating material:vertical interconnects are formed on the first redistribution layer.
- The preparation method of the chip packaging structure is characterized by comprising the following steps:forming a vertical silicon bridge, wherein the vertical silicon bridge is provided with a silicon through hole, one side of the vertical silicon bridge is provided with a third wiring layer coupled with the silicon through hole, and a second solder ball coupled with the third wiring layer, and the other side of the vertical silicon bridge is provided with a first micro-bump coupled with the silicon through hole;a second chip is fixed on the first carrier plate through a second connecting film, and a third micro-bump of the second chip is positioned at one side away from the first carrier plate;the second chip is encapsulated by adopting a second insulating material, and a third micro-bump of the second chip is exposed;forming a second redistribution layer coupled to a third microbump of the second chip;fixing a first chip on the second redistribution layer through a first connection film, and welding the vertical silicon bridge through a second welding ball of the vertical silicon bridge; the second micro-bump of the first chip is positioned at one side far away from the first carrier plate;the first chip and the vertical silicon bridge are encapsulated by adopting a first insulating material, and the second micro-bump of the first chip and the first micro-bump of the vertical silicon bridge are exposed;forming a first rewiring layer coupled to the second microbump of the first chip and the first microbump of the vertical silicon bridge;and forming a first solder ball on the first rewiring layer, and removing the first carrier plate.
- The method of manufacturing of claim 14, further comprising, after forming the second redistribution layer and before plastic packaging the first chip and the vertical silicon bridge with a first insulating material:vertical interconnects are formed on the second redistribution layer.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2021/097053 WO2022251986A1 (en) | 2021-05-29 | 2021-05-29 | Chip packaging structure and preparation method therefor, and terminal device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116648780A true CN116648780A (en) | 2023-08-25 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202180086852.5A Pending CN116648780A (en) | 2021-05-29 | 2021-05-29 | Chip packaging structure, preparation method thereof and terminal equipment |
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| CN (1) | CN116648780A (en) |
| WO (1) | WO2022251986A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8115292B2 (en) * | 2008-10-23 | 2012-02-14 | United Test And Assembly Center Ltd. | Interposer for semiconductor package |
| CN109300837B (en) * | 2017-07-25 | 2023-10-20 | 华天科技（昆山）电子有限公司 | Thin 3D fan-out packaging structure and wafer level packaging method |
| US11862546B2 (en) * | 2019-11-27 | 2024-01-02 | Applied Materials, Inc. | Package core assembly and fabrication methods |
| CN112802820B (en) * | 2021-01-15 | 2022-03-11 | 上海航天电子通讯设备研究所 | Three-dimensional packaging structure based on silicon-aluminum alloy vertical interconnection packaging substrate and LCP rewiring and preparation method |
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- 2021-05-29 CN CN202180086852.5A patent/CN116648780A/en active Pending
- 2021-05-29 WO PCT/CN2021/097053 patent/WO2022251986A1/en active Application Filing
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| WO2022251986A1 (en) | 2022-12-08 |
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