CN116648004A - System-in-package method based on medium integrated suspension line platform - Google Patents

System-in-package method based on medium integrated suspension line platform Download PDF

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Publication number
CN116648004A
CN116648004A CN202310513246.8A CN202310513246A CN116648004A CN 116648004 A CN116648004 A CN 116648004A CN 202310513246 A CN202310513246 A CN 202310513246A CN 116648004 A CN116648004 A CN 116648004A
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CN
China
Prior art keywords
sisl
circuits
suspension line
cavity
line platform
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310513246.8A
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Chinese (zh)
Inventor
王勇强
王瀚永
马凯学
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Tianjin University
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Tianjin University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tianjin University filed Critical Tianjin University
Priority to CN202310513246.8A priority Critical patent/CN116648004A/en
Publication of CN116648004A publication Critical patent/CN116648004A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H05K3/4015—Surface contacts, e.g. bumps using auxiliary conductive elements, e.g. pieces of metal foil, metallic spheres
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Variable-Direction Aerials And Aerial Arrays (AREA)

Abstract

The application discloses a system-level packaging method based on a medium integrated suspension line platform, which integrates active devices and circuits, passive devices and circuits, chips, antennas and components in the same or different cavities of a SISL structure for interconnection packaging; the cavities are interconnected laterally and/or longitudinally by a SISL transition structure. The application integrates the active device and the circuit, the passive device and the circuit, the chip, the antenna and the component into the same or different cavities of the SISL structure for interconnection packaging based on the medium integrated suspension line platform, electromagnetic waves are transmitted in the air cavity, dielectric loss is lower, vertical or horizontal interconnection of the active device and the circuit, the passive device and the circuit, the chip, the antenna and the component can be realized, and the entity system has high integration level; low cost interconnections and packaging of active devices and circuits, passive devices and circuits, chips, antennas, components can be achieved.

Description

System-in-package method based on medium integrated suspension line platform
Technical Field
The application relates to a packaging system with an air cavity, in particular to a system-in-package method based on a medium integrated suspension line platform, and in particular relates to a system-in-package of active devices, circuits, passive devices, circuits, chips, antennas, components and the like in the fields of radio frequency, microwaves and millimeter waves.
Background
With the rapid development of modern communication and radar technology, miniaturization, planarization and modularization of microwave and millimeter wave systems are required, while excellent performance and reliability are not lost. The multilayer board structure of the dielectric integrated suspension line (Substrate Integrated Suspended Line, SISL) is widely applied in the field of radio frequency microwave circuits due to the advantages of self-packaging, low loss, high power capacity, high integration and the like. However, at present, in each application scenario, there is no case of performing system level SISL self-packaging on active devices and circuits, passive devices and circuits, chips, antennas, components and the like.
Disclosure of Invention
The application aims at providing a system-in-package method with low loss, high integration and low cost for active devices and circuits, passive devices and circuits, chips, antennas, components and the like.
The technical scheme adopted for realizing the purpose of the application is as follows:
a system-level packaging method based on a medium integrated suspension line platform integrates an active device and a circuit, a passive device and a circuit, a chip, an antenna and a component into the same or different cavities of a SISL structure for interconnection packaging; the cavities are interconnected laterally and/or longitudinally by a SISL transition structure.
Preferably, each cavity is provided with N active devices and circuits, and N is more than or equal to 0.
Preferably, each cavity is provided with N passive devices and circuits, and N is more than or equal to 0.
Preferably, each cavity is provided with N chips, and N is more than or equal to 0.
Preferably, each cavity is provided with N antennas, and N is more than or equal to 0.
Preferably, each cavity is provided with N components, and N is more than or equal to 0.
Preferably, the number of the cavities is Q, and Q is more than or equal to 2.
Preferably, the antennas are distributed on a top dielectric substrate or a bottom dielectric substrate of the SISL structure, and the number of the antennas is N, wherein N is more than or equal to 0.
Preferably, the antennas are distributed on a top dielectric substrate, a middle dielectric substrate or a bottom dielectric substrate of the SISL structure, and the number of the antennas is N, wherein N is more than or equal to 0.
Preferably, the antennas are distributed on the upper metal layer or the lower metal layer of the top dielectric substrate, the upper metal layer or the lower metal layer of the middle dielectric substrate, or the upper metal layer or the lower metal layer of the bottom dielectric substrate.
The application packages active devices and circuits, passive devices and circuits, chips, antennas and non-devices in the same or different cavities of SISL structure for interconnection packaging based on a medium integrated suspension line platform; the cavities are transversely and/or longitudinally interconnected through the SISL transition structure, electromagnetic waves are transmitted in the air cavity, and dielectric loss is lower; the multilayer structure based on the medium integrated suspension line platform can realize the high integration level of an entity system by vertically or horizontally interconnecting active devices and circuits, passive devices and circuits, chips, antennas and components; the PCB board medium based on the medium integrated suspension line platform can realize low-cost interconnection and encapsulation of active devices and circuits, passive devices and circuits, chips, antennas and components.
Drawings
FIG. 1 is a schematic diagram of a system in package of a dielectric integrated suspension wire platform of the present application;
FIG. 2 is a cross-sectional view of an antenna portion of the present application (with the antenna being disposed on top of the top dielectric substrate);
FIG. 3 is a cross-sectional view of an antenna portion type II (with the antennas distributed on the lower layer of the top dielectric substrate) according to the present application;
FIG. 4 is a cross-sectional view of an antenna portion of the present application of type three (antennas distributed on the top layer of the middle layer dielectric substrate, where the antennas are metal-free with respect to the top and bottom layers of the top layer dielectric substrate);
FIG. 5 is a cross-sectional view of a fourth type of antenna portion of the present application (antenna distributed on the lower layer of the middle dielectric substrate, where the antenna corresponds to the upper and lower layers of the top dielectric substrate without metal);
FIG. 6 is a cross-sectional view of an antenna portion of the present application of type five (with the antenna being disposed beneath the underlying dielectric substrate);
FIG. 7 is a cross-sectional view of a sixth type of antenna portion (with the antenna disposed on top of the underlying dielectric substrate) in accordance with the present application;
FIG. 8 is a cross-sectional view of an antenna portion of the present application of type seven (antenna is disposed on the lower layer of the middle dielectric substrate, where the antenna corresponds to the upper and lower layers of the bottom dielectric substrate without metal);
FIG. 9 is a cross-sectional view of an antenna portion type eight of the present application (antenna distributed on the upper layer of the middle dielectric substrate, where the antenna corresponds to the upper and lower layers of the bottom dielectric substrate without metal);
FIG. 10 is a cross-sectional view of a portion of an active device and circuit of the present application of type one (active device and circuit are only distributed in the upper cavity of the SISL structure);
FIG. 11 is a cross-sectional view of a portion of a second type of active device and circuit of the present application (active device and circuit are only distributed in the lower cavity of the SISL structure);
FIG. 12 is a cross-sectional view of a third type of active device and circuit portion of the present application (active device and circuit are simultaneously distributed in the upper and lower cavities of the SISL structure);
FIG. 13 is a cross-sectional view of a passive device and circuit portion type one of the present application (passive device and circuit are only distributed in the upper cavity of the SISL structure);
FIG. 14 is a cross-sectional view of a passive device and circuit portion type two of the present application (passive device and circuit are only distributed in the lower cavity of the SISL structure);
FIG. 15 is a cross-sectional view of a passive device and circuit portion of the present application of type three (passive device and circuit are simultaneously distributed in the upper and lower cavities of the SISL structure);
FIG. 16 is a cross-sectional view of a chip portion type one of the present application (chip is only distributed in the upper cavity of the SISL structure);
FIG. 17 is a cross-sectional view of a chip portion type II of the present application (chip is only distributed in the lower cavity of the SISL structure);
FIG. 18 is a cross-sectional view of a chip portion type III of the present application (chips are simultaneously distributed in the upper and lower cavities of the SISL structure);
FIG. 19 is a cross-sectional view of a component part type I of the present application (components are only distributed in the upper cavity of the SISL structure);
FIG. 20 is a cross-sectional view of a component part type II of the present application (components are only distributed in the lower cavity of the SISL structure);
FIG. 21 is a cross-sectional view of a component part type III of the present application (components are distributed in both the upper and lower cavities of the SISL structure);
FIG. 22 is a cross-sectional view of a first type of cavity structure portion (SISL cavity horizontal interconnect) of the application;
FIG. 23 is a cross-sectional view of a cavity structure portion type two (SISL cavity vertical interconnect) of the application;
FIG. 24 is a cross-sectional view of a third embodiment of the present application; (the SISL cavities are interconnected horizontally and vertically simultaneously);
FIG. 25 is a cross-sectional view of a first embodiment of the present application;
FIG. 26 is a cross-sectional view of a second embodiment of the present application;
FIG. 27 is a cross-sectional view of a third embodiment of the present application;
FIG. 28 is a cross-sectional view of a fourth embodiment of the present application;
fig. 29 is a cross-sectional view of a fifth embodiment of the present application.
Reference numerals illustrate:
1 is a metal layer, 2 is an antenna, 3 is a metalized through hole, 4 is a cavity, 5 is an active device, 6 is a chip heat dissipation hole, 7 is a chip, 8 is a component, 9 is a SISL transition structure, 10 is an antenna unit, 11 is a feed network, 12 is a ball implant, and 13 is a passive device.
Detailed Description
In order that the application may be fully understood and readily put into practical effect, it is to be understood that the application is not limited to the specific embodiments disclosed, but is to be accorded the full scope of any horizontal or vertical combination of the structures disclosed in FIGS. 1-29.
According to the embodiment of the application, one or more same or different active devices and circuits, passive devices and circuits, chips, antennas and components can be packaged and integrated through a medium integrated suspension line (SISL) platform. See fig. 1.
Example 1
In a preferred embodiment of the system in package based on the dielectric integrated suspension line platform, as shown in fig. 25, the passive devices and circuits, the active devices and circuits, and the components contained in the antenna, the chip, and the feed network are all distributed in the same SISL structure. The whole structure sequentially comprises a metal layer, a dielectric substrate, a metal layer, a dielectric substrate and a metal layer from top to bottom. The metal through holes at two ends of the integral structure penetrate from the top layer plate to the bottom layer plate to form a metal shield, so that the SISL structure is formed. The antennas forming the antenna unit are distributed on the upper layer metal of the top layer dielectric substrate and the upper layer metal of the middle layer dielectric substrate, and the fifth layer dielectric substrate is distributed with chip heat dissipation through holes. The chip is placed in the lower cavity of the SISL structure, the components forming the feed network are placed in the upper cavity of the SISL structure, and the components are interconnected through an active circuit or a passive circuit.
Example two
In a second preferred embodiment of the system in package based on the dielectric integrated suspension line platform, as shown in fig. 26, the passive devices and circuits, the active devices and circuits, and the components included in the antenna, the chip, and the feeding network formed by the components that form the antenna unit are longitudinally distributed among multiple SISL structures. The SISL cavity and the circuit between the SISL cavities are interconnected through a SISL vertical transition structure. The whole structure sequentially comprises a metal layer, a dielectric substrate, a metal layer, a dielectric substrate and a metal layer from top to bottom, a metal layer, a dielectric substrate, a metal layer, a dielectric substrate, a metal layer. The metal through holes at two ends of the integral structure penetrate from the top layer plate to the bottom layer plate to form a metal shield, so that the SISL structure is formed. The antennas are distributed on the upper metal of the top dielectric substrate and the upper metal of the third dielectric substrate, the chip is placed in the second cavity of the vertical structure, the components are respectively placed in the third cavity and the fourth cavity of the vertical structure, and the passive circuit and the active circuit are also distributed in the third cavity and the fourth cavity of the vertical structure.
Example III
In a third preferred embodiment of the system in package based on the dielectric integrated suspension line platform, as shown in fig. 27, the passive devices and circuits, the active devices and circuits, and the components included in the antenna, the chip, and the feeding network made up of the components that constitute the antenna unit are laterally distributed among multiple SISL structures. The SISL cavity and the circuit between the SISL cavities are interconnected by a SISL horizontal transition structure. The whole structure sequentially comprises a metal layer, a dielectric substrate, a metal layer, a dielectric substrate and a metal layer from top to bottom. The lateral multi-cavity SISL structure is constituted by a metal passage passing through from the top plate to the bottom plate. The antennas are distributed on the upper metal of the top dielectric substrate and the upper metal of the middle dielectric substrate, and the fifth dielectric substrate is distributed with chip heat dissipation through holes. The chip is placed in the lower cavity of the first SISL structure, and the feed network is distributed in the second SISL structure and the 3 rd SISL structure.
Example IV
In a fourth preferred embodiment of the system in package based on a dielectric integrated suspension wire platform, as shown in fig. 28, the passive devices and circuits, the active devices and circuits, and the components included in the antennas, chips, and the feed network formed by the components that constitute the antenna unit are distributed in multiple SISL structures both longitudinally and laterally. The SISL cavity and the circuit between the SISL cavities are interconnected through a SISL vertical transition structure and a SISL horizontal transition structure. The whole structure sequentially comprises a metal layer, a dielectric substrate, a metal layer, a dielectric substrate and a metal layer from top to bottom, metal layer, dielectric substrate, metal layer, dielectric substrate, metal layer. The metal passing through from the top plate to the bottom plate constitutes a transverse multi-cavity SISL structure and a longitudinal multi-cavity SISL structure. The antennas are distributed on the upper layer metal of the top dielectric substrate and the upper layer metal of the second dielectric substrate. The chip is placed in the cavity of the 1 st cavity from right to left and the second cavity from top to bottom, and the feed network is distributed in the four cavities below.
Example five
In a fifth preferred embodiment of the system in package based on a dielectric integrated suspension wire platform, as shown in fig. 29, the circuits and systems already packaged by the SISL structure can be interconnected with a plurality of different circuits and systems in the form of a surface mount, such as through ball placement.
The foregoing is merely a preferred embodiment of the present application and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present application, which are intended to be comprehended within the scope of the present application.

Claims (10)

1. The system-level packaging method based on the medium integrated suspension line platform is characterized in that active devices and circuits, passive devices and circuits, chips, antennas and components are integrated in the same or different cavities of a SISL structure to be subjected to interconnection packaging; the cavities are interconnected laterally and/or longitudinally by a SISL transition structure.
2. The system-in-package method based on a dielectric integrated suspension line platform according to claim 1, wherein each cavity has N active devices and circuits, N being greater than or equal to 0.
3. The system-in-package method based on a dielectric integrated suspension line platform according to claim 1, wherein each cavity has N passive devices and circuits, N is greater than or equal to 0.
4. The system-in-package method based on a dielectric integrated suspension line platform according to claim 1, wherein each cavity has N chips, N being greater than or equal to 0.
5. The system-in-package method based on a dielectric integrated suspension line platform according to claim 1, wherein each cavity has N antennas, N being greater than or equal to 0.
6. The system-in-package method based on a dielectric integrated suspension line platform according to claim 1, wherein each cavity has N components, N being greater than or equal to 0.
7. The system-in-package method based on the medium integrated suspension line platform of claim 1, wherein the number of cavities is Q, and Q is more than or equal to 2.
8. The system-in-package method based on the dielectric integrated suspension line platform of claim 1, wherein the antennas are distributed on a top dielectric substrate, a middle dielectric substrate or a bottom dielectric substrate of the SISL structure, and the number of the antennas is N, wherein N is more than or equal to 0.
9. The system-in-package method of claim 1, wherein the antennas are disposed on an upper metal layer or a lower metal layer of the top dielectric substrate, an upper metal layer or a lower metal layer of the middle dielectric substrate, or an upper metal layer or a lower metal layer of the bottom dielectric substrate.
10. The system-in-package method based on the medium integrated suspension line platform according to claim 1, wherein radiating holes are distributed on the upper medium substrate or the lower medium substrate of the cavity where the chip is placed, and the number of the radiating holes is K, wherein K is more than or equal to 0.
CN202310513246.8A 2023-05-09 2023-05-09 System-in-package method based on medium integrated suspension line platform Pending CN116648004A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310513246.8A CN116648004A (en) 2023-05-09 2023-05-09 System-in-package method based on medium integrated suspension line platform

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310513246.8A CN116648004A (en) 2023-05-09 2023-05-09 System-in-package method based on medium integrated suspension line platform

Publications (1)

Publication Number Publication Date
CN116648004A true CN116648004A (en) 2023-08-25

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310513246.8A Pending CN116648004A (en) 2023-05-09 2023-05-09 System-in-package method based on medium integrated suspension line platform

Country Status (1)

Country Link
CN (1) CN116648004A (en)

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