CN116647215A - Burr eliminating method and circuit in switching process of differential clock driving circuit - Google Patents

Burr eliminating method and circuit in switching process of differential clock driving circuit Download PDF

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Publication number
CN116647215A
CN116647215A CN202310564254.5A CN202310564254A CN116647215A CN 116647215 A CN116647215 A CN 116647215A CN 202310564254 A CN202310564254 A CN 202310564254A CN 116647215 A CN116647215 A CN 116647215A
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clock
clkn
clkp
output
ref
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CN116647215B (en
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朱欢
孙永升
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Chengdu Cetc Xingtuo Technology Co ltd
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Chengdu Cetc Xingtuo Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/013—Modifications of generator to prevent operation by noise or interference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention discloses a burr eliminating method and a circuit in the switching process of a differential clock driving circuit, wherein the method comprises the following steps: differential input: generating two pairs of clock signals with the same frequency and the same phase based on a differential input clock signal of a clock chip, inputting one pair of clock signals into a clock main signal path as a differential clock, and inputting the other pair of clock signals into a clock synchronous circuit as a synchronous sampling clock; clock synchronization: the rising edge or the falling edge of the synchronous sampling clock is selected through the two D triggers, the clock synchronization is carried out on the sampled enabling signals at different time points, and the time Zhong Zhu signal path and the output stage driving circuit are controlled; output driving: and when the output clock is turned off, the strong pull-up control circuit performs strong pull-up or pull-down control on the output, and the output driving circuit transmits the clock signal of the clock main signal path and externally outputs the clock signal. The invention can realize that the output clock has no burr when being closed and opened.

Description

Burr eliminating method and circuit in switching process of differential clock driving circuit
Technical Field
The invention relates to the technical field of clock chip design, in particular to a burr eliminating method and a burr eliminating circuit in the switching process of a differential clock driving circuit.
Background
In the application scenario of the clock buffer chip, the clock frequency and jitter/offset performance of the clock buffer output are required to be higher, and the requirements can be met easily when the clock buffer works normally. However, some application scenarios not only require that the clock output by the clock buffer meet corresponding performance requirements during normal operation, but also require that the output clock frequency and jitter meet the corresponding performance requirements during the process of opening and closing the clock buffer output. However, in practice, many clock buffer products easily generate a jitter (glitch) on the clock output by the clock buffer during the process of closing and opening the internal drive, and this jitter has a great influence on the frequency and jitter performance of the output clock.
As shown in fig. 1, the circuit structure of a common clock buffer chip is shown, CLKP and CLKN are differential input clock signals of the clock buffer chip, PD is an off control signal of a clock buffer driving circuit, and a BUFF module can be used as a cascade of two-stage inverters, and a DRIVER module is an output stage driving circuit.
When the turn-off control signal pd=0, the clock buffer chip is in the normal working process, S2 and S4 are turned on, S1 and S3 are turned off, the output clkp_out and CLKP are signals with approximately the same frequency and the same phase (in practice, clkp_out has a certain transmission delay relative to CLKP), and clkn_out and CLKN are signals with approximately the same frequency and the same phase (in practice, clkn_out has a certain transmission delay relative to CLKN); when pd=1, S2, S4 are off, S1, S3 are on, clkp_out=clkn_out=0.
In practice, the turn-off control signal PD may have a phenomenon that the transition occurs in clk_out and clk_outn during the inversion (0 to 1 or 1 to 0).
As shown in FIG. 2, the dashed line marks are all the glottals. When the off control signal PD transitions from 0 to 1 during CLKP high, clkp_out exhibits a gap of narrow pulse width; PD jumps from 1 to 0 during the low level of CLKP, and CLKN_OUT exhibits a narrow pulse width of glove. In a practical scenario, the PD jumps either during CLKP high level or CLKP low level, and the PD jumps at random time, so that the common clock buffer circuit structure must generate a glitch when the output clock is turned on and off. The occurrence of the jitter changes the clock frequency in the current period and has a great influence on the jitter of the output clock.
Disclosure of Invention
In order to solve the problem of burrs of a clock chip in the process of opening and closing an output clock, the invention provides a method and a circuit for eliminating burrs in the process of switching a differential clock driving circuit.
The technical scheme adopted by the invention is as follows:
a burr eliminating method in the switching process of a differential clock driving circuit comprises the following steps:
s1, differential input: generating clock signals CLKP_REF and CLKP_DRV with the same frequency and the same phase based on a positive differential input clock signal CLKP of a clock chip, generating clock signals CLKN_REF and CLKN_DRV with the same frequency and the same phase based on a negative differential input clock signal CLKN of the clock chip, wherein the clock signals CLKP_DRV and CLKN_DRV are mutually differential clocks and are input into a clock main signal path, and the clock signals CLKP_REF and CLKN_REF are mutually differential clocks and are input into a clock synchronous circuit as synchronous sampling clocks;
s2, clock synchronization: the clock synchronization circuit selects the rising edge or the falling edge of the clock signal CLKP_REF through one D trigger, selects the rising edge or the falling edge of the clock signal CLKN_REF through the other D trigger, and performs clock synchronization on the sampled enabling signal D2A_CH_EN at different time points so as to generate CH_EN_DRV_VOP and CH_EN_DRV_VOM signals, and controls the clock main signal path and the output stage driving circuit so that the output clock signal does not generate burr when being closed and opened;
s3, output driving: the output stage driving circuit comprises two repeating units, wherein the repeating units comprise a strong pull control circuit and an output driving circuit, and the strong pull control circuit is configured to perform strong pull-up or pull-down control on the output when an output clock is turned off so as to keep the output in a fixed potential state; the output driving circuit is configured to transfer the clock signal of the clock main signal path and to output clock signals clkp_out and clkn_out externally.
Further, when the off control signal PD of the output stage driving circuit transitions from 0 to 1 and the D flip-flop is triggered by a clock rising edge, the process of closing the output clock signal includes:
the turn-off control signal PD jumps from 0 to 1, a D2A_CH_EN signal is obtained through the inversion of an analog inverter, and under the clock action of CLKN_REF and CLKP_REF, CH_EN_DRV_VOP and CH_EN_DRV_VOM signals are generated through sampling of the clock synchronization circuit;
the output clock signal clkp_out is turned off without burrs: under the synchronous action of the rising edge of the CLKN_REF clock, after the CLKP_OUT enters a 0 level state, the clock main signal path part corresponding to the CLKP is closed, and then the strong pull control circuit is opened to forcedly pull down the CLKP_OUT to the 0 level state without generating burrs during the process;
the output clock signal clkn_out is turned off without burrs: under the synchronization of the rising edge of the clkp_ref clock, the ch_en_drv_vom immediately closes the clock main signal path portion corresponding to CLKN after clkn_out enters the 0 level state, and then the pull-up control circuit is turned on to forcedly pull down clkn_out to the 0 level state without generating burrs during this period.
Further, when the off control signal PD of the output stage driving circuit transitions from 1 to 0 and the D flip-flop is triggered by a clock rising edge, the process of opening the output clock signal includes:
the turn-off control signal PD jumps from 1 to 0, a D2A_CH_EN signal is obtained through the inversion of an analog inverter, and under the clock action of CLKN_REF and CLKP_REF, CH_EN_DRV_VOP and CH_EN_DRV_VOM signals are generated through sampling of the clock synchronization circuit;
the output clock signal clkp_out is turned on without burrs: under the synchronous action of the rising edge of the CLKN_REF clock, after the CLKP_DRV enters a 0 level state, a clock main signal path part corresponding to the CLKP is opened, the CLKP_OUT is driven to the 0 level state by the output driving circuit and no burr is generated during the clock main signal path part, and then the strong pull control circuit is closed;
the no-glove on of the output clock signal clkn_out: under the synchronization action of the rising edge of the CLKP_REF clock, after CLKN_DRV enters a 0 level state, a clock main signal path part corresponding to CLKN is opened, CLKN_OUT is driven to the 0 level state by the output driving circuit and no burr is generated during the clock main signal path part, and then the strong pull control circuit is closed.
Further, the off control signal PD is sampled and taken out after being synchronously clocked by the digital circuit at least twice, and then is input to the analog inverter.
Further, the digital circuit employs a forward differential input clock signal CLKP or a reverse differential input clock signal CLKN as a clock source.
A glitch elimination circuit in the switching process of a differential clock driving circuit, which is applied to a clock chip, the glitch elimination circuit comprising:
a differential input circuit configured to generate clock signals clkp_ref and clkp_drv of the same frequency and the same phase based on a positive differential input clock signal CLKP of the clock chip, generate clock signals clkn_ref and clkn_drv of the same frequency and the same phase based on a negative differential input clock signal CLKN of the clock chip, wherein the clock signals clkp_drv and clkn_drv are differential clocks with each other and are input to the clock main signal path, and the clock signals clkp_ref and clkn_ref are differential clocks with each other and are input to the clock synchronization circuit as synchronous sampling clocks;
a clock synchronization circuit configured to select a rising edge or a falling edge of the clock signal clkp_ref by one D flip-flop, select a rising edge or a falling edge of the clock signal clkn_ref by another D flip-flop, and clock-synchronize the sampled enable signal d2a_ch_en at different time points, thereby generating ch_en_drv_vop and ch_en_drv_vom signals, and control the clock main signal path and the output stage driving circuit so that the output clock signal does not generate glitch when turned off and on;
an output stage driving circuit configured as two repeating units including a strong pull control circuit configured to perform strong pull-up or pull-down control of an output when an output clock is turned off, to keep the output in a fixed potential state; the output driving circuit is configured to transfer the clock signal of the clock main signal path and to output clock signals clkp_out and clkn_out externally.
Further, when the off control signal PD of the output stage driving circuit transitions from 0 to 1 and the D flip-flop is triggered by a clock rising edge, the process of closing the output clock signal includes:
the turn-off control signal PD jumps from 0 to 1, a D2A_CH_EN signal is obtained through the inversion of an analog inverter, and under the clock action of CLKN_REF and CLKP_REF, CH_EN_DRV_VOP and CH_EN_DRV_VOM signals are generated through sampling of the clock synchronization circuit;
the output clock signal clkp_out is turned off without burrs: under the synchronous action of the rising edge of the CLKN_REF clock, after the CLKP_OUT enters a 0 level state, the clock main signal path part corresponding to the CLKP is closed, and then the strong pull control circuit is opened to forcedly pull down the CLKP_OUT to the 0 level state without generating burrs during the process;
the output clock signal clkn_out is turned off without burrs: under the synchronization of the rising edge of the clkp_ref clock, the ch_en_drv_vom immediately closes the clock main signal path portion corresponding to CLKN after clkn_out enters the 0 level state, and then the pull-up control circuit is turned on to forcedly pull down clkn_out to the 0 level state without generating burrs during this period.
Further, when the off control signal PD of the output stage driving circuit transitions from 1 to 0 and the D flip-flop is triggered by a clock rising edge, the process of opening the output clock signal includes:
the turn-off control signal PD jumps from 1 to 0, a D2A_CH_EN signal is obtained through the inversion of an analog inverter, and under the clock action of CLKN_REF and CLKP_REF, CH_EN_DRV_VOP and CH_EN_DRV_VOM signals are generated through sampling of the clock synchronization circuit;
the output clock signal clkp_out is turned on without burrs: under the synchronous action of the rising edge of the CLKN_REF clock, after the CLKP_DRV enters a 0 level state, a clock main signal path part corresponding to the CLKP is opened, the CLKP_OUT is driven to the 0 level state by the output driving circuit and no burr is generated during the clock main signal path part, and then the strong pull control circuit is closed;
the no-glove on of the output clock signal clkn_out: under the synchronization action of the rising edge of the CLKP_REF clock, after CLKN_DRV enters a 0 level state, a clock main signal path part corresponding to CLKN is opened, CLKN_OUT is driven to the 0 level state by the output driving circuit and no burr is generated during the clock main signal path part, and then the strong pull control circuit is closed.
Further, the off control signal PD is sampled and taken out after being synchronously clocked by the digital circuit at least twice, and then is input to the analog inverter.
Further, the digital circuit employs a forward differential input clock signal CLKP or a reverse differential input clock signal CLKN as a clock source.
The invention has the beneficial effects that:
in order to solve the problem of burrs occurring in output during the opening and closing processes of a clock driving circuit, the invention selects rising edges or falling edges of synchronous sampling clocks CLKP_REF and CLKN_REF through two D triggers, and clock synchronizes the sampled enabling signals at different time points, thereby generating CH_EN_DRV_VOP and CH_EN_DRV_VOM signals, and controlling a Zhong Zhu signal path and an output stage driving circuit so as to realize that the output clock does not have burrs when being closed and opened.
Drawings
Fig. 1 is a simplified block diagram of a driving circuit of a differential clock buffer chip of a conventional structure.
Fig. 2 shows a timing chart in which the off control signal PD varies to cause glitch on the output.
FIG. 3 is a block diagram of a system with no glitch output when the circuit is on and off in embodiment 1.
Fig. 4 is a timing chart of the circuit of embodiment 1 with no glitch output on and off.
Fig. 5 is a block diagram of a system with no glitch output when the circuit is on and off in embodiment 2.
Fig. 6 is a timing chart of the circuit of embodiment 2 with no glitch output on and off.
Fig. 7 is a schematic diagram of the internal circuit structure of the BUFF module in embodiment 2.
Fig. 8 is a schematic diagram of the internal circuit structure of the INV module in embodiment 2.
Fig. 9 is a schematic diagram of the internal circuit structure of the inv_en module in embodiment 2.
Fig. 10 is one of the block diagrams of the output off or on no-glitch output system in embodiment 3.
Fig. 11 is one of timing charts in which the output is turned off or on without the glitch output in embodiment 3.
FIG. 12 is a second block diagram of the output off or on no-glitch output system of embodiment 3.
FIG. 13 is a second timing diagram of the output off or on no-glove output in embodiment 3.
FIG. 14, embodiment 3, outputs a third block diagram of the off or on no-glove output system.
FIG. 15 is a third timing chart of the output on or off of the no-glove output in embodiment 3.
Detailed Description
Specific embodiments of the present invention will now be described in order to provide a clearer understanding of the technical features, objects and effects of the present invention. It should be understood that the particular embodiments described herein are illustrative only and are not intended to limit the invention, i.e., the embodiments described are merely some, but not all, of the embodiments of the invention. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present invention.
Example 1
As shown in fig. 3, the present embodiment provides a method for removing burrs during a switching process of a differential clock driving circuit, which includes the following steps:
s1, differential input: generating clock signals CLKP_REF and CLKP_DRV with the same frequency and the same phase based on a positive differential input clock signal CLKP of a clock chip, generating clock signals CLKN_REF and CLKN_DRV with the same frequency and the same phase based on a negative differential input clock signal CLKN of the clock chip, wherein the clock signals CLKP_DRV and CLKN_DRV are mutually differential clocks and are input into a clock main signal path, and the clock signals CLKP_REF and CLKN_REF are mutually differential clocks and are input into a clock synchronous circuit as synchronous sampling clocks;
s2, clock synchronization: the clock synchronization circuit selects the rising edge or the falling edge of the clock signal CLKP_REF through one D trigger, selects the rising edge or the falling edge of the clock signal CLKN_REF through the other D trigger, and performs clock synchronization on the sampled enabling signal D2A_CH_EN at different time points so as to generate CH_EN_DRV_VOP and CH_EN_DRV_VOM signals, and controls a Zhong Zhu signal path and the output stage driving circuit so that the output clock signal does not generate burr glitch when being closed and opened;
s3, output driving: the output stage driving circuit comprises two repeating units, wherein the repeating units comprise a strong pull control circuit and an output driving circuit, and the strong pull control circuit is configured to perform strong pull-up or pull-down control on the output when the output clock is turned off, so that the output is kept in a fixed potential state; the output driving circuit is configured to transfer the clock signal of the clock main signal path and externally output clock signals clkp_out and clkn_out.
Preferably, when the off control signal PD of the output stage driving circuit transitions from 0 to 1 and the D flip-flop is triggered with a clock rising edge, the shutdown process of the output clock signal includes:
the turn-off control signal PD jumps from 0 to 1, the D2A_CH_EN signal is obtained through the inversion of an analog inverter, and under the clock action of the CLKN_REF and the CLKP_REF, the CH_EN_DRV_VOP and the CH_EN_DRV_VOM signals are generated through sampling of a clock synchronization circuit;
the output clock signal clkp_out is turned off without burrs: under the synchronization of the rising edge of the clkn_ref clock, the ch_en_drv_vop closes the clock main signal path portion corresponding to CLKP after clkp_out enters the 0 level state, and then the strong pull control circuit is opened to forcedly pull down clkp_out to the 0 level state without generating burrs during this period. The final effect is as follows: it is possible to turn off clkp_out after clkp_out enters the 0 level state and to strongly pull it to the 0 level state by turning on its strong pull control circuit.
The output clock signal clkn_out is turned off without burrs: under the synchronization of the rising edge of the clkp_ref clock, the ch_en_drv_vom closes the clock main signal path portion corresponding to CLKN immediately after clkn_out enters the 0 level state, and then the strong pull control circuit is opened to forcedly pull down clkn_out to the 0 level state without generating burrs during this period. The final effect is as follows: after clkn_out enters the 0 level state, clkn_out is turned off and is strongly pulled to the 0 level state by turning on its strong pull control circuit.
Preferably, when the off control signal PD of the output stage driving circuit transitions from 1 to 0 and the D flip-flop is triggered with a clock rising edge, the opening process of the output clock signal includes:
the turn-off control signal PD jumps from 1 to 0, the D2A_CH_EN signal is obtained through the inversion of an analog inverter, and under the clock action of the CLKN_REF and the CLKP_REF, the CH_EN_DRV_VOP and the CH_EN_DRV_VOM signals are generated through sampling of a clock synchronization circuit;
the output clock signal clkp_out is turned on without burrs: under the synchronization of the rising edge of the clkn_ref clock, the ch_en_drv_vop opens the clock main signal path portion corresponding to CLKP after clkp_drv enters the 0 level state, clkp_out is driven to the 0 level state by the output driving circuit and no glitch is generated during this period, and then the strong pull control circuit is turned off. The final effect is as follows: the method can realize that the CLKP_OUT main signal path is opened immediately after the CLKP_DRV enters a 0 level state to transmit a main clock signal, and the function of a strong pull control circuit is closed.
The no-glove on of the output clock signal clkn_out: under the synchronization of the rising edge of the clkp_ref clock, the ch_en_drv_vom will turn on the clock main signal path portion corresponding to CLKN after clkn_drv enters the 0 level state, clkn_out is driven to the 0 level state by the output driving circuit and no glitch is generated during this period, and then the strong pull control circuit is turned off. The final effect is as follows: the method can realize that the CLKN_OUT main signal path is opened immediately after the CLKN_DRV enters a 0 level state to transmit a main clock signal, and the function of a strong pull control circuit is closed.
More preferably, the off control signal PD is sampled and taken out after being clocked at least twice by the digital circuit clock and then input to the analog inverter. The main purpose of beating at least twice is to prevent the D flip-flop in the clock synchronization circuit from sampling PD, and taking the intermediate potential to cause the D flip-flop to output an uncertain state. In addition, the digital circuit employs a forward differential input clock signal CLKP or an inverse differential input clock signal CLKN as a clock source.
As shown in fig. 3, the present embodiment further provides a glitch elimination circuit in a switching process of a differential clock driving circuit, which is applied to a clock chip, and the glitch elimination circuit includes a differential input circuit, a clock synchronization circuit and an output stage driving circuit, wherein:
the differential input circuit is configured to generate clock signals clkp_ref and clkp_drv of the same frequency and the same phase based on a positive differential input clock signal CLKP of the clock chip, generate clock signals clkn_ref and clkn_drv of the same frequency and the same phase based on a negative differential input clock signal CLKN of the clock chip, wherein the clock signals clkp_drv and clkn_drv are differential clocks with each other and are input to the clock main signal path, and the clock signals clkp_ref and clkn_ref are differential clocks with each other and are input to the clock synchronization circuit as synchronous sampling clocks.
The clock synchronization circuit is configured to select a rising edge or a falling edge of the clock signal clkp_ref by one D flip-flop, select a rising edge or a falling edge of the clock signal clkn_ref by another D flip-flop, and clock-synchronize the sampled enable signal d2a_ch_en at different time points, thereby generating ch_en_drv_vop and ch_en_drv_vom signals, and control the timing Zhong Zhu signal path and the output stage driving circuit so that the output clock signal does not generate a glitch when turned off and on.
The output stage driving circuit is configured as two repeating units, the repeating units comprise a strong pull control circuit and an output driving circuit, and the strong pull control circuit is configured to perform strong pull-up or pull-down control on the output when the output clock is turned off, so that the output is kept in a fixed potential state; the output driving circuit is configured to transfer the clock signal of the clock main signal path and externally output clock signals clkp_out and clkn_out.
In summary, in this embodiment, the rising edge or the falling edge of the synchronous sampling clocks clkp_ref and clkn_ref are selected by the two D flip-flops, and the sampled enable signals are clock-synchronized at different time points, so as to generate the ch_en_drv_vop and ch_en_drv_vom signals, and control the Zhong Zhu signal path and the output stage driving circuit, so that no burrs occur when the output clock is turned off and turned on. As shown in fig. 4, it can be seen that clkp_out and clkn_out will not have burrs when they are turned off and on, but because clock synchronization technology is adopted in the scheme, when PD is turned off and on, the output needs to wait 3-4 clock cycles before it can be turned off and on.
Example 2
This example is based on example 1:
as shown in fig. 5, the present embodiment provides a glitch elimination circuit in the switching process of a differential clock driving circuit, in which the following important signals are illustrated:
1. clkp_ref and clkn_ref are differential clocks from each other, clkp_drv and clkn_ref
Clkn_drv are differential clocks to each other;
2. clkp_ref and clkp_drv are the same-frequency and same-phase clocks, clkn_ref and clkn_drv are the same-frequency and same-phase clocks;
3. clkp_ref, clkn_ref are clock synchronization signals, clkp_drv, clkn_drv, vop_up, vop_dn, vom_up, vom_dn are clock signals on the differential clock master signal path;
4. dff_0, dff_1, dff_2 are all conventional D flip-flop function blocks (without special explanation, all use rising edge triggering);
5. BUFF is a buffer of a conventional two-stage inverter series structure, as shown in FIG. 7;
6. INV is a conventional inverter, as shown in fig. 8;
7. inv_en in Driver is an inverter with an enabling function: when en=0, its output is 0; when en=1, it is equivalent to a conventional inverter, as shown in fig. 9;
8. the strong pull control circuits in the Driver all adopt small-size NMOS tubes to carry out upward and downward pull control;
9. the output driving circuits in the Driver all adopt large-size NMOS tubes to drive the output.
1. Taking PD as an example from 0 to 1, it is specifically described how to eliminate output glitch when the output clock is turned off (in this example, the D flip-flops are all triggered by clock rising edges):
(1) PD jumps from 0 to 1, after which the signal is inverted by an analog inverter to obtain a D2A_CH_EN (from 1 to 0) signal. This signal produces a ch_en_q (from 1 to 0) signal after 1 beat of analog local clkp_ref clock synchronization, which is simultaneously fed to dff_1 and dff_2 for clock synchronization. The difference between the two clocks is that dff_1 uses clkp_ref as the synchronizing clock and dff_2 uses clkn_ref as the synchronizing clock.
(2) First, the no-glove shutdown of clkp_out: after the ch_en_q (from 1 to 0) signal is generated, the first rising edge of clkn_ref comes first. At the same time as this rising edge comes, clkp_out toggles from 1 to 0, entering the 0 level state. Dff_2, at this rising edge sampling of clkn_ref, produces a ch_en_drv_vop transition (from 1 to 0) slightly later than the first rising edge of clkn_ref (due to the gate delay of CLK to Q of the D flip-flop being around 1 ns). The transition of ch_en_drv_vop (from 1 to 0) turns off the main signal path of clkn_drv clock and pulls vop_up, vop_dn down to 0, turning off the output drive circuit of clkp_out. Almost simultaneously, en_vop_up is still 0, en_vop_dn hops (from 0 to 1), and the strong pull control circuit of the clkp_out terminal acts to forcedly pull down clkp_out to 0, thereby realizing no-glitch closing of clkp_out.
(3) Then, the no-glove shutdown of clkn_out: after the ch_en_q (from 1 to 0) signal is generated, the first rising edge of clkp_ref (after half a period after the arrival of the first rising edge of clkn_ref) arrives. At the same time as this rising edge comes, clkn_out toggles from 1 to 0, entering the 0 level state. Dff_1, at this rising edge sampling of clkp_ref, produces a ch_en_drv_vom (from 1 to 0) transition slightly later than this rising edge of clkp_ref (due to the gate level delay of CLK to Q of the D flip-flop being around 1 ns). The transition of ch_en_drv_vom (from 1 to 0) turns off the main signal path of clkn_drv clock and pulls down vom_up, vom_dn to 0, turning off the output drive circuit of clkn_out. Almost simultaneously, en_vom_up is still 0, en_vom_dn (from 0 to 1) hops, and the strong pull control circuit of the clkn_out terminal acts to forcedly pull down clkn_out to 0, thereby realizing no-glitch closing of clkn_out.
2. Taking the PD transition from 1 to 0 as an example, it is specifically described how to eliminate the output glitch when the output clock is turned on (in this example, the D flip-flops are all triggered by clock rising edges):
(1) PD jumps from 1 to 0, after which the signal is inverted by an analog inverter to obtain a D2A_CH_EN (from 0 to 1) signal. This signal produces a ch_en_q (from 0 to 1) signal after the analog local clkp_ref clock synchronizes 1 beat, which is fed to dff_1 and dff_2 simultaneously for clock synchronization. The difference between the two clocks is that dff_1 uses clkp_ref as the synchronizing clock and dff_2 uses clkn_ref as the synchronizing clock.
(2) First, clkp_out has no glotch open: after the ch_en_q (from 0 to 1) signal is generated, the first rising edge of clkn_ref comes first. At the same time as this rising edge comes, clkp_out is still in the 0 level state. Dff_2, at this rising edge sampling of clkn_ref, produces a ch_en_drv_vop transition (from 0 to 1) slightly later than the first rising edge of clkn_ref (due to the gate delay of CLK to Q of the D flip-flop being around 1 ns). The transitions of ch_en_drv_vop (from 0 to 1) open the main signal path of clkn_drv clock, vop_up, vop_dn pass the previous stage clock signal to clkp_out, and the output drive circuit of clkp_out is opened to drive clkp_out to 0 (corresponding to the high state of clkn_ref). Almost simultaneously, en_vop_up is still 0, en_vop_dn (from 1 to 0) hops, and the strong pull control circuit of the clkp_out terminal is turned off, thus realizing the no-glotch turn-off of clkp_out.
(3) Then clkn_out's no-glove open: the first rising edge of clkp_ref (after half a period after the arrival of the first rising edge of clkn_ref) comes after the generation of the ch_en_q (from 0 to 1) signal. At the same time as this rising edge comes, clkn_out is still in the 0 level state. Dff_1, at this rising edge sampling of clkp_ref, produces a ch_en_drv_vom (from 0 to 1) transition slightly later than the first rising edge of clkp_ref (due to the gate delay of CLK to Q of the D flip-flop being around 1 ns). The transitions of ch_en_drv_vom (from 0 to 1) open the main signal path of clkp_drv clock, vom_up, vom_dn pass the previous stage clock signal to clkn_out, turn on the output drive circuit of clkn_out, and drive clkn_out to 0 (corresponding to the high state of clkp_ref). Almost simultaneously, en_vom_up is still 0, en_vom_dn (from 1 to 0) hops, and the strong pull control circuit of the clkn_out terminal is turned off, thus realizing the no-glotch turn-off of clkn_out.
Fig. 6 shows a timing diagram without the glitch output when the clock driving circuit is turned on and off, where clkp_out=0 and clkn_out=0 when the output clock is turned off.
Example 3
This example is based on examples 1 and 2:
the embodiment provides a burr eliminating method in the switching process of a differential clock driving circuit, which is specifically described as follows.
1. Sampling control mode of clock synchronization circuit
Because of the differential clock transmission, there are two clock signals clkp_ref, clkn_ref that are opposite to each other as sampling clocks for dff_1, dff_2. Dff_1, dff_2 can select either clkp_ref, clkn_ref as its synchronous sampling clock respectively, to satisfy clkp_out, clkn_out different potential application scenarios after closing. The application scenarios according to different potentials after the CLKP_OUT and the CLKN_OUT are closed are described as follows:
(1) For the scenarios with clkp_out=0 and clkn_out=0 after the output is turned off, dff_1 selects clkp_ref clock rising edge sampling generation ch_en_drv_vom to turn off or turn on clkn_out, and dff_2 selects clkn_ref clock rising edge sampling generation ch_en_drv_vop to turn off or turn on clkp_out, thereby realizing the no-glowing output turn-off and turn-on of clkp_out and clkn_out. Embodiment 2 is a detailed description taking this application scenario as an example.
(2) For the scenes of clkp_out=0 and clkn_out=1 after output is turned off, dff_1 and dff_2 select clkn_ref clock rising edge sampling generation ch_en_drv_vom and ch_en_drv_vop to turn off or turn on clkp_out and clkn_out, thereby realizing no-glowing output turn-off and turn-on of clkp_out and clkn_out. The combination logic of the strong pull control circuits of the clkn_out terminal in this application scenario is slightly different, as shown in fig. 10 and 11.
(3) For the scenarios with clkp_out=1 and clkn_out=0 after output is turned off, dff_1 and dff_2 select clkp_ref clock rising edge sampling to generate ch_en_drv_vom and ch_en_drv_vop to turn off or turn on clkp_out and clkn_out, so as to realize no-glowing output turn-off and turn-on of clkp_out and clkn_out. The combination logic of the strong pull control circuit of the clkp_out terminal in this application scenario is slightly different, as shown in fig. 12 and 13.
(4) For the scenarios with clkp_out=1 and clkn_out=1 after the output is turned off, dff_1 selects clkn_ref clock rising edge sampling generation ch_en_drv_vom to turn off or turn on clkn_out, and dff_2 selects clkp_ref clock rising edge sampling generation ch_en_drv_vop to turn off or turn on clkp_out, thereby realizing the no-glowing output turn-off and turn-on of clkp_out and clkn_out. The combination logic of the strong pull control circuits of the clkp_out and clkn_out terminals in this application scenario is slightly different, as shown in fig. 13 and 14.
2. The DFF sampling in the clock synchronization circuit may be triggered not only by rising edges but also by falling edges.
The description of the example section of this patent is a detailed description taking the application scenario triggered by the rising edge as an example. If dff_1, dff_2 are triggered by falling edges, the following is the following according to the application scenario of different potentials after clkp_out, clkn_out are closed:
(1) For the scenarios with clkp_out=0 and clkn_out=0 after the output is turned off, dff_1 selects clkn_ref clock falling edge sampling generation ch_en_drv_vom to turn off or turn on clkn_out, and dff_2 selects clkp_ref clock rising edge sampling generation ch_en_drv_vop to turn off or turn on clkp_out, thereby realizing the no-gap output turn-off and turn-on of clkp_out and clkn_out.
(2) For the scenes of clkp_out=0 and clkn_out=1 after the output is turned off, dff_1 and dff_2 select clkp_ref clock falling edge sampling generation ch_en_drv_vom and ch_en_drv_vop to turn off or turn on clkp_out and clkn_out, thereby realizing the no-glowing output turn-off and turn-on of clkp_out and clkn_out. The combination logic of the strong pull control circuit of the clkn_out terminal in this application scenario is the same as that of fig. 10.
(3) For the scenarios with clkp_out=1 and clkn_out=0 after output is turned off, dff_1 and dff_2 select clkn_ref clock rising edge sampling to generate ch_en_drv_vom and ch_en_drv_vop to turn off or turn on clkp_out and clkn_out, so as to realize no-glowing output turn-off and turn-on of clkp_out and clkn_out. The combination logic of the strong pull control circuit of the clkp_out terminal in this application scenario is the same as that of fig. 12.
(4) For the scenarios with clkp_out=1 and clkn_out=1 after the output is turned off, dff_1 selects clkp_ref clock falling edge sampling generation ch_en_drv_vom to turn off or turn on clkn_out, and dff_2 selects clkn_ref clock falling edge sampling generation ch_en_drv_vop to turn off or turn on clkp_out, thereby realizing the no-gap output turn-off and turn-on of clkp_out and clkn_out. The combination logic of the strong pull control circuits of the clkp_out and clkn_out terminals in this application scenario is the same as that of fig. 14.

Claims (10)

1. The burr eliminating method in the switching process of the differential clock driving circuit is characterized by comprising the following steps:
s1, differential input: generating clock signals CLKP_REF and CLKP_DRV with the same frequency and the same phase based on a positive differential input clock signal CLKP of a clock chip, generating clock signals CLKN_REF and CLKN_DRV with the same frequency and the same phase based on a negative differential input clock signal CLKN of the clock chip, wherein the clock signals CLKP_DRV and CLKN_DRV are mutually differential clocks and are input into a clock main signal path, and the clock signals CLKP_REF and CLKN_REF are mutually differential clocks and are input into a clock synchronous circuit as synchronous sampling clocks;
s2, clock synchronization: the clock synchronization circuit selects the rising edge or the falling edge of the clock signal CLKP_REF through one D trigger, selects the rising edge or the falling edge of the clock signal CLKN_REF through the other D trigger, and performs clock synchronization on the sampled enabling signal D2A_CH_EN at different time points so as to generate CH_EN_DRV_VOP and CH_EN_DRV_VOM signals, and controls the clock main signal path and the output stage driving circuit so that the output clock signal does not generate burr when being closed and opened;
s3, output driving: the output stage driving circuit comprises two repeating units, wherein the repeating units comprise a strong pull control circuit and an output driving circuit, and the strong pull control circuit is configured to perform strong pull-up or pull-down control on the output when an output clock is turned off so as to keep the output in a fixed potential state; the output driving circuit is configured to transfer the clock signal of the clock main signal path and to output clock signals clkp_out and clkn_out externally.
2. The glitch removal method of claim 1, in which the turning-off of the output clock signal when the turn-off control signal PD of the output stage driver circuit transitions from 0 to 1 and the D flip-flop is triggered by a clock rising edge comprises:
the turn-off control signal PD jumps from 0 to 1, a D2A_CH_EN signal is obtained through the inversion of an analog inverter, and under the clock action of CLKN_REF and CLKP_REF, CH_EN_DRV_VOP and CH_EN_DRV_VOM signals are generated through sampling of the clock synchronization circuit;
the output clock signal clkp_out is turned off without burrs: under the synchronous action of the rising edge of the CLKN_REF clock, after the CLKP_OUT enters a 0 level state, the clock main signal path part corresponding to the CLKP is closed, and then the strong pull control circuit is opened to forcedly pull down the CLKP_OUT to the 0 level state without generating burrs during the process;
the output clock signal clkn_out is turned off without burrs: under the synchronization of the rising edge of the clkp_ref clock, the ch_en_drv_vom immediately closes the clock main signal path portion corresponding to CLKN after clkn_out enters the 0 level state, and then the pull-up control circuit is turned on to forcedly pull down clkn_out to the 0 level state without generating burrs during this period.
3. The glitch removal method of claim 1, in which the step of opening the output clock signal when the off control signal PD of the output stage driver circuit transitions from 1 to 0 and the D flip-flop is triggered by a clock rising edge comprises:
the turn-off control signal PD jumps from 1 to 0, a D2A_CH_EN signal is obtained through the inversion of an analog inverter, and under the clock action of CLKN_REF and CLKP_REF, CH_EN_DRV_VOP and CH_EN_DRV_VOM signals are generated through sampling of the clock synchronization circuit;
the output clock signal clkp_out is turned on without burrs: under the synchronous action of the rising edge of the CLKN_REF clock, after the CLKP_DRV enters a 0 level state, a clock main signal path part corresponding to the CLKP is opened, the CLKP_OUT is driven to the 0 level state by the output driving circuit and no burr is generated during the clock main signal path part, and then the strong pull control circuit is closed;
the no-glove on of the output clock signal clkn_out: under the synchronization action of the rising edge of the CLKP_REF clock, after CLKN_DRV enters a 0 level state, a clock main signal path part corresponding to CLKN is opened, CLKN_OUT is driven to the 0 level state by the output driving circuit and no burr is generated during the clock main signal path part, and then the strong pull control circuit is closed.
4. A method of glitch removal during switching of a differential clock drive circuit of claim 2 or claim 3 in which the off control signal PD is sampled at least twice by a digital circuit clock synchronisation and taken out before being input to the analogue inverter.
5. The method of claim 4, wherein the digital circuit uses a positive differential input clock signal CLKP or a negative differential input clock signal CLKN as a clock source.
6. A glitch elimination circuit in the switching process of a differential clock driving circuit, which is applied to a clock chip, and is characterized by comprising:
a differential input circuit configured to generate clock signals clkp_ref and clkp_drv of the same frequency and the same phase based on a positive differential input clock signal CLKP of the clock chip, generate clock signals clkn_ref and clkn_drv of the same frequency and the same phase based on a negative differential input clock signal CLKN of the clock chip, wherein the clock signals clkp_drv and clkn_drv are differential clocks with each other and are input to the clock main signal path, and the clock signals clkp_ref and clkn_ref are differential clocks with each other and are input to the clock synchronization circuit as synchronous sampling clocks;
a clock synchronization circuit configured to select a rising edge or a falling edge of the clock signal clkp_ref by one D flip-flop, select a rising edge or a falling edge of the clock signal clkn_ref by another D flip-flop, and clock-synchronize the sampled enable signal d2a_ch_en at different time points, thereby generating ch_en_drv_vop and ch_en_drv_vom signals, and control the clock main signal path and the output stage driving circuit so that the output clock signal does not generate glitch when turned off and on;
an output stage driving circuit configured as two repeating units including a strong pull control circuit configured to perform strong pull-up or pull-down control of an output when an output clock is turned off, to keep the output in a fixed potential state; the output driving circuit is configured to transfer the clock signal of the clock main signal path and to output clock signals clkp_out and clkn_out externally.
7. The glitch removal circuit of claim 6, in which the turning-off of the output clock signal when the turn-off control signal PD of the output stage driver circuit transitions from 0 to 1 and the D flip-flop is triggered by a clock rising edge comprises:
the turn-off control signal PD jumps from 0 to 1, a D2A_CH_EN signal is obtained through the inversion of an analog inverter, and under the clock action of CLKN_REF and CLKP_REF, CH_EN_DRV_VOP and CH_EN_DRV_VOM signals are generated through sampling of the clock synchronization circuit;
the output clock signal clkp_out is turned off without burrs: under the synchronous action of the rising edge of the CLKN_REF clock, after the CLKP_OUT enters a 0 level state, the clock main signal path part corresponding to the CLKP is closed, and then the strong pull control circuit is opened to forcedly pull down the CLKP_OUT to the 0 level state without generating burrs during the process;
the output clock signal clkn_out is turned off without burrs: under the synchronization of the rising edge of the clkp_ref clock, the ch_en_drv_vom immediately closes the clock main signal path portion corresponding to CLKN after clkn_out enters the 0 level state, and then the pull-up control circuit is turned on to forcedly pull down clkn_out to the 0 level state without generating burrs during this period.
8. The glitch removal circuit of claim 6, in which the turning-off of the output clock signal when the turn-off control signal PD of the output stage driver circuit transitions from 1 to 0 and the D flip-flop is triggered by a clock rising edge comprises:
the turn-off control signal PD jumps from 1 to 0, a D2A_CH_EN signal is obtained through the inversion of an analog inverter, and under the clock action of CLKN_REF and CLKP_REF, CH_EN_DRV_VOP and CH_EN_DRV_VOM signals are generated through sampling of the clock synchronization circuit;
the output clock signal clkp_out is turned on without burrs: under the synchronous action of the rising edge of the CLKN_REF clock, after the CLKP_DRV enters a 0 level state, a clock main signal path part corresponding to the CLKP is opened, the CLKP_OUT is driven to the 0 level state by the output driving circuit and no burr is generated during the clock main signal path part, and then the strong pull control circuit is closed;
the no-glove on of the output clock signal clkn_out: under the synchronization action of the rising edge of the CLKP_REF clock, after CLKN_DRV enters a 0 level state, a clock main signal path part corresponding to CLKN is opened, CLKN_OUT is driven to the 0 level state by the output driving circuit and no burr is generated during the clock main signal path part, and then the strong pull control circuit is closed.
9. The glitch elimination circuit of claim 7 or 8, in which said off control signal PD is sampled at least twice by a digital circuit clock synchronization and then input to said analog inverter.
10. The spur cancellation circuit in a switching process of a differential clock drive circuit according to claim 9, wherein the digital circuit uses either a forward differential input clock signal CLKP or a reverse differential input clock signal CLKN as a clock source.
CN202310564254.5A 2023-05-18 2023-05-18 Burr eliminating method and circuit in switching process of differential clock driving circuit Active CN116647215B (en)

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CN115483912A (en) * 2022-10-08 2022-12-16 聆思半导体技术(苏州)有限公司 Noise suppression delay circuit
CN116015255A (en) * 2022-12-30 2023-04-25 成都电科星拓科技有限公司 Clock seamless switching circuit supporting automatic switching loss

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* Cited by examiner, † Cited by third party
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US20040056696A1 (en) * 1999-09-29 2004-03-25 Agere Systems Inc. Edge-triggered toggle flip-flop circuit
US20020174374A1 (en) * 2001-05-18 2002-11-21 Bahram Ghaderi High speed phase selector
CN101267194A (en) * 2008-04-18 2008-09-17 启攀微电子（上海）有限公司 A burr judgement and elimination circuit
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