CN116646424A - Silicon-based solar cell and preparation method thereof - Google Patents

Silicon-based solar cell and preparation method thereof Download PDF

Info

Publication number
CN116646424A
CN116646424A CN202310644740.8A CN202310644740A CN116646424A CN 116646424 A CN116646424 A CN 116646424A CN 202310644740 A CN202310644740 A CN 202310644740A CN 116646424 A CN116646424 A CN 116646424A
Authority
CN
China
Prior art keywords
layer
silicon
silicon wafer
type region
tunneling oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310644740.8A
Other languages
Chinese (zh)
Inventor
吴慧敏
陈刚
石强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhejiang Aiko Solar Energy Technology Co Ltd
Guangdong Aiko Technology Co Ltd
Tianjin Aiko Solar Energy Technology Co Ltd
Zhuhai Fushan Aixu Solar Energy Technology Co Ltd
Original Assignee
Zhejiang Aiko Solar Energy Technology Co Ltd
Guangdong Aiko Technology Co Ltd
Tianjin Aiko Solar Energy Technology Co Ltd
Zhuhai Fushan Aixu Solar Energy Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zhejiang Aiko Solar Energy Technology Co Ltd, Guangdong Aiko Technology Co Ltd, Tianjin Aiko Solar Energy Technology Co Ltd, Zhuhai Fushan Aixu Solar Energy Technology Co Ltd filed Critical Zhejiang Aiko Solar Energy Technology Co Ltd
Priority to CN202310644740.8A priority Critical patent/CN116646424A/en
Publication of CN116646424A publication Critical patent/CN116646424A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1868—Passivation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Development (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Sustainable Energy (AREA)
  • Photovoltaic Devices (AREA)

Abstract

The invention discloses a silicon-based solar cell and a preparation method thereof, and relates to the technical field of solar cells. The preparation method comprises the following steps: texturing and back polishing of the silicon wafer; forming a first tunneling oxide layer and a first amorphous silicon layer; b diffusion is carried out to convert the first amorphous silicon layer into a P+ polycrystalline silicon layer, a BSG layer is formed, and the front side B of the silicon wafer is internally expanded to form a P++ silicon layer; etching the back surface to form an N-type region; forming a second tunneling oxide layer and a second amorphous silicon layer; p diffusion converts the second amorphous silicon layer into an N+ polycrystalline silicon layer and forms a PSG layer; the N-type region and the P-type region are electrically isolated; removing a PSG layer, an N+ polycrystalline silicon layer, a second tunneling oxide layer, a BSG layer, a P+ polycrystalline silicon layer and a first tunneling oxide layer on the front surface of the silicon wafer, and reserving the P++ silicon layer; sequentially on the front and back of the silicon waferFace formation AlO x Layer, siN x A layer; forming N electrode and P electrode. The preparation method disclosed by the invention is simple in process, reduces surface recombination and improves the conversion efficiency.

Description

Silicon-based solar cell and preparation method thereof
Technical Field
The invention relates to the technical field of solar cells, in particular to a silicon-based solar cell and a preparation method thereof.
Background
The interdigital back contact (Interdigitated Back Contact, IBC) solar cell has the advantages of high conversion efficiency, no shielding on the front surface, beautiful appearance, simple and diversified package of components, and the front surface thereof generally adopts AlO x Layer and SiN x The layer passivation is still higher in the positive surface recombination, and the body recombination is also higher due to the disordered electron holes in the battery piece when the battery piece is undoped, and the surface recombination can be reduced when the front surface field FSF is formed by doping phosphorus P, but the aluminum oxide coating (with opposite charge polarity) is not facilitated, and the conventional B diffusion surface BSG and the boron-rich layer cannot be effectively removed.
Disclosure of Invention
The invention aims to solve the technical problem of providing the preparation method of the silicon-based solar cell, which has simple process, avoids the generation of a boron-rich layer dead zone, reduces the positive surface recombination and improves the conversion efficiency of the solar cell.
The invention also solves the technical problem of providing a silicon-based solar cell with high conversion efficiency.
In order to solve the technical problems, the invention provides a preparation method of a silicon-based solar cell, which comprises the following steps:
(1) Providing a silicon wafer and texturing to form a textured surface;
(2) Polishing the back surface of the silicon wafer after texturing;
(3) Forming a first tunneling oxide layer and a first amorphous silicon layer on the front surface and the back surface of the silicon wafer;
(4) Converting the first amorphous silicon layers on the front side and the back side of the silicon wafer into a P+ polycrystalline silicon layer by adopting a B diffusion process, and forming a BSG layer on the P+ polycrystalline silicon layer; in addition, the front side B of the silicon wafer is internally expanded, and a P++ silicon layer is formed on the surface of the textured surface;
(5) Etching a preset area on the back of the silicon wafer to form an N-type area, wherein the unetched area is a P-type area;
(6) Forming a second tunneling oxide layer and a second amorphous silicon layer on the front surface and the back surface of the silicon wafer obtained in the step (5);
(7) Converting the second amorphous silicon layers on the front side and the back side of the silicon wafer into an N+ polycrystalline silicon layer by adopting a P diffusion process, and forming a PSG layer on the N+ polycrystalline silicon layer; wherein the temperature of P diffusion is 50-100 ℃ lower than that of B diffusion;
(8) Laser ablates PSG layer with preset width between P type region and N type region;
(9) Removing the second tunneling oxide layer and the N+ polysilicon layer exposed on the back surface of the silicon wafer in the step (8), so that the P-type region and the N-type region are electrically isolated;
(10) Removing a PSG layer, an N+ polycrystalline silicon layer, a second tunneling oxide layer, a BSG layer, a P+ polycrystalline silicon layer and a first tunneling oxide layer on the front surface of the silicon wafer, and reserving the P++ silicon layer;
(11) AlO formation on the front and back surfaces of the silicon wafer obtained in step (10) x A layer;
(12) SiN formation on the front and back surfaces of the silicon wafer obtained in step (11) x A layer;
(13) And forming an N electrode in the N type region and forming a P electrode in the P type region.
As an improvement of the above technical solution, the step (1) includes:
(1.1) providing a silicon wafer and texturing to form a textured surface;
(1.2) treating the silicon wafer subjected to texturing by hydrogen peroxide or ozone so as to ensure that the surface of the silicon wafer has hydrophilicity.
As an improvement of the above technical scheme, in the step (3), the first tunneling oxide layer and the first amorphous silicon layer are prepared by using LPCVD, and the deposition temperature of the first amorphous silicon layer is 550-600 ℃;
in the step (6), the second tunneling oxide layer and the second amorphous silicon layer are prepared by LPCVD, and the deposition temperature of the second amorphous silicon layer is 550-600 ℃.
As an improvement of the technical scheme, in the step (4), the diffusion temperature of B is 850-1000 ℃;
in the step (7), the temperature of P diffusion is 800-900 ℃.
As an improvement of the above technical solution, the step (6) includes:
(6.1) carrying out alkali polishing on the silicon wafer obtained in the step (5) to remove laser damage of the N-type region; meanwhile, the BSG layer protects the first tunneling oxide layer and the P+ polysilicon layer on the P-type region from being damaged;
(6.2) forming a second tunneling oxide layer and a second amorphous silicon layer on the front side and the back side of the silicon wafer obtained in the step (6.1).
In the step (9), alkali polishing is adopted to remove the second tunneling oxide layer and the N+ polysilicon layer.
As an improvement of the above technical scheme, in the step (11), ALD is used to form the AlO x A layer having a thickness of 1 to 20nm;
in step (12), PECVD is used to form the SiN x The thickness of the layer is 60-110 nm.
As an improvement of the technical scheme, the doping concentration of the P++ silicon layer is 5E 18-5E 19cm -3 The P++ silicon layer and the silicon wafer form a floating junction, and the junction depth is 0.1-1 mu m.
As an improvement of the technical proposal, the thickness of the N+ polysilicon layer is 40-300 nm, and the doping concentration is 3E 19-1E 21cm -3 ；
The thickness of the P+ polysilicon layer is 40-300 nm, and the doping concentration is 5E 19-1E 21cm -3 。
Correspondingly, the invention also discloses a silicon-based solar cell, which comprises a silicon wafer, a P++ silicon layer and AlO, wherein the P++ silicon layer and the AlO are sequentially arranged on the front surface of the silicon wafer x Layer and SiN x A layer;
the silicon isThe back of the chip is provided with an N-type region and a P-type region which are arranged in a crossing way, wherein the N-type region comprises a second tunneling oxide layer, an N+ polysilicon layer and an AlO which are sequentially arranged x Layer, siN x The N electrode is connected with the N+ polycrystalline silicon layer in a conductive mode; the P-type region comprises a first tunneling oxide layer, a P+ polysilicon layer and AlO which are sequentially arranged x Layer, siN x The P electrode is connected with the P+ polycrystalline silicon layer in a conductive mode.
The implementation of the invention has the following beneficial effects:
according to the preparation method of the silicon-based solar cell, the first tunneling passivation layer and the first amorphous silicon layer are formed on the front surface and the back surface of the silicon wafer at the same time, and then the P+ polycrystalline silicon layer is formed through the B diffusion process. In the process of B diffusion, the front B diffusion enters the silicon wafer substrate to form a P++ silicon layer, so that the front surface recombination is effectively reduced. In addition, the P++ silicon layer and the silicon wafer substrate form a floating PN junction (namely FFE), the electronic barrier height at one side of the N region of the front surface P++/N is reduced due to the built-in electric field effect of the PN junction, and a pumping effect peculiar to FFE is formed, so that the body recombination is reduced, and the open-circuit voltage of the battery piece is improved. Furthermore, based on the preparation method, a separate boron diffusion process is not needed, so that the dead zone of a boron-rich layer in boron diffusion is reduced, the positive surface recombination is reduced, and the open-circuit voltage of the battery piece is further improved.
Drawings
FIG. 1 is a flow chart of a method of fabricating a silicon-based solar cell of the present invention;
FIG. 2 is a schematic structural diagram of a silicon wafer after step S3;
FIG. 3 is a schematic structural diagram of a silicon wafer after step S4;
FIG. 4 is a schematic structural diagram of a silicon wafer after step S5;
FIG. 5 is a schematic structural diagram of a silicon wafer after step S6;
FIG. 6 is a schematic structural diagram of a silicon wafer after step S7;
FIG. 7 is a schematic structural diagram of a silicon wafer after step S9;
FIG. 8 is a schematic structural diagram of a silicon wafer after step S10;
FIG. 9 is a schematic structural diagram of a silicon wafer after step S12;
fig. 10 is a schematic structural diagram of a silicon-based solar cell according to an embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings, for the purpose of making the objects, technical solutions and advantages of the present invention more apparent. It is only stated that the terms of orientation such as up, down, left, right, front, back, inner, outer, etc. used in this document or the imminent present invention, are used only with reference to the drawings of the present invention, and are not meant to be limiting in any way.
Referring to fig. 1, the invention provides a method for preparing a silicon-based solar cell, which comprises the following steps:
s1: providing a silicon wafer 1 and texturing to form a textured surface;
specifically, the silicon wafer 1 is an N-type silicon wafer having a thickness of 50 to 250 μm, and exemplary ones thereof are 60 μm, 80 μm, 100 μm, 150 μm, 180 μm, 220 μm or 240 μm, but are not limited thereto.
Specifically, the texturing process is a common procedure in the field, and a pyramid light trapping structure can be formed on the surface of the silicon wafer through texturing, so that the light conversion efficiency is improved.
Preferably, in one embodiment of the present invention, after the texturing is completed, the silicon wafer 1 is treated with hydrogen peroxide or deionized water containing ozone, so as to make the surface of the silicon wafer hydrophilic.
S2: polishing the back of the textured silicon wafer 1;
specifically, the back surface of the silicon wafer is polished by an acid polishing or alkali polishing process to form a surface with the reflectivity of 20-40%. Specifically, the acid polishing process may be, but not limited to, polishing with a mixed solution of hydrofluoric acid, nitric acid, and sulfuric acid, or with a mixed solution of hydrofluoric acid and nitric acid. The alkali polishing may be polishing with NaOH solution or KOH solution, but is not limited thereto.
S3: forming a first tunneling oxide layer 2 and a first amorphous silicon layer 3a on the front surface and the back surface of the silicon wafer 1;
specifically, the method can be carried out by a thermal nitric acid oxidation method, an ultraviolet ozone oxidation method, PECVD-N 2 The first tunneling oxide layer 2 is prepared by an O method, an ozone oxidation method, and an LPCVD method, but is not limited thereto. Preferably, in one embodiment of the present invention, the first tunnel oxide layer 2 is prepared by LPCVD.
Specifically, the first amorphous silicon layer 3a may be formed by a PECVD method or an LPCVD method, but is not limited thereto. Preferably, in one embodiment of the present invention, the first amorphous silicon layer 3a is formed by an LPCVD method, and its deposition temperature is 550 to 600 ℃, illustratively 560 ℃, 570 ℃, 580 ℃, or 590 ℃, but is not limited thereto. Referring to fig. 2, the first amorphous silicon layer 3a has a thickness of 40 to 300nm, and exemplary is 55nm, 80nm, 120nm, 180nm, 230nm, 250nm, or 280nm, but is not limited thereto.
S4: converting the first amorphous silicon layer 3a into a p+ polysilicon layer 3 by using a B diffusion process, and forming a BSG layer 3B thereon; expanding the front side B of the silicon wafer 1 to form a P++ silicon layer 11;
wherein the temperature of B diffusion is 850-1000 ℃, and is exemplified by but not limited to 880 ℃, 920 ℃, 950 ℃ or 970 ℃. The first amorphous silicon layer 3a on the front and back sides of the silicon wafer 1 can be converted into a p+ polysilicon layer 3 by a B diffusion process, and a BSG layer 3B is formed on the p+ polysilicon layer 3. Then, based on the B diffusion process, B on the front surface of the silicon wafer 1 is internally diffused, and a p++ silicon layer 11 is formed on the textured surface (see fig. 3). Based on the process, a separate boron diffusion process is not needed, the dead zone of a boron-rich layer in boron diffusion is reduced, the positive surface recombination is reduced, and the open circuit voltage of the battery piece is further improved.
Specifically, the doping concentration of the P+ polysilicon layer 3 is 5E 19-1E 21cm -3 Exemplary is 7E19cm -3 、9E19cm -3 、2E20cm -3 、4E20cm -3 、6E20cm -3 Or 8E20cm -3 But is not limited thereto.
Specifically, the doping concentration of the P++ silicon layer 11 is 5E 18-5E 19cm -3 Exemplary is 7E18cm -3 、9E18cm -3 、1E19cm -3 、2E19cm -3 Or 4E19cm -3 But is not limited thereto. The P++ silicon layer 11 forms a floating junction (FFE) with the silicon wafer 1 (N-type silicon wafer) having a junction depth of 0.1 to 1 μm, and is exemplified by 0.3 μm, 0.5 μm, 0.7 μm or 0.9. Mu.mm, but is not limited thereto.
S5: etching a preset area on the back of the silicon wafer to form an N-type area;
the first tunneling oxide layer 2 and the P+ polysilicon layer 3 on the back surface of the silicon wafer can be etched by photoetching or laser ablation to form an N-type region, and the region which is not etched is a P-type region; the P-type regions and the N-type regions are alternately arranged (refer to fig. 4).
Preferably, in one embodiment of the present invention, the N-type region is formed by laser ablating the first tunnel oxide layer 2 and the p+ polysilicon layer 3 on the back side of the silicon wafer and partially ablating the wafer.
S6: forming a second tunneling oxide layer 4 and a second amorphous silicon layer 5a on the front surface and the back surface of the silicon wafer obtained in the step S5;
specifically, the method can be carried out by a thermal nitric acid oxidation method, an ultraviolet ozone oxidation method, PECVD-N 2 The second tunnel oxide layer 4 is prepared by an O method, an ozone oxidation method, an LPCVD method, but is not limited thereto. Preferably, in one embodiment of the present invention, the second tunnel oxide layer 4 is prepared by LPCVD.
Specifically, the second amorphous silicon layer 5a (see fig. 5) may be formed by a PECVD method or an LPCVD method, but is not limited thereto. Preferably, in one embodiment of the present invention, the second amorphous silicon layer 5a is formed by an LPCVD method, and its deposition temperature is 550 to 600 ℃, illustratively 560 ℃, 570 ℃, 580 ℃ or 590 ℃, but is not limited thereto. The thickness of the second amorphous silicon layer 5a is 40 to 300nm, and exemplary is 55nm, 80nm, 120nm, 180nm, 230nm, 250nm, or 280nm, but is not limited thereto.
Preferably, in one embodiment of the present invention, step S6 includes:
s61: performing alkali polishing on the silicon wafer obtained in the step S5 to remove laser damage of the N-type region; meanwhile, the BSG layer protects the first tunneling oxide layer 2 and the P+ polysilicon layer 3 on the P-type region from being damaged;
specifically, the alkali polishing may be performed using a KOH solution or a NaOH solution, but is not limited thereto.
S62: the second tunneling oxide layer 4 and the second amorphous silicon layer 5a are formed on the front surface and the back surface of the silicon wafer obtained in step S61.
S7: converting the second amorphous silicon layer 5a into an n+ polysilicon layer 5 by using a P diffusion process, and forming a PSG layer 5b thereon;
wherein the temperature of P diffusion is 50 to 100 ℃ lower than the temperature of B diffusion, and based on this control, the first amorphous silicon layer 2 and the p+ polysilicon layer 3 can be substantially not damaged. Specifically, the temperature of P diffusion is 800 to 900 ℃, and exemplary is 820 ℃, 840 ℃, 860 ℃, 880 ℃, or 890 ℃, but is not limited thereto. The second amorphous silicon layer 5a on the front and back sides of the silicon wafer may be converted into an n+ polysilicon layer 5 by a P diffusion process, and a PSG layer 5b may be formed on the n+ polysilicon layer 5 (refer to fig. 6).
Specifically, the doping concentration of the N+ polysilicon layer 5 is 3E 19-1E 21cm -3 Exemplary is 5E19cm -3 、7E19cm -3 、9E19cm -3 、2E20cm -3 、4E20cm -3 、6E20cm -3 Or 8E20cm -3 But is not limited thereto.
S8: laser ablates PSG layer with preset width between P type region and N type region;
specifically, removing the PSG layer 5b on the surface of the P-type region by laser ablation can provide a good basis for subsequently removing the second tunneling oxide layer 4 and the n+ polysilicon layer 5 on the P-type region. By removing the PSG layer 5b with a preset width between the P-type region and the N-type region, a good foundation can be provided for the electric isolation of the P-type region and the N-type region.
Specifically, the preset width is 100 to 3000nm, and exemplary is 300nm, 800nm, 1300nm, 1700nm, 2200nm, 2600nm or 2800nm, but is not limited thereto.
S9: removing the second tunneling oxide layer and the N+ polysilicon layer exposed on the back surface of the silicon wafer;
the second tunneling oxide layer 4 and the n+ polysilicon layer 5 may be removed by a laser ablation and alkali polishing process, but not limited thereto. Preferably, in one embodiment of the present invention, the second tunneling oxide layer 4 and the n+ polysilicon layer 5 are removed by alkali polishing under such a condition that a KOH solution containing TMAH (2 to 5 wt%) is used for polishing at 50 to 70 ℃ for 1.5 to 3 minutes.
It should be noted that, the first tunneling oxide layer 2 and the p+ polysilicon layer 3 in the P-type region are protected by the BSG layer 3b, and are not removed during the alkaline polishing process. Accordingly, the second tunneling oxide layer 4 and the n+ polysilicon layer 5 of the N-type region are not removed during the alkali polishing process due to the protection of the PSG layer 5b (refer to fig. 7).
S10: removing the PSG layer, the N+ polysilicon layer, the second tunneling oxide layer, the BSG layer, the P+ polysilicon layer and the first tunneling oxide layer on the front surface of the silicon wafer, and reserving the P++ silicon layer;
specifically, the PSG layer 5b, the n+ polysilicon layer 5, the second tunneling oxide layer 4, the BSG layer 3b, the p+ polysilicon layer 3 and the first tunneling oxide layer 2 on the front surface of the silicon wafer 1 may be removed by a laser ablation and alkali polishing process, but not limited thereto.
Preferably, in one embodiment of the present invention, the PSG layer 5b, the n+ polysilicon layer 5, the second tunnel oxide layer 4, the BSG layer 3b, the p+ polysilicon layer 3 and the first tunnel oxide layer 2 on the front side of the silicon wafer 1 are removed by a chain polishing process. The method specifically comprises the following steps: HF and HNO are firstly adopted 3 、H 2 Polishing the mixed solution of O (the mass ratio of the mixed solution to the mixed solution is 1:1-2:1-2) at 50-80 ℃ for 1-3 min, removing the PSG layer 5b, and then polishing the mixed solution of O for 1.5-3 min at 50-70 ℃ by adopting KOH solution containing TMAH (2-5 wt%) to remove the N+ polysilicon layer 5 and the second tunneling oxide layer. Then HF and HNO are adopted 3 、H 2 The mixed solution of O (the mass ratio of the mixed solution to the mixed solution is 1:1-2:1-2) is polished at 50-80 ℃ for 1-3 min, the BSG layer 5b is removed, then a KOH solution containing TMAH (2-5 wt%) is adopted for polishing at 50-70 ℃ for 1.5-3 min, and the P+ polysilicon layer 3 and the first tunneling oxide layer 2 are removed (refer to figure 8).
S11: alO formation on the front and back surfaces of the silicon wafer obtained in step S10 x Layer 6;
specifically, the AlO can be formed by PECVD, ALD, MOCVD x Layer 6, but is not limited thereto. Preferably, in one embodiment of the invention, ALD is used to form AlO x Layer 6, which has a thickness of 1 to 20nm, is exemplified by, but not limited to, 4nm, 8nm, 10nm, 13nm, 16nm, or 18 nm.
S12: siN formation on the front and back surfaces of the silicon wafer obtained in step S11 x Layer 7;
specifically, PECVD may be usedMethod, ALD method, MOCVD method for forming SiN x Layer 7 (see fig. 9), but is not limited thereto. Preferably, in one embodiment of the invention, ALD is used to form SiN x Layer 7, which has a thickness of 60 to 110nm, is exemplified by 66nm, 72nm, 80nm, 88nm, 96nm, 103nm or 108nm, but is not limited thereto.
S13: forming an N electrode 8 in the N type region and forming a P electrode 9 in the P type region;
specifically, the N electrode 8 may be an Al electrode, but is not limited thereto. The P electrode 9 may be an Ag electrode, a Cu electrode, a Ni electrode, or a composite of several metals, but is not limited thereto.
Specifically, the N electrode or the P electrode may be formed using an electroplating or screen printing process, but is not limited thereto.
Specifically, in one embodiment of the present invention, a burn-through paste may be used to burn through SiN x Layer 7 and AlO x Layer 6, so that N electrode 8 and n+ polysilicon layer 5 are conductively connected, and P electrode 9 and p+ polysilicon layer 3 are conductively connected. In another embodiment of the present invention, laser ablation of partial regions of SiN may be employed x Layer 7 and AlO x Layer 6, then N electrode 8 and P electrode 9 are formed.
Correspondingly, referring to FIG. 9, the invention also provides a silicon-based solar cell which is prepared by the preparation method and comprises a silicon wafer 1, a P++ silicon layer 11 and AlO sequentially arranged on the front surface of the silicon wafer 1 x Layer 6 and SiN x Layer 7;
the back of the silicon wafer 1 is provided with an N-type region and a P-type region which are arranged in a crossing way, wherein the N-type region comprises a second tunneling oxide layer 4, an N+ polysilicon layer 5 and an AlO which are sequentially arranged x Layer 6, siN x The layer 7 and the N electrode 8, the N electrode 8 is connected with the N+ polysilicon layer 5 in a conductive way; the P-type region comprises a first tunneling oxide layer 2, a P+ polysilicon layer 3 and AlO which are sequentially arranged x Layer 6, siN x Layer 7 and P electrode 9,P electrode 9 are conductively connected to p+ polysilicon layer 3.
Based on the preparation process, the conversion efficiency of the silicon-based solar cell can reach 23.7-24.1%, and the conventional PERC cell is only 21-22%.
The above disclosure is only a preferred embodiment of the present invention, and it is needless to say that the scope of the invention is not limited thereto, and therefore, the equivalent changes according to the claims of the present invention still fall within the scope of the present invention.

Claims (10)

1. The preparation method of the silicon-based solar cell is characterized by comprising the following steps of:
(1) Providing a silicon wafer and texturing to form a textured surface;
(2) Polishing the back surface of the silicon wafer after texturing;
(3) Forming a first tunneling oxide layer and a first amorphous silicon layer on the front surface and the back surface of the silicon wafer;
(4) Converting the first amorphous silicon layers on the front side and the back side of the silicon wafer into a P+ polycrystalline silicon layer by adopting a B diffusion process, and forming a BSG layer on the P+ polycrystalline silicon layer; in addition, the front side B of the silicon wafer is internally expanded, and a P++ silicon layer is formed on the surface of the textured surface;
(5) Etching a preset area on the back of the silicon wafer to form an N-type area, wherein the unetched area is a P-type area;
(6) Forming a second tunneling oxide layer and a second amorphous silicon layer on the front surface and the back surface of the silicon wafer obtained in the step (5);
(7) Converting the second amorphous silicon layers on the front side and the back side of the silicon wafer into an N+ polycrystalline silicon layer by adopting a P diffusion process, and forming a PSG layer on the N+ polycrystalline silicon layer; wherein the temperature of P diffusion is 50-100 ℃ lower than that of B diffusion;
(8) Laser ablates PSG layer with preset width between P type region and N type region;
(9) Removing the second tunneling oxide layer and the N+ polysilicon layer exposed on the back surface of the silicon wafer in the step (8), so that the P-type region and the N-type region are electrically isolated;
(10) Removing a PSG layer, an N+ polycrystalline silicon layer, a second tunneling oxide layer, a BSG layer, a P+ polycrystalline silicon layer and a first tunneling oxide layer on the front surface of the silicon wafer, and reserving the P++ silicon layer;
(11) AlO formation on the front and back surfaces of the silicon wafer obtained in step (10) x A layer;
(12) SiN formation on the front and back surfaces of the silicon wafer obtained in step (11) x A layer;
(13) And forming an N electrode in the N type region and forming a P electrode in the P type region.
2. The method of fabricating a silicon-based solar cell according to claim 1, wherein step (1) comprises:
(1.1) providing a silicon wafer and texturing to form a textured surface;
(1.2) treating the silicon wafer subjected to texturing by hydrogen peroxide or ozone so as to ensure that the surface of the silicon wafer has hydrophilicity.
3. The method of fabricating a silicon-based solar cell according to claim 1, wherein in the step (3), the first tunneling oxide layer and the first amorphous silicon layer are fabricated by LPCVD, and the deposition temperature of the first amorphous silicon layer is 550 to 600 ℃;
in the step (6), the second tunneling oxide layer and the second amorphous silicon layer are prepared by LPCVD, and the deposition temperature of the second amorphous silicon layer is 550-600 ℃.
4. The method of manufacturing a silicon-based solar cell according to claim 1, wherein in step (4), the temperature of B diffusion is 850 to 1000 ℃;
in the step (7), the temperature of P diffusion is 800-900 ℃.
5. The method of fabricating a silicon-based solar cell according to claim 1, wherein step (6) comprises:
(6.1) carrying out alkali polishing on the silicon wafer obtained in the step (5) to remove laser damage of the N-type region; meanwhile, the BSG layer protects the first tunneling oxide layer and the P+ polysilicon layer on the P-type region from being damaged;
(6.2) forming a second tunneling oxide layer and a second amorphous silicon layer on the front side and the back side of the silicon wafer obtained in the step (6.1).
6. The method of fabricating a silicon-based solar cell according to claim 1, wherein in step (9), the second tunnel oxide layer and the n+ polysilicon layer are removed by alkali polishing.
7. The method of fabricating a silicon-based solar cell according to claim 1, wherein in step (11), ALD is used to form the AlO x A layer having a thickness of 1 to 20nm;
in step (12), PECVD is used to form the SiN x The thickness of the layer is 60-110 nm.
8. The method for manufacturing a silicon-based solar cell according to claim 1, wherein the doping concentration of the P++ silicon layer is 5E 18-5E 19cm -3 The P++ silicon layer and the silicon wafer form a floating junction, and the junction depth is 0.1-1 mu m.
9. The method for manufacturing a silicon-based solar cell according to claim 1, wherein the thickness of the n+ polysilicon layer is 40-300 nm, and the doping concentration is 3E 19-1E 21cm -3 ；
The thickness of the P+ polysilicon layer is 40-300 nm, and the doping concentration is 5E 19-1E 21cm -3 。
10. A silicon-based solar cell is characterized by comprising a silicon wafer, a P++ silicon layer and AlO, wherein the P++ silicon layer and the AlO are sequentially arranged on the front surface of the silicon wafer x Layer and SiN x A layer;
the back of the silicon chip is provided with an N-type region and a P-type region which are arranged in a crossing way, wherein the N-type region comprises a second tunneling oxide layer, an N+ polysilicon layer and an AlO which are sequentially arranged x Layer, siN x The N electrode is connected with the N+ polycrystalline silicon layer in a conductive mode; the P-type region comprises a first tunneling oxide layer, a P+ polysilicon layer and AlO which are sequentially arranged x Layer, siN x The P electrode is connected with the P+ polycrystalline silicon layer in a conductive mode.
CN202310644740.8A 2023-06-01 2023-06-01 Silicon-based solar cell and preparation method thereof Pending CN116646424A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310644740.8A CN116646424A (en) 2023-06-01 2023-06-01 Silicon-based solar cell and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310644740.8A CN116646424A (en) 2023-06-01 2023-06-01 Silicon-based solar cell and preparation method thereof

Publications (1)

Publication Number Publication Date
CN116646424A true CN116646424A (en) 2023-08-25

Family

ID=87615112

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310644740.8A Pending CN116646424A (en) 2023-06-01 2023-06-01 Silicon-based solar cell and preparation method thereof

Country Status (1)

Country Link
CN (1) CN116646424A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117497645A (en) * 2024-01-03 2024-02-02 淮安捷泰新能源科技有限公司 Preparation method of TBC solar cell, TBC solar cell and photovoltaic system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117497645A (en) * 2024-01-03 2024-02-02 淮安捷泰新能源科技有限公司 Preparation method of TBC solar cell, TBC solar cell and photovoltaic system
CN117497645B (en) * 2024-01-03 2024-03-26 淮安捷泰新能源科技有限公司 Preparation method of TBC solar cell, TBC solar cell and photovoltaic system

Similar Documents

Publication Publication Date Title
CN110518088B (en) Preparation method of SE solar cell
TWI669830B (en) Method for manufacturing local back contact solar cell
CN109346536B (en) Contact passivation crystalline silicon solar cell structure and preparation method
WO2008065918A1 (en) Solar cell and method for manufacturing the same
CN102986042A (en) Method for producing a photovoltaic solar cell
CN110890432A (en) Efficient polycrystalline silicon solar cell and preparation method thereof
CN114005908A (en) Solar cell and preparation method thereof
CN109545880A (en) A kind of monocrystalline silicon base class inverted pyramid suede structure back passivating solar battery and preparation method thereof
CN116646424A (en) Silicon-based solar cell and preparation method thereof
CN114792743A (en) Solar cell, preparation method thereof and photovoltaic system
CN111816714A (en) Laser boron-doped back-passivated solar cell and preparation method thereof
CN111599895A (en) Preparation method of crystalline silicon solar passivated contact cell
CN116525697A (en) Back contact type solar cell and preparation method thereof
CN116469952A (en) Solar cell and manufacturing method thereof
TWI401810B (en) Solar cell
CN116741877A (en) TBC battery preparation method and TBC battery
CN117153953A (en) Preparation method of split-film type double-sided TOPCON battery
CN116632113A (en) P-type IBC battery and preparation method thereof
CN111446331A (en) Method for removing plating and method for preparing passivated contact solar cell
CN115084314A (en) IBC solar cell preparation method of TOPCon passivation contact structure
CN114050105A (en) TopCon battery preparation method
CN114220882A (en) Preparation method of solar crystalline silicon cell and solar crystalline silicon cell
CN106158996A (en) A kind of monocrystalline silicon-based nano inverted pyramid structure back of the body passivating solar battery and preparation method thereof
CN115176345A (en) Solar cell laminated passivation structure and preparation method thereof
TWI650872B (en) Solar cell and its manufacturing method, solar cell module and solar cell power generation system

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination