CN116632113A - P-type IBC battery and preparation method thereof - Google Patents
P-type IBC battery and preparation method thereof Download PDFInfo
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- CN116632113A CN116632113A CN202310642771.XA CN202310642771A CN116632113A CN 116632113 A CN116632113 A CN 116632113A CN 202310642771 A CN202310642771 A CN 202310642771A CN 116632113 A CN116632113 A CN 116632113A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 116
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 116
- 239000010703 silicon Substances 0.000 claims abstract description 116
- 230000005641 tunneling Effects 0.000 claims abstract description 48
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims abstract description 33
- 238000005498 polishing Methods 0.000 claims abstract description 17
- 229920005591 polysilicon Polymers 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 12
- 239000003513 alkali Substances 0.000 claims description 11
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 7
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000007667 floating Methods 0.000 claims description 4
- 238000010329 laser etching Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 238000005215 recombination Methods 0.000 abstract description 9
- 230000006798 recombination Effects 0.000 abstract description 9
- 238000006243 chemical reaction Methods 0.000 abstract description 6
- 239000000243 solution Substances 0.000 description 11
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 8
- 229910052796 boron Inorganic materials 0.000 description 8
- 239000011259 mixed solution Substances 0.000 description 7
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 3
- 238000000608 laser ablation Methods 0.000 description 3
- 229910017604 nitric acid Inorganic materials 0.000 description 3
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- 229910017107 AlOx Inorganic materials 0.000 description 1
- 101001073212 Arabidopsis thaliana Peroxidase 33 Proteins 0.000 description 1
- 101001123325 Homo sapiens Peroxisome proliferator-activated receptor gamma coactivator 1-beta Proteins 0.000 description 1
- 102100028961 Peroxisome proliferator-activated receptor gamma coactivator 1-beta Human genes 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
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- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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Abstract
The invention discloses a P-type IBC battery and a preparation method thereof, and relates to the technical field of solar batteries. The preparation method comprises the steps of silicon wafer texturing, back polishing, and forming a first oxide tunneling layer, a P-type amorphous silicon layer and a first mask layer on the front surface; forming a second oxide tunneling layer, an N-type amorphous silicon layer and a second mask layer on the back surface; high-temperature treatment is carried out to obtain a P-type polycrystalline silicon layer and an N-type polycrystalline silicon layer; and the doping elements in the P-type amorphous silicon layer are expanded into the silicon wafer to form a heavily doped P-type silicon layer; back etching to form a P-type region; removing the first mask layer, the P-type polysilicon layer, the first oxide tunneling layer and the second mask layer, and reserving the heavily doped P-type silicon layerThe method comprises the steps of carrying out a first treatment on the surface of the Sequentially forming AlO on the front surface and the back surface of the silicon wafer x Layer, siN x A layer; then forming N electrode in the N type region and forming P electrode in the P type region. The preparation method disclosed by the invention is simple in process, reduces surface recombination and improves the conversion efficiency.
Description
Technical Field
The invention relates to the technical field of solar cells, in particular to a P-type IBC cell and a preparation method thereof.
Background
The interdigital back contact (Interdigitated Back Contact, IBC) solar cell has the advantages of high conversion efficiency, no shielding on the front surface, attractive appearance and simple and diversified component packaging, the front surface is generally passivated by adopting an AlOx layer and a SiNx layer, but the front surface recombination is still higher, the body recombination is also higher due to disordered electron holes in the cell when the cell is undoped, the surface recombination can be reduced when the front surface field FSF is formed by doping phosphorus P, but the aluminum oxide coating (with opposite charge polarity) is not facilitated, and the conventional B diffusion surface BSG and the boron-rich layer cannot be effectively removed.
Disclosure of Invention
The technical problem to be solved by the invention is to provide the preparation method of the P-type IBC battery, which has simple process, avoids the generation of the dead zone of the boron-rich layer, reduces the positive surface recombination and improves the conversion efficiency of the solar battery.
The invention also solves the technical problem of providing a preparation method of a P-type IBC battery, which comprises the following steps:
(1) Providing a silicon wafer and texturing to form a textured surface;
(2) Polishing the back surface of the silicon wafer after texturing;
(3) Forming a first oxide tunneling layer, a P-type amorphous silicon layer and a first mask layer on the front surface of the silicon wafer;
(4) Forming a second oxide tunneling layer, an N-type amorphous silicon layer and a second mask layer on the back surface of the silicon wafer;
(5) Performing high-temperature treatment on the silicon wafer obtained in the step (4) to convert the P-type amorphous silicon layer into a P-type polycrystalline silicon layer, and converting the N-type amorphous silicon layer into an N-type polycrystalline silicon layer; and the doping elements in the P-type amorphous silicon layer are expanded into the silicon wafer to form a heavily doped P-type silicon layer;
(6) Etching a preset area on the back of the silicon wafer to form a P-type area, wherein the area which is not etched is an N-type area;
(7) Removing the first mask layer, the P-type polycrystalline silicon layer and the first oxide tunneling layer on the front surface of the silicon wafer, and reserving the heavily doped P-type silicon layer; removing the second mask layer on the back of the silicon wafer;
(8) AlO formation on the front and back surfaces of the silicon wafer obtained in step (7) x A layer;
(9) SiN formation on the front and back surfaces of the silicon wafer obtained in step (8) x A layer;
(10) And forming an N electrode in the N type region and forming a P electrode in the P type region.
As an improvement of the above technical solution, in the step (3), a PECVD is adopted to prepare the first oxide tunneling layer, the P-type amorphous silicon layer and the first mask layer;
the first oxide tunneling layer is a silicon oxide layer or a silicon oxynitride layer, and the thickness of the first oxide tunneling layer is 0.5-5 nm;
the thickness of the P-type amorphous silicon layer is 40-300 nm;
the first mask layer is a silicon oxide layer, and the thickness of the first mask layer is 5-100 nm.
In step (4), the second oxide tunneling layer, the N-type amorphous silicon layer and the second mask layer are prepared by PECVD.
The second oxide tunneling layer is a silicon oxide layer or a silicon oxynitride layer, and the thickness of the second oxide tunneling layer is 0.5-5 nm;
the thickness of the N-type amorphous silicon layer is 40-300 nm;
the second mask layer is a silicon oxide layer, and the thickness of the second mask layer is 5-100 nm.
As a means ofThe doping concentration of the N-type polycrystalline silicon layer is 3E 19-1E 21cm -3 ；
The doping concentration of the heavily doped P-type silicon layer is 5E 18-5E 19cm -3 The heavily doped P-type silicon layer and the silicon wafer form a floating junction, and the junction depth is 0.1-1 mu m.
As an improvement of the above technical solution, the step (1) includes:
(1.1) providing a silicon wafer and texturing to form a textured surface;
(1.2) treating the silicon wafer subjected to texturing by hydrogen peroxide or ozone so as to ensure that the surface of the silicon wafer has hydrophilicity.
As an improvement of the technical scheme, in the step (3), the temperature of the high-temperature treatment is 800-900 ℃.
As an improvement of the above technical solution, the step (6) includes:
(6.1) carrying out laser etching on the silicon wafer obtained in the step (5) to form an N-type region and a P-type region;
(6.2) carrying out alkali polishing on the silicon wafer obtained in the step (6.1) to remove laser damage of the P-type region; and simultaneously, the second mask layer protects the second oxide tunneling layer and the N-type polycrystalline silicon layer on the N-type region from being damaged.
In step (6), the first mask layer, the P-type polysilicon layer, the first oxide tunneling layer and the second mask layer on the back of the silicon wafer are removed by alkali polishing.
As an improvement of the above technical solution, in step (8), ALD is used to form the AlO x A layer having a thickness of 1 to 20nm;
in step (9), PECVD is used to form the SiN x The thickness of the layer is 60-110 nm.
Correspondingly, the invention also discloses a P-type IBC battery, which comprises a silicon wafer, a heavily doped P-type silicon layer and AlO sequentially arranged on the front surface of the silicon wafer x Layer and SiN x A layer;
the back of the silicon chip is provided with an N-type region and a P-type region which are arranged in a crossing way, and the P-type region comprises AlO which are arranged in sequence x Layer, siN x The layer and the P electrode are connected with the silicon chip in a conductive way; the saidThe N-type region comprises a second oxide tunneling layer, an N-type polysilicon layer and AlO which are sequentially arranged x Layer, siN x The N electrode is connected with the N-type polycrystalline silicon layer in a conductive mode.
The implementation of the invention has the following beneficial effects:
according to the preparation method of the P-type IBC battery, the first oxide tunneling layer, the P-type amorphous silicon layer and the first mask layer are formed on the front surface of the silicon wafer, and then the P-type doping elements in the P-type amorphous silicon layer are pushed to the silicon wafer substrate through a later-stage high-temperature treatment process, the heavily doped P-type layer is formed on the surface of the silicon wafer, and the front surface recombination is effectively reduced. In addition, the heavily doped P-type silicon layer and the silicon wafer substrate form a floating P+/P structure (namely FFE), the pumping effect special for FFE reduces the body recombination and improves the open-circuit voltage of the battery piece. Furthermore, based on the preparation method, a separate boron diffusion process is not needed, so that the dead zone of a boron-rich layer in boron diffusion is reduced, the positive surface recombination is reduced, and the open-circuit voltage of the battery piece is further improved.
Drawings
FIG. 1 is a flow chart of a method of making a P-type IBC battery of the present invention;
FIG. 2 is a schematic structural diagram of a silicon wafer after step S3;
FIG. 3 is a schematic structural diagram of a silicon wafer after step S4;
FIG. 4 is a schematic structural diagram of a silicon wafer after step S6;
FIG. 5 is a schematic structural diagram of a silicon wafer after step S7;
FIG. 6 is a schematic structural diagram of a silicon wafer after step S9;
fig. 7 is a schematic diagram of a P-type IBC cell according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings, for the purpose of making the objects, technical solutions and advantages of the present invention more apparent. It is only stated that the terms of orientation such as up, down, left, right, front, back, inner, outer, etc. used in this document or the imminent present invention, are used only with reference to the drawings of the present invention, and are not meant to be limiting in any way.
Referring to fig. 1, the invention provides a preparation method of a P-type IBC battery, comprising the following steps:
s1: providing a silicon wafer 1 and texturing to form a textured surface;
specifically, the silicon wafer 1 is a P-type silicon wafer having a thickness of 50 to 250 μm, and exemplary ones thereof are 60 μm, 80 μm, 100 μm, 150 μm, 180 μm, 220 μm or 240 μm, but are not limited thereto.
Specifically, the texturing process is a common procedure in the field, and a pyramid light trapping structure can be formed on the surface of the silicon wafer through texturing, so that the light conversion efficiency is improved.
Preferably, in one embodiment of the present invention, after the texturing is completed, the silicon wafer is treated with hydrogen peroxide or deionized water containing ozone, so as to make the surface of the silicon wafer hydrophilic.
S2: polishing the back of the textured silicon wafer 1;
specifically, the back surface of the silicon wafer 1 is polished by an acid polishing or alkali polishing process to form a surface with a reflectivity of 20-40%.
Specifically, the acid polishing may be a mixed solution of nitric acid and sulfuric acid, but is not limited thereto. The alkali polishing may be NaOH solution or KOH solution, but is not limited thereto.
S3: forming a first oxide tunneling layer 2, a P-type amorphous silicon layer 3a and a first mask layer 3b on the front surface of a silicon wafer;
specifically, the method can be carried out by a thermal nitric acid oxidation method, an ultraviolet ozone oxidation method, PECVD-N 2 The first oxide tunneling layer is prepared by an O method, an ozone oxidation method, and an LPCVD method, but is not limited thereto. Preferably, in one embodiment of the present invention, the first oxide tunneling layer 2 is prepared by PECVD (refer to fig. 2).
The first tunneling oxide layer 2 is a silicon oxide layer or a silicon oxynitride layer, but is not limited thereto. Preferably a silicon oxynitride layer. The thickness of the first tunneling oxide layer 2 is 0.5 to 5nm, and is exemplified by 1nm, 2nm, 3nm, or 4nm, but is not limited thereto.
Specifically, the P-type amorphous silicon layer 3a and the first mask layer 3b may be formed by a PECVD method or an LPCVD method, but is not limited thereto. Preferably, in one embodiment of the present invention, the P-type amorphous silicon layer 3a and the first mask layer 3b are formed by a PECVD method.
Among them, the thickness of the P-type amorphous silicon layer 3a is 40 to 300nm, and exemplary is 55nm, 80nm, 120nm, 180nm, 230nm, 250nm or 280nm, but not limited thereto.
The first mask layer 3b is a silicon oxide layer, but is not limited thereto. The thickness of the first mask layer 3b is 5 to 100nm, and is exemplified by 15nm, 30nm, 45nm, 60nm, 75nm, or 90nm, but is not limited thereto.
S4: forming a second oxide tunneling layer 4, an N-type amorphous silicon layer 5a and a second mask layer 5b on the back surface of the silicon wafer;
specifically, the method can be carried out by a thermal nitric acid oxidation method, an ultraviolet ozone oxidation method, PECVD-N 2 The second oxide tunneling layer 4 is prepared by an O method, an ozone oxidation method, an LPCVD method, but is not limited thereto. Preferably, in one embodiment of the present invention, the second oxide tunneling layer 4 is prepared by PECVD (see fig. 3).
The second tunneling oxide layer 4 is a silicon oxide layer or a silicon oxynitride layer, but is not limited thereto. Preferably a silicon oxynitride layer. The thickness of the second tunneling oxide layer 4 is 0.5 to 5nm, and is exemplified by 1nm, 2nm, 3nm, or 4nm, but is not limited thereto.
Specifically, the N-type amorphous silicon layer 5a and the second mask layer 5b may be formed by a PECVD method or an LPCVD method, but is not limited thereto. Preferably, in one embodiment of the present invention, the N-type amorphous silicon layer 5a and the second mask layer 5b are formed by a PECVD method.
Among them, the thickness of the N-type amorphous silicon layer 5a is 40 to 300nm, and exemplary is 55nm, 80nm, 120nm, 180nm, 230nm, 250nm or 280nm, but not limited thereto.
The second mask layer 5b is a silicon oxide layer, but is not limited thereto. The thickness of the second mask layer 5b is 5 to 100nm, and is exemplified by 15nm, 30nm, 45nm, 60nm, 75nm, or 90nm, but is not limited thereto.
S5: performing high-temperature treatment on the silicon wafer obtained in the step S4;
specifically, the P-type amorphous silicon layer 3a can be converted into the P-type polysilicon layer 3 through high-temperature treatment, so that the first oxide tunneling layer 2 and the P-type polysilicon layer 3 form a P-type POLO structure. The N-type amorphous silicon layer 5a is converted into an N-type polysilicon layer 5 through high temperature treatment, and then the second oxide tunneling layer 4 and the N-type polysilicon layer 5 form an N-type POLO structure. In addition, by high temperature treatment, the P-type doping element (such as B) in the P-type amorphous silicon layer 3a can be extended into the silicon wafer 1 to form the heavily doped P-type silicon layer 11. Based on the process, a separate boron diffusion process is not needed, the dead zone of a boron-rich layer in boron diffusion is reduced, the positive surface recombination is reduced, and the open circuit voltage of the battery piece is further improved.
The high temperature treatment is performed at 800 to 900 ℃, and is exemplified by 810 ℃, 830 ℃, 850 ℃, 870 ℃ or 890 ℃, but not limited thereto.
Wherein the doping concentration of the heavily doped P-type silicon layer 11 is 5E 18-5E 19cm -3 Exemplary is 7E18cm -3 、9E18cm -3 、1E19cm -3 、2E19cm -3 Or 4E19cm -3 But is not limited thereto. The heavily doped P-type silicon layer 11 forms a floating junction (FFE) with the silicon wafer 1 (P-type silicon wafer) having a junction depth of 0.1 to 1 μm, and exemplary is 0.3 μm, 0.5 μm, 0.7 μm or 0.9 μm, but is not limited thereto.
Wherein the doping concentration of the N-type polycrystalline silicon layer 5 is 3E 19-1E 21cm -3 Exemplary is 5E19cm -3 、7E19cm -3 、9E19cm -3 、2E20cm -3 、4E20cm -3 、6E20cm -3 Or 8E20cm -3 But is not limited thereto.
S6: etching a preset area on the back of the silicon wafer to form a P-type area;
the second oxide tunneling layer 4 and the N-type polycrystalline silicon layer 5 of the preset area on the back of the silicon wafer can be etched by photoetching or laser ablation to form a P-type area, and the area which is not etched is an N-type area; the P-type regions and the N-type regions are alternately arranged (refer to fig. 4).
Preferably, in one embodiment of the present invention, the P-type region is formed by laser ablating the second tunneling oxide layer 4 and the N-type polysilicon layer 5 on the back side of the silicon wafer and partially ablating the wafer.
More preferably, in one embodiment of the present invention, step S6 includes:
s61: carrying out laser etching on the silicon wafer obtained in the step S5 to form an N-type region and a P-type region;
s62: performing alkali polishing on the silicon wafer obtained in the step S61 to remove laser damage of the P-type region; meanwhile, the second mask layer protects the second oxide tunneling layer and the N-type polycrystalline silicon layer on the N-type region from being damaged.
Specifically, the alkali solution used for alkali polishing is KOH solution or NaOH solution, and only the back surface of the silicon wafer is polished, wherein the polishing temperature is 50-80 ℃, and the polishing time is 1-2 min.
S7: removing the first mask layer 3b, the P-type polycrystalline silicon layer 3 and the first oxide tunneling layer 2 on the front surface of the silicon wafer 1, and reserving the heavily doped P-type silicon layer 11; removing the second mask layer 5b on the back surface of the silicon wafer 1;
the first mask layer 3b on the front side of the silicon wafer 1, the P-type polysilicon layer 3, the first oxide tunneling layer 2, and the second mask layer 5b on the back side of the silicon wafer 1 may be removed by a laser ablation and alkali polishing process (refer to fig. 5).
In one embodiment of the present invention, the first mask layer 3b, the P-type polysilicon layer 3, the first oxide tunneling layer 2, and the second mask layer 5b are removed by chained alkali polishing. Specifically, HF and H are adopted first 2 The mixed solution of O (the mass ratio of the mixed solution to the mixed solution is 1:1-2) is polished for 1-3 min at 50-80 ℃, the first mask layer 3b is removed, then KOH solution containing TMAH (2-5 wt%) is polished for 1.5-3 min at 50-70 ℃, and the P-type polycrystalline silicon layer 3 and the first oxide tunneling layer 2 are removed. Then HF and H are adopted 2 And polishing the mixed solution of O (the mass ratio of the mixed solution to the mixed solution is 1:1-2) at 50-80 ℃ for 1-3 min, and removing the second mask layer 5b.
S8: alO formation on the front and back surfaces of the silicon wafer 1 obtained in step S7 x Layer 6;
specifically, the AlO can be formed by PECVD, ALD, MOCVD x Layer 6, but is not limited thereto. Preferably, in one embodiment of the invention, ALD is used to form AlO x Layer 6, which has a thickness of 1 to 20nm, is exemplified by, but not limited to, 4nm, 8nm, 10nm, 13nm, 16nm, or 18 nm.
S9: siN formation on the front and back surfaces of the silicon wafer obtained in step S8 x Layer 7;
specifically, the SiN can be formed by PECVD, ALD, MOCVD x Layer 7 (see fig. 6), but is not limited thereto. Preferably, in one embodiment of the present invention, the SiN is formed by PECVD x Layer 7, which has a thickness of 60 to 110nm, is exemplified by 66nm, 72nm, 80nm, 88nm, 96nm, 103nm or 108nm, but is not limited thereto.
S10: forming an N electrode 9 in the N type region and forming a P electrode 8 in the P type region;
specifically, the P electrode 8 may be an Al electrode or an Ag electrode, but is not limited thereto. Preferably, the P electrode 8 is an Al electrode, which can be combined with the silicon wafer 1 (P-type silicon) to form an aluminum-silicon alloy region 8a, so as to form a p++ junction, and further improve the light conversion efficiency.
Specifically, the N electrode 9 may be an Ag electrode, a Cu electrode, a Ni electrode, or a composite of several metals, but is not limited thereto.
Specifically, the N electrode 9 or the P electrode 8 may be formed using an electroplating or screen printing process, but is not limited thereto.
Specifically, in one embodiment of the present invention, a burn-through paste may be used to burn through SiN x Layer 7 and AlO x Layer 6, so that N electrode 9 is conductively connected to N-type polysilicon layer 5, and P electrode 8 is conductively connected to silicon wafer 1. In another embodiment of the present invention, laser ablation of partial regions of SiN may be employed x Layer 7 and AlO x Layer 6, then N electrode 9 and P electrode 8 are formed.
Correspondingly, referring to FIG. 7, the invention also provides a P-type IBC battery which is prepared by the preparation method and comprises a silicon wafer 1, a heavily doped P-type silicon layer 11 and AlO sequentially arranged on the front surface of the silicon wafer 1 x Layer 6 and SiN x Layer 7;
the back of the silicon wafer 1 is provided with an N-type region and a P-type region which are arranged in a crossing way, wherein the N-type region comprises a second oxide tunneling layer 4, an N-type polycrystalline silicon layer 5 and an AlO which are sequentially arranged x Layer 6, siN x The layer 7 and the N electrode 9,N electrode 9 are connected with the N-type polycrystalline silicon layer 5 in a conductive manner; the P-type region comprises AlO arranged in sequence x Layer 6, siN x Layer 7 and P electrode 8, P electrode 8 is connected with silicon chip 1 electrically conductive.
Based on the preparation process, the conversion efficiency of the P-type IBC battery can reach 23-24%, and the conventional PERC battery only reaches 21-22%.
The above disclosure is only a preferred embodiment of the present invention, and it is needless to say that the scope of the invention is not limited thereto, and therefore, the equivalent changes according to the claims of the present invention still fall within the scope of the present invention.
Claims (10)
1. The preparation method of the P-type IBC battery is characterized by comprising the following steps of:
(1) Providing a silicon wafer and texturing to form a textured surface;
(2) Polishing the back surface of the silicon wafer after texturing;
(3) Forming a first oxide tunneling layer, a P-type amorphous silicon layer and a first mask layer on the front surface of the silicon wafer;
(4) Forming a second oxide tunneling layer, an N-type amorphous silicon layer and a second mask layer on the back surface of the silicon wafer;
(5) Performing high-temperature treatment on the silicon wafer obtained in the step (4) to convert the P-type amorphous silicon layer into a P-type polycrystalline silicon layer, and converting the N-type amorphous silicon layer into an N-type polycrystalline silicon layer; and the doping elements in the P-type amorphous silicon layer are expanded into the silicon wafer to form a heavily doped P-type silicon layer;
(6) Etching a preset area on the back of the silicon wafer to form a P-type area, wherein the area which is not etched is an N-type area;
(7) Removing the first mask layer, the P-type polycrystalline silicon layer and the first oxide tunneling layer on the front surface of the silicon wafer, and reserving the heavily doped P-type silicon layer; removing the second mask layer on the back of the silicon wafer;
(8) AlO formation on the front and back surfaces of the silicon wafer obtained in step (7) x A layer;
(9) SiN formation on the front and back surfaces of the silicon wafer obtained in step (8) x A layer;
(10) And forming an N electrode in the N type region and forming a P electrode in the P type region.
2. The method of fabricating a P-type IBC cell according to claim 1, wherein in step (3), the first oxide tunneling layer, the P-type amorphous silicon layer and the first mask layer are fabricated by PECVD;
the first oxide tunneling layer is a silicon oxide layer or a silicon oxynitride layer, and the thickness of the first oxide tunneling layer is 0.5-5 nm;
the thickness of the P-type amorphous silicon layer is 40-300 nm;
the first mask layer is a silicon oxide layer, and the thickness of the first mask layer is 5-100 nm.
3. The method of claim 1, wherein in step (4), the second tunneling oxide layer, the N-type amorphous silicon layer, and the second mask layer are prepared by PECVD.
The second oxide tunneling layer is a silicon oxide layer or a silicon oxynitride layer, and the thickness of the second oxide tunneling layer is 0.5-5 nm;
the thickness of the N-type amorphous silicon layer is 40-300 nm;
the second mask layer is a silicon oxide layer, and the thickness of the second mask layer is 5-100 nm.
4. The method for manufacturing a P-type IBC cell according to claim 1, wherein the doping concentration of the N-type polysilicon layer is 3E 19-1E 21cm -3 ；
The doping concentration of the heavily doped P-type silicon layer is 5E 18-5E 19cm -3 The heavily doped P-type silicon layer and the silicon wafer form a floating junction, and the junction depth is 0.1-1 mu m.
5. The method of preparing a P-type IBC cell according to claim 1, wherein step (1) comprises:
(1.1) providing a silicon wafer and texturing to form a textured surface;
(1.2) treating the silicon wafer subjected to texturing by hydrogen peroxide or ozone so as to ensure that the surface of the silicon wafer has hydrophilicity.
6. The method of claim 1, wherein in step (3), the high temperature treatment temperature is 800 to 900 ℃.
7. The method of preparing a P-type IBC cell according to claim 1, wherein step (6) comprises:
(6.1) carrying out laser etching on the silicon wafer obtained in the step (5) to form an N-type region and a P-type region;
(6.2) carrying out alkali polishing on the silicon wafer obtained in the step (6.1) to remove laser damage of the P-type region; and simultaneously, the second mask layer protects the second oxide tunneling layer and the N-type polycrystalline silicon layer on the N-type region from being damaged.
8. The method of claim 1, wherein in step (6), the first mask layer, the P-type polysilicon layer, the first tunneling oxide layer, and the second mask layer are removed from the front surface of the silicon wafer by alkali polishing.
9. The method of claim 1, wherein in step (8), ALD is used to form the AlO x A layer having a thickness of 1 to 20nm;
in step (9), PECVD is used to form the SiN x The thickness of the layer is 60-110 nm.
10. The P-type IBC battery is characterized by comprising a silicon wafer, a heavily doped P-type silicon layer and AlO, wherein the heavily doped P-type silicon layer and AlO are sequentially arranged on the front surface of the silicon wafer x Layer and SiN x A layer;
the back of the silicon chip is provided with an N-type region and a P-type region which are arranged in a crossing way, and the P-type region comprises AlO which are arranged in sequence x Layer, siN x The layer and the P electrode are connected with the silicon chip in a conductive way; the N-type region comprises a second oxide tunneling layer, an N-type polysilicon layer and AlO which are sequentially arranged x Layer, siN x The N electrode is connected with the N-type polycrystalline silicon layer in a conductive mode.
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| CN117153903B (en) * | 2023-10-26 | 2024-05-10 | 晶科能源(海宁)有限公司 | Solar cell and method for manufacturing solar cell |
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