CN116646263A - Chip packaging method and packaging structure - Google Patents

Chip packaging method and packaging structure Download PDF

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Publication number
CN116646263A
CN116646263A CN202310665537.9A CN202310665537A CN116646263A CN 116646263 A CN116646263 A CN 116646263A CN 202310665537 A CN202310665537 A CN 202310665537A CN 116646263 A CN116646263 A CN 116646263A
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CN
China
Prior art keywords
substrate
chip
bearing plate
metal bearing
metal
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CN202310665537.9A
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Chinese (zh)
Inventor
高雄
陶玉娟
姜艳
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Tongfu Microelectronics Co Ltd
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Tongfu Microelectronics Co Ltd
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Priority to CN202310665537.9A priority Critical patent/CN116646263A/en
Publication of CN116646263A publication Critical patent/CN116646263A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The embodiment of the disclosure provides a chip packaging method and a chip packaging structure, wherein the method comprises the following steps: providing a substrate and fixing a first chip to a central area of a first surface of the substrate; providing a first metal bearing plate and a second metal bearing plate respectively, wherein the second metal bearing plate is provided with a plurality of conductive supporting structures; fixing a first metal bearing plate on one side of the first chip, which is away from the substrate, and fixing a second metal bearing plate on the edge area of the first surface of the substrate through a conductive supporting structure; the first metal bearing plate is flush with the second metal bearing plate, and a gap is reserved between the first metal bearing plate and the second metal bearing plate; fixing the second chip on the second surface of the substrate; and forming plastic sealing layers on the first surface and the second surface of the substrate respectively through a one-time plastic sealing process. The first metal bearing plate, the second metal bearing plate and the conductive supporting structure have bearing effect on the substrate when the second chip is attached to the second surface of the substrate and when the substrate is cut after the double-sided attachment is completed.

Description

Chip packaging method and packaging structure
Technical Field
The embodiment of the disclosure belongs to the technical field of semiconductor packaging, and particularly relates to a chip packaging method and a chip packaging structure.
Background
At present, in the packaging process of a semiconductor, two-sided plastic packaging is generally adopted, the front surface of a substrate is firstly subjected to plastic packaging, and the back surface of the substrate is subjected to plastic packaging, wherein the two-sided plastic packaging can lead to serious warping of a packaging structure; meanwhile, the strip-shaped adapter plate/plastic sealing layer is attached to the back surface of the substrate, so that the overall heat dissipation effect of the packaging structure is poor. In the existing double-sided one-step plastic packaging process, when the chips are subjected to double-sided mounting, no load is carried when the back mounting is carried out due to different heights of the front chips, mounting is difficult, and no load is carried when the back mounting of the substrate and the cutting is carried out after the double-sided mounting of the substrate are finished, so that the chips are difficult to cut and easy to damage due to no load.
In view of the above, it is necessary to provide a chip packaging method and a packaging structure which are reasonable in design and effectively solve the above problems.
Disclosure of Invention
The embodiment of the disclosure aims to at least solve one of the technical problems in the prior art and provides a chip packaging method and a packaging structure.
An aspect of an embodiment of the present disclosure provides a chip packaging method, including:
providing a substrate, and fixing a first chip in a central area of a first surface of the substrate;
providing a first metal bearing plate and a second metal bearing plate respectively, wherein the second metal bearing plate is provided with a plurality of conductive supporting structures;
fixing the first metal bearing plate on one side of the first chip, which is away from the substrate, and fixing the second metal bearing plate on the edge area of the first surface of the substrate through the conductive supporting structure; wherein,,
the first metal bearing plate is flush with the second metal bearing plate, and a gap is formed between the first metal bearing plate and the second metal bearing plate;
fixing a second chip on a second surface of the substrate;
and forming plastic sealing layers on the first surface and the second surface of the substrate respectively through a one-time plastic sealing process, wherein the plastic sealing layers respectively wrap the second chip, the first metal bearing plate and the second metal bearing plate.
Optionally, after the fixing the first chip to the central area of the first surface of the substrate, the method further includes:
and forming a welding metal layer on one side of the first chip, which is away from the substrate.
Optionally, the fixing the first metal carrier board on a side of the first chip facing away from the substrate includes:
and fixing the first metal bearing plate on one side of the first chip, which is away from the substrate, through the welding metal layer.
Optionally, the fixing the first chip on the first surface of the substrate includes:
flip-chip the first chip on a central area of the first surface of the substrate;
an underfill layer is formed between the first chip and the first surface of the substrate.
Optionally, the fixing the second metal carrier board to the edge area of the first surface of the substrate through the conductive supporting structure includes:
and fixing the second metal bearing plate on the edge area of the first surface of the substrate through the conductive supporting structure by a hot-pressing reflow process.
Optionally, after forming the plastic layer on the first surface and the second surface of the substrate through a one-time plastic packaging process, the method further includes:
and if the outer edge area of the second metal bearing plate is the second metal bearing plate, forming a shielding layer on the periphery of the second chip.
Optionally, after forming the plastic layer on the first surface and the second surface of the substrate through a one-time plastic packaging process, the method further includes:
and if the outer side edge area of the second metal bearing plate is the plastic sealing layer, forming a shielding layer on the periphery of the plastic sealing layer.
Optionally, after forming the plastic layer on the first surface and the second surface of the substrate through a one-time plastic packaging process, the method further includes:
and forming a signal extraction layer on one side of the first metal bearing plate and one side of the second metal bearing plate, which are away from the substrate.
Optionally, the conductive support structure is a metal conductive post or a solder ball.
Another aspect of the embodiments of the present disclosure provides a chip packaging structure, which is formed by adopting the packaging method described above.
According to the chip packaging method and the packaging structure, the first chip is fixed on the first surface of the substrate, then the first metal bearing plate is fixed on one side, away from the substrate, of the first chip, and the second metal bearing plate is fixed on the edge area of the first surface of the substrate through the conductive supporting structure, so that when the second chip is attached to the second surface of the substrate, the first metal bearing plate, the second metal bearing plate and the conductive supporting structure have good bearing effect on the substrate, and chip attachment on the second surface of the substrate can be well achieved.
In addition, when cutting is carried out after the double-sided mounting of the substrate is completed, the first metal bearing plate, the second metal bearing plate and the conductive supporting structure play a good bearing role on the substrate, so that the cutting difficulty is reduced, and the chip cannot be damaged.
According to the packaging method disclosed by the embodiment of the disclosure, the plastic layers are respectively formed on the first surface and the second surface of the substrate by adopting the one-time plastic packaging process, so that the warpage of the packaging structure is reduced, and the yield of the packaging structure is increased.
In addition, in the plastic packaging process, the first metal bearing plate, the second metal bearing plate and the plurality of conductive supporting structures play a bearing role on the substrate, so that the stability of the substrate in the plastic packaging process is ensured, the plurality of conductive supporting structures strengthen the firmness of the connection between the second metal bearing plate and the substrate, and further, the damage caused by the impact of plastic packaging materials on the first chip and the second chip can be avoided, and the yield of plastic packaging finished products is improved.
According to the packaging method, the first metal bearing plate is fixed on the first chip, and the first chip can be further subjected to heat dissipation.
Drawings
Fig. 1 is a flow chart of a chip packaging method according to an embodiment of the disclosure;
FIGS. 2-8 are schematic diagrams illustrating a packaging process of a chip package according to another embodiment of the disclosure;
FIG. 9 is a schematic diagram of a chip package structure according to another embodiment of the disclosure;
fig. 10 is a schematic structural diagram of a chip package structure according to another embodiment of the disclosure.
Detailed Description
In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the embodiments of the present disclosure are described in further detail below with reference to the accompanying drawings and detailed description.
As shown in fig. 1, an aspect of an embodiment of the present disclosure provides a chip packaging method S100, the method S100 including:
s110, providing a substrate, and fixing the first chip in the central area of the first surface of the substrate.
As shown in fig. 2 and 3, a substrate 110 is provided, and a first chip 120 is fixed to a central region of a first surface of the substrate 110.
It should be understood that the first surface of the substrate 110 may be the front surface of the substrate 110 or the back surface of the substrate 110, which may be specifically selected according to practical needs. In this embodiment, the first surface of the substrate 110 is taken as the back surface of the substrate 110, and the second surface of the substrate 110 is taken as the front surface of the substrate 110. That is, the first chip 120 is fixed to the central region of the back surface of the substrate 110.
In this embodiment, the first chip 120 is fixed to the central area of the first surface of the substrate 110, and specifically includes:
as shown in fig. 3, first, the first chip 120 is flip-chip mounted on a central region of the first surface of the substrate 110. Specifically, the first chip 120 is flip-chip mounted on the central region of the back surface of the substrate 110 through the conductive bump 121.
The manner in which the first chip 120 is fixed to the back surface of the substrate 110 is not particularly limited. In addition to the flip-chip method in this embodiment, a method such as a forward mounting method may be adopted, and may be selected according to actual needs.
It should be noted that, the number of the first chips 120 is not limited in this embodiment, and may be 1, 2 or more, and may be selected according to actual needs.
Next, as shown in fig. 3, an underfill layer 122 is formed between the first chip 120 and the first surface of the substrate 110. The first chip 120 may be better fixed to the back surface of the substrate 110 by the underfill layer 122.
Illustratively, after securing the first chip to the central region of the first surface of the substrate, the method further comprises:
and forming a welding metal layer on one side of the first chip, which is away from the substrate.
As shown in fig. 4, a solder metal layer 123 is formed on a side of the first chip 120 facing away from the substrate 110. In the present embodiment, the solder metal layer 123 is made of a thermal interface material, and preferably, the solder metal layer 123 is made of a metal indium sheet.
S120, providing a first metal bearing plate and a second metal bearing plate respectively, wherein the second metal bearing plate is provided with a plurality of conductive supporting structures.
As shown in fig. 4, a first metal carrier 130 and a second metal carrier 140 are provided, wherein a plurality of conductive support structures 150 are preset on the second metal carrier 140. The plurality of conductive support structures 150 may function as supports on the one hand and may also function as electrical connections on the other hand.
In this embodiment, the first metal carrier plate 130 and the second metal carrier plate 140 are both made of a metal copper plate, and may be made of other metal materials, which is not particularly limited in this embodiment.
It should be further noted that the conductive support structure 150 may be a metal copper pillar or a solder ball, and preferably, the conductive support structure 150 may be a copper pillar or a solder ball. As shown, in this embodiment, the conductive support structure 150 employs copper pillars.
S130, fixing the first metal bearing plate on one side of the first chip, which is away from the substrate, and fixing the second metal bearing plate on an edge area of the first surface of the substrate through the conductive supporting structure; wherein,,
the first metal bearing plate is flush with the second metal bearing plate, and a gap is formed between the first metal bearing plate and the second metal bearing plate.
Specifically, as shown in fig. 4, the first metal carrier 130 is fixed on a side of the first chip 120 facing away from the substrate 110, and the second metal carrier 140 is fixed on an edge region of the first surface of the substrate 110 through the conductive support structure 150. The first metal carrier 130 and the second metal carrier 140 are flush, so that when the chips are mounted on the second surface of the substrate 110 after the first metal carrier 130 and the second metal carrier 140 are turned over, the first metal carrier 130, the second metal carrier 140 and the conductive support structure 150 support the substrate 110.
As shown in fig. 4, there is a gap between the first metal carrier plate 130 and the second metal carrier plate 140, that is, the first metal carrier plate 130 and the second metal carrier plate 140 are not connected together, but have a gap, so that a short circuit is not caused when the signals of the package structure are finally led out through the first metal carrier plate 130 and the second metal carrier plate 140.
Exemplary, the fixing the first metal carrier board on the side of the first chip facing away from the substrate specifically includes:
the first metal carrier 130 is fixed to the side of the first chip 120 facing away from the substrate 110 by the solder metal layer 123 using a thermal reflow process.
Illustratively, the fixing the second metal carrier board to the edge region of the first surface of the substrate through the conductive support structure includes:
as shown in fig. 4, the conductive support structure 150 is fixed to the edge region of the back surface of the substrate 110 through the conductive bump 121 by using a thermal reflow process, so as to fix the second metal carrier plate 140 to the back surface of the substrate 110.
And S140, fixing the second chip on the second surface of the substrate.
As shown in fig. 5, after the second metal carrier plate 140 is fixed on the substrate 110, the first metal carrier plate 130 and the second metal carrier plate 140 are turned over, and the second chip 160 is fixed on the front surface of the substrate 110, so as to complete the double-sided chip mounting of the substrate 110.
That is, as shown in fig. 5, the first and second metal carrier plates 130 and 140 serve as carriers at the bottom, and then the plurality of second chips 160 are fixed to the front surface of the substrate 110.
In the present embodiment, the heights of the plurality of second chips 160 are not specifically limited, and the heights of the plurality of second chips 160 may be the same or different, and the present embodiment is not specifically limited. In addition, the number of the second chips 160 is not particularly limited in this embodiment, and may be selected according to actual needs.
S150, forming plastic layers on the first surface and the second surface of the substrate respectively through a one-time plastic packaging process, wherein the plastic layers respectively wrap the second chip, the first metal bearing plate and the second metal bearing plate.
Specifically, as shown in fig. 6, after the mounting of the two sides of the substrate 110 is completed, a plastic layer 170 is formed on the first surface and the second surface of the substrate 110 by a single plastic packaging process, and the plastic layer 170 wraps the second chip 160, the first metal carrier 130 and the second metal carrier 140.
Specifically, the structure to be molded after the chip is mounted is placed in a plastic mold, that is, the first metal carrier 130 and the second metal carrier 140 are placed as bottoms in the plastic mold, the plastic material is injected, and the plastic layer 170 is formed on the back and the front of the substrate 110 through one-time plastic process, and the plastic layer 170 encapsulates the second chip 160 and the first metal carrier 130 and the second metal carrier 140. The plastic layer 170 protects the substrate 110, the first chip 120, the first metal carrier 130, the second metal carrier 140, the plurality of conductive support structures 150, and the second chip 160.
Only one side of the first metal carrier plate 130 and the second metal carrier plate 140 facing the substrate 110 and the gap therebetween are formed with a plastic layer 170, and one side of the first metal carrier plate 130 and the second metal carrier plate 140 facing away from the substrate 110 is not provided with the plastic layer 170.
After the structure to be molded is molded to form the molding layer 170, the whole substrate 110 is cut to form an independent package.
In the above embodiment, the first metal carrier plate 130, the second metal carrier plate 140 and the plurality of conductive support structures 150 can perform a good carrying function on the substrate 110 in the cutting process after the double-sided mounting of the substrate 110 and the plastic packaging, so that the cutting difficulty is reduced and the chip is not damaged.
In the above embodiment, the plastic layer 170 is formed on the first surface and the second surface of the substrate 110 by using a one-time plastic packaging process, so that the warpage of the package structure can be reduced, and the yield of the package structure can be increased. In addition, in the plastic packaging process, the substrate 110 needs to bear the impact of the plastic packaging material, the first metal bearing plate 130, the second metal bearing plate 140 and the plurality of conductive supporting structures 150 play a bearing role on the substrate 110, so that the stability of the substrate 110 in the plastic packaging process is ensured, the plurality of conductive supporting structures 150 strengthen the connection firmness of the second metal bearing plate 140 and the substrate 110, and further, the damage caused by the impact of the plastic packaging material on the first chip 120 and the second chip 160 can be avoided, and the yield of plastic packaging finished products is improved.
Illustratively, after forming the plastic layers on the first surface and the second surface of the substrate through a one-time plastic packaging process, the method further includes:
as shown in fig. 7, if the outer edge region of the second metal carrier 140 is the second metal carrier 140, a shielding layer 180 is formed on the periphery of the second chip 160. The shielding layer 180 may prevent the second chip 160 from electromagnetic interference.
Since the bottom edge of the package structure is the second metal carrier 140, that is, the bottom edge of the package structure is the metal layer, if the shielding layer 180 is formed at the periphery of the entire package structure, the contact of the shielding layer 180 with the metal layer at the bottom edge of the package structure may cause a short circuit, so that the shielding layer 180 is selectively formed at the periphery of each second chip 160.
The step of forming the shielding layer 180 by the package structure may be:
a through groove surrounding the periphery of the second chip 160 is formed on the plastic sealing layer 170 on the periphery of the second chip 160 by adopting a plastic sealing material perforation process, and a metal layer is deposited in the through groove by adopting a sputtering process and the like, so that a shielding layer 180 surrounding the periphery of the second chip 160 is formed.
Illustratively, after forming the plastic layers on the first surface and the second surface of the substrate through a one-time plastic packaging process, the method further includes:
as shown in fig. 8, if the outer edge region of the second metal carrier plate 140 is the plastic sealing layer 170, a shielding layer 180 is formed on the periphery of the plastic sealing layer 170. The shielding layer 180 may prevent the entire package structure from electromagnetic interference.
Because the bottom edge of the package structure is the plastic layer 170, that is, the bottom edge of the package structure is the plastic layer material and not the metal material, the shielding layer 180 is formed on the periphery of the plastic layer 170, and the contact between the shielding layer 180 and the bottom edge of the package structure is the plastic layer 170 will not cause short circuit.
The specific steps of forming the shielding layer 180 on the periphery of the package structure may be:
a through groove surrounding the periphery of the plastic sealing layer 170 is formed at the periphery of the plastic sealing layer 170 by adopting a plastic sealing material perforation process, a metal layer is deposited in the through groove by adopting a sputtering process and the like, so that a shielding layer 180 surrounding the periphery of the plastic sealing layer 170 is formed, namely, the shielding layer 180 surrounding the periphery of the whole packaging structure is formed, and only one side on which the first metal bearing plate 130 and the second metal bearing plate 140 are formed is reserved for signal output.
After forming the plastic sealing layers on the first surface and the second surface of the substrate respectively through a one-time plastic sealing process, the method further comprises:
a signal extraction layer (not shown) is formed on a side of the first and second metal carrier plates 130 and 140 facing away from the substrate 110 to extract signals of the system-in-package structure. In this embodiment, a tin layer may be coated on a side of the first metal carrier 130 and the second metal carrier 140 facing away from the substrate 110, so as to lead out signals of the package structure. The specific structure of the signal extraction layer is not particularly limited, and the embodiment may be selected according to practical situations, for example, the signal extraction layer may be a solder ball or the like.
In this embodiment, after the signal extraction layer is formed on the side of the first metal carrier 130 and the second metal carrier 140 facing away from the substrate 110, the whole package structure may be mounted on a square flat leadless package or on a PCB circuit board, and the signals of the package structure are extracted through the signal extraction layer.
In the above embodiment, since the plastic layer 170 is formed on the side of the first metal carrier plate 130 and the second metal carrier plate 140 facing the substrate 110 and in the gap between the two, when the signal extraction layer is formed on the side of the first metal carrier plate 130 and the second metal carrier plate 140 facing away from the substrate 110, the short circuit between the first metal carrier plate 130 and the second metal carrier plate 140 on the two sides of the gap due to the connection of the signal extraction layer can be avoided, and the performance of the package structure is ensured.
According to the chip packaging method, the first chip is fixed on the first surface of the substrate, then the first metal bearing plate is fixed on one side, away from the substrate, of the first chip, and the second metal bearing plate is fixed on the edge area of the first surface of the substrate through the conductive supporting structure, so that when the second chip is attached to the second surface of the substrate, the first metal bearing plate, the second metal bearing plate and the conductive supporting structure have good bearing effect on the substrate, chip attachment on the second surface of the substrate can be well achieved, in addition, when cutting is carried out after the double-sided attachment of the substrate, the first metal bearing plate, the second metal bearing plate and the conductive supporting structure have good bearing effect on the substrate, cutting difficulty is reduced, and the chip cannot be damaged; according to the packaging method, a primary plastic packaging process is adopted to form plastic layers on the first surface and the second surface of the substrate respectively, so that the warping of the packaging structure is reduced, and the yield of the packaging structure is increased; the first metal bearing plate is fixed on the first chip, and the first chip can be further subjected to heat dissipation.
As shown in fig. 9 and 10, another aspect of the embodiments of the present disclosure provides a chip package structure 100, which is formed by using the above-described packaging method S100. Specific steps of the packaging method S100 have been described in detail above and will not be repeated here
As shown in fig. 9 and 10, the chip package structure 100 includes a substrate 110, a first chip 120 disposed on a first surface of the substrate 110, a second chip 160 disposed on a second surface of the substrate 110, a first metal carrier 130 disposed on a side of the first chip 120 facing away from the substrate 110, a second metal carrier electrically connected to the first surface of the substrate 110 through a plurality of conductive support structures 150, and a plastic layer 170. The first metal bearing plate 130 and the second metal bearing plate 140 are flush, and a gap is formed between the first metal bearing plate 130 and the second metal bearing plate 140.
In this embodiment, the first metal carrier plate 130 and the second metal carrier plate 140 are both made of a metal copper plate, and may be made of other metal materials, which is not particularly limited in this embodiment.
It should be further noted that the conductive support structure 150 may be a metal copper pillar or a solder ball, and preferably, the conductive support structure 150 may be a copper pillar or a solder ball. As shown in fig. 4, in the present embodiment, the conductive support structure 150 employs copper pillars.
As shown in fig. 9 and 10, a plastic layer 170 is disposed on the first and second surfaces of the substrate 110, and the plastic layer 170 encapsulates the second chip 160 and the first and second metal carrier plates 130 and 140. The plastic layer 170 protects the substrate 110, the first chip 120, the second chip 160, the first metal carrier 130, the second metal carrier 140, and the plurality of conductive support structures 150.
Specifically, the plastic layer 170 is formed on the first surface and the second surface of the substrate 110 by a one-time plastic packaging process, so that the warpage of the package structure 100 is reduced, and the yield of the package structure 100 is increased.
It should be understood that the first surface of the substrate 110 may be the front surface of the substrate 110 or the back surface of the substrate 110, which may be specifically selected according to practical needs. In this embodiment, the first surface of the substrate 110 is taken as the back surface of the substrate 110, and the second surface of the substrate 110 is taken as the front surface of the substrate 110. That is, the first chip 120 is fixed to the back surface of the substrate 110.
In the present embodiment, the first chip 120 is flip-chip mounted on the back surface of the substrate 110 through the conductive bumps 121 as shown in fig. 9 and 10. An underfill layer 122 is disposed between the first chip 120 and the substrate 110. The underfill layer 122 may better fix the first chip 120 to the back surface of the substrate 110.
As shown in fig. 9 and 10, the package structure 100 further includes a solder metal layer 123, and the solder metal layer 123 is sandwiched between the first chip 120 and the first metal carrier 130. In the present embodiment, the solder metal layer 123 is made of a thermal interface material, and preferably, the solder metal layer 123 is made of a metal indium sheet.
As shown in fig. 9 and 10, the package structure 100 further includes a shielding layer 180, and as shown in fig. 9, if the edge area of the second metal carrier 140 is the second metal carrier 140, the shielding layer 180 is enclosed on the periphery of the second chip 160. As shown in fig. 10, if the edge area of the second metal carrier plate 140 is the plastic layer 170, the shielding layer 180 is disposed on the periphery of the entire package structure 100, and only one side of the first metal carrier plate 130 and the second metal carrier plate 140 facing away from the substrate 110 is exposed.
A signal extraction layer (not shown) is disposed on a side of the first and second metal carrier plates 130 and 140 facing away from the substrate 110, so as to extract signals of the system-in-package structure.
In this embodiment, the signal extraction layer may be a tin layer or a solder ball, etc., and the embodiment is not particularly limited and may be limited according to practical situations.
In this embodiment, after the signal extraction layer is formed on the side of the first metal carrier 130 and the second metal carrier 140 facing away from the substrate 110, the whole package structure may be mounted on a square flat leadless package or on a PCB circuit board, and the signals of the package structure are extracted through the signal extraction layer.
In the chip packaging structure disclosed by the embodiment of the disclosure, when the first metal bearing plate, the second metal bearing plate and the plurality of conductive supporting structures are attached to the second surface of the substrate, a good bearing effect is achieved on the substrate, and the chip attachment on the second surface of the substrate can be well achieved, in addition, when the double-sided attachment of the substrate is completed and then cutting is conducted, the first metal bearing plate, the second metal bearing plate and the plurality of conductive supporting structures have a good bearing effect on the substrate, so that the cutting difficulty is reduced, and the chip cannot be damaged; a primary plastic packaging process is adopted to form plastic packaging layers on the first surface and the second surface of the substrate respectively, so that the warping of the packaging structure is reduced, and the yield of the packaging structure is increased; the first metal bearing plate is arranged on one side of the first chip, which is away from the substrate, and can also play a role in heat dissipation of the first chip.
It is to be understood that the above implementations are merely exemplary implementations employed to illustrate the principles of the disclosed embodiments, which are not limited thereto. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the embodiments of the disclosure, and these modifications and improvements are also considered to be within the scope of the embodiments of the disclosure.

Claims (10)

1. A method of packaging a chip, the method comprising:
providing a substrate, and fixing a first chip in a central area of a first surface of the substrate;
providing a first metal bearing plate and a second metal bearing plate respectively, wherein the second metal bearing plate is provided with a plurality of conductive supporting structures;
fixing the first metal bearing plate on one side of the first chip, which is away from the substrate, and fixing the second metal bearing plate on the edge area of the first surface of the substrate through the conductive supporting structure; wherein,,
the first metal bearing plate is flush with the second metal bearing plate, and a gap is formed between the first metal bearing plate and the second metal bearing plate;
fixing a second chip on a second surface of the substrate;
and forming plastic sealing layers on the first surface and the second surface of the substrate respectively through a one-time plastic sealing process, wherein the plastic sealing layers respectively wrap the second chip, the first metal bearing plate and the second metal bearing plate.
2. The method of claim 1, wherein after the securing the first chip to the central region of the first surface of the substrate, the method further comprises:
and forming a welding metal layer on one side of the first chip, which is away from the substrate.
3. The method of claim 2, wherein the securing the first metal carrier plate to the side of the first chip facing away from the substrate comprises:
and fixing the first metal bearing plate on one side of the first chip, which is away from the substrate, through the welding metal layer.
4. A method according to any one of claims 1 to 3, wherein said securing said first chip to said first surface of said substrate comprises:
flip-chip the first chip on a central area of the first surface of the substrate;
an underfill layer is formed between the first chip and the first surface of the substrate.
5. A method according to any one of claims 1 to 3, wherein said securing the second metal carrier plate to the edge region of the first surface of the substrate by the conductive support structure comprises:
and fixing the second metal bearing plate on the edge area of the first surface of the substrate through the conductive supporting structure by a hot-pressing reflow process.
6. A method according to any one of claims 1 to 3, wherein after forming the plastic layer on the first surface and the second surface of the substrate by a single plastic sealing process, the method further comprises:
and if the outer edge area of the second metal bearing plate is the second metal bearing plate, forming a shielding layer on the periphery of the second chip.
7. A method according to any one of claims 1 to 3, wherein after forming the plastic layer on the first surface and the second surface of the substrate by a single plastic sealing process, the method further comprises:
and if the outer side edge area of the second metal bearing plate is the plastic sealing layer, forming a shielding layer on the periphery of the plastic sealing layer.
8. A method according to any one of claims 1 to 3, wherein after forming the plastic layer on the first surface and the second surface of the substrate by a single plastic sealing process, the method further comprises:
and forming a signal extraction layer on one side of the first metal bearing plate and one side of the second metal bearing plate, which are away from the substrate.
9. A method according to any one of claims 1 to 3, wherein the conductive support structure is a metallic conductive post or a solder ball.
10. A chip packaging structure formed by packaging by the packaging method according to any one of claims 1 to 9.
CN202310665537.9A 2023-06-06 2023-06-06 Chip packaging method and packaging structure Pending CN116646263A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310665537.9A CN116646263A (en) 2023-06-06 2023-06-06 Chip packaging method and packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310665537.9A CN116646263A (en) 2023-06-06 2023-06-06 Chip packaging method and packaging structure

Publications (1)

Publication Number Publication Date
CN116646263A true CN116646263A (en) 2023-08-25

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310665537.9A Pending CN116646263A (en) 2023-06-06 2023-06-06 Chip packaging method and packaging structure

Country Status (1)

Country Link
CN (1) CN116646263A (en)

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