CN116636005A - 半导体裸片堆叠以及相关联系统及方法 - Google Patents
半导体裸片堆叠以及相关联系统及方法 Download PDFInfo
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- CN116636005A CN116636005A CN202180052891.3A CN202180052891A CN116636005A CN 116636005 A CN116636005 A CN 116636005A CN 202180052891 A CN202180052891 A CN 202180052891A CN 116636005 A CN116636005 A CN 116636005A
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Abstract
本发明公开半导体裸片堆叠以及相关联方法及系统。所述半导体裸片堆叠可包含具有存储器阵列的第一裸片及具有经配置以存取所述存储器阵列的CMOS电路系统的第二裸片。所述第一裸片可不具有用于存取所述存储器阵列的电路系统。此外,所述第一及第二裸片可经接合以用作单个存储器装置,且所述第一及第二裸片的前表面经连结以在其间形成电连接。所述第二裸片可包含未由所述第一裸片覆盖的部分,所述半导体裸片堆叠的接合垫定位于所述部分中。所述第一裸片可提供用于接合线连接到所述接合垫的空间,而不干扰附接于所述半导体裸片堆叠上方的另一裸片。多个半导体裸片堆叠可堆叠在彼此顶部上且彼此成一直线。
Description
技术领域
本公开大体上涉及半导体装置组合件,且更特定来说,涉及半导体裸片堆叠以及相关联系统及方法。
背景技术
半导体封装通常包含一或多个半导体裸片(例如,存储器芯片、微处理器芯片、成像器芯片),其安装在衬底上并围封在保护覆盖层中。半导体裸片可包含功能特征(例如存储器单元、处理器电路及成像器装置),以及电连接到功能特征的接合垫。接合垫可电连接到衬底的对应导电结构,所述导电结构可耦合到保护覆盖层外部的终端,使得半导体裸片可连接到更高级别的电路系统。
在一些半导体封装中,两个或更多个半导体裸片堆叠在彼此顶部上,以减少半导体封装的占据面积。堆叠中的半导体裸片可布置成类似阶梯状的图案(其可称为“叠瓦”),使得半导体裸片的部分可自由存取,例如,以形成到定位于所述部分中的一或多个接合垫的接合线。然而,此布置倾向于增加半导体封装的占据面积。在一些情况下,半导体裸片可以锯齿形图案堆叠,以相对于上覆于接合垫上方的半导体裸片增加接合垫上方的空间。此外,半导体裸片可包含穿衬底通路(TSV),以促进半导体裸片的堆叠,但与线接合技术相比,成本增加。
附图说明
参考以下图式可充分理解本技术的许多方面。图式中的组件不一定按比例绘制。替代地,重点清楚地说明本技术的总体特征及原则。
图1A是半导体裸片的横截面图。
图1B到1D是根据本技术的实施例的半导体裸片对及半导体裸片组合件的横截面图。
图2A及2B是根据本技术的实施例的半导体裸片堆叠及半导体裸片组合件的三维图。
图3说明根据本技术的实施例的半导体裸片堆叠的各种平面视图。
图4说明根据本技术的实施例的制作半导体裸片堆叠的实例工艺步骤。
图5是示意性说明包含根据本技术的实施例配置的半导体装置组合件的系统的框图。
图6是根据本技术的实施例的制作半导体裸片对的方法的流程图。
具体实施方式
下文描述半导体裸片堆叠的若干实施例的特定细节以及相关联系统及方法。术语“半导体装置或裸片”一般是指包含一或多个半导体材料的固态装置。半导体装置的实例包含逻辑装置、存储器装置、控制器或微处理器(例如,中央处理单元(CPU)、图形处理单元(GPU))等。此类半导体装置可包含集成电路或组件、数据存储元件、处理组件及/或在半导体衬底上制造的其它特征。此外,术语“半导体装置或裸片”可指成品装置或在成为成品功能装置之前的各个处理阶段的组合件或其它结构。取决于使用衬底的上下文,术语“衬底”可指晶片级衬底或单粒化裸片级衬底。此外,衬底可包含半导体晶片、封装支撑衬底、中介层、半导体装置或裸片等。相关领域的一般技术人员将认识到,可在晶片级或裸片级执行本文中描述的方法的适合步骤。
此外,除非上下文另有指示,否则本文中公开的结构可使用常规半导体制造技术形成。可例如使用化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)、旋涂、电镀及/或其它适合技术来沉积材料。类似地,可(例如)使用等离子体蚀刻、湿式蚀刻、化学机械平坦化或其它合适技术来移除材料。一些技术可与光刻工艺组合。相关领域的技术人员还将理解,本技术可具有额外实施例,且可在无本文参考图1A到1D、2A、2B及3到6描述的实施例的若干细节的情况下实践本技术。
特定半导体装置(例如,存储器装置)可包含具有存储器单元阵列的区(其还可称为阵列、存储器阵列、阵列区、阵列部分或类似物)及具有外围电路系统的另一区(其还可称为外围装置、外围区、外围部分或类似物)。存储器单元阵列可包含各种类型的存储器单元,例如动态随机存取存储器(DRAM)单元、相变存储器(PCM)单元、快闪存储器单元(例如,NAND单元、NOR单元)等等。外围电路系统可经配置以执行半导体装置的各种功能,包含存取阵列的存储器单元。在一些情况下,鉴于包含在外围电路系统中的互补金属氧化物半导体(CMOS)晶体管,外围区可称为CMOS区(CMOS、CMOS部分、CMOS区等)。另外,或替代地,由于外围电路系统执行的数字逻辑功能的性质,外围区可称为逻辑区。因而,存储器装置可被视为具有阵列区及CMOS区(或外围/逻辑区)等。
通常,存储器装置的裸片尺寸可主要由阵列区的面积及CMOS区的面积确定。因此,研究及开发努力已集中于减小两个面积(例如,垂直堆叠存储器单元(例如,如在三维(3D)NAND存储器技术中))以减小阵列区的面积,或CMOS晶体管按比例调整以减小CMOS区的面积。然而,与制造存储器单元阵列相关联的工艺步骤可包含与用于制造CMOS电路系统的工艺步骤不同的特性。例如,特定CMOS工艺步骤的温度可高于存储器阵列工艺步骤中使用的温度(且可高于存储器阵列可耐受而不损坏的温度)。另外或替代地,与存储器单元阵列相关联的缺陷机制倾向于不同于与CMOS电路相关联的缺陷机制。
因而,本技术的实例实施例涉及将存储器装置的CMOS区及阵列区制造为两个单独的半导体装置(或半导体裸片),以彼此独立地优化CMOS电路系统及存储器单元的制造工艺。此外,两个单独裸片(例如,阵列裸片及CMOS裸片)可垂直地组合(例如,经堆叠以形成一对半导体裸片),使得两个(或更多个)单独裸片组合地可用作单个装置(例如,一个存储器装置)。在一些实施例中,可将两个半导体裸片的前(例如,有源)表面布置成彼此面对以形成所述对,使得可减小CMOS电路系统与存储器单元之间的距离。此外,两个半导体裸片的前表面可经连结以通过在阵列裸片与CMOS裸片之间的界面处的导电组件(例如,铜(Cu)、含铜合金)将CMOS电路系统与阵列的存储器单元耦合。当与具有横向分布的CMOS电路系统及存储器单元的存储器装置相比时,半导体裸片的堆叠(即,半导体裸片堆叠)可提供更小占据面积及改进的性能(例如,由于CMOS电路系统与存储器单元之间的距离减小而减小的延迟时间)。
此外,堆叠的一个裸片(例如,阵列裸片)可经布置以延伸超过其它裸片(例如,CMOS裸片)以产生门廊(例如,未由CMOS装置覆盖的阵列装置的延伸部分),其中可定位存储器装置(即,半导体裸片堆叠)的接合垫。产生门廊的此布置在安置于另一半导体裸片堆叠(例如,半导体裸片堆叠的堆叠)的顶部上的连续半导体裸片堆叠之间提供间隙(或垂直空间)。间隙又可促进接合线连接到定位于门廊中的存储器装置的接合垫,以将接合垫与承载半导体裸片堆叠的堆叠的支撑衬底的衬底接合垫耦合。换句话说,堆叠的半导体裸片中的一者(例如,CMOS裸片)可经配置以提供空间(例如,间隙)以制作到堆叠中的每一半导体裸片堆叠的线接合连接。以此方式,当半导体裸片堆叠经堆叠在彼此顶部上且彼此成一直线时,可形成到堆叠的每一半导体裸片堆叠的线接合,而不增加堆叠的总占据面积(例如,避免叠瓦堆叠配置)。此外,与针对个别存储器装置形成用于将其堆叠在彼此顶部上且彼此成一直线的衬底通路(TSV,还可称为穿硅通路)相比时,到个别半导体裸片堆叠(例如,个别存储器装置)的线接合可提供成本较低的替代方案。
如本文中使用,鉴于图中展示的定向,术语“前”、“后”、“垂直”、“横向”、“向下”、“向上”、“上”及“下”可指半导体装置组合件中的特征的相对方向或位置。例如,“上”或“最上”可指定位成比另一特征更靠近页面顶部的特征。然而,这些术语应广泛地理解以包含具有其它定向的半导体装置。除非另有说明,否则例如“第一”及“第二”的术语用于任意区分此类术语所描述的元件。因此,这些术语不一定希望指示此类元件的时间或其它优先级。此外,尽管在本文中的实例实施例中,使用具有两个裸片(例如,半导体裸片对)的半导体裸片堆叠来清楚地说明本技术的总体特征及原理,但本技术不限于此。例如,在一些实施例中,半导体裸片堆叠可包含承载两个或更多个较小裸片的单个较大裸片。另外,或替代地,由单个较大裸片承载的一或多个较小裸片可包含裸片堆叠。
图1A是具有前侧102及后侧103的半导体装置101的实例示意性横截面视图。半导体装置101可包含衬底104、阵列区105及CMOS(外围或逻辑)区106。阵列区105可包含存储器单元阵列108(DRAM单元、3D NAND单元、NOR单元或类似物)。CMOS区106可包含CMOS电路系统113(命令及/或地址解码器、列解码器、行解码器、感测放大器等),其经配置以存取存储器单元阵列108(或存储器阵列108)。
半导体装置101的横截面视图说明与将阵列区105及CMOS区106定位在共面表面(例如,半导体装置101的前侧102)上相关的问题。例如,在阵列区105与CMOS区106之间传播的信号(例如,在存储器单元阵列108与CMOS电路系统113之间行进不同距离的电压及/或电流)可表现半导体装置101将处置的不同延迟。在这方面,阵列区105包含近单元109a(例如,靠近CMOS区106定位的一或多个存储器单元)及远单元109b(例如,相对远离CMOS区106定位的一或多个存储器单元)。此外,CMOS区106包含近CMOS组件114a(例如,靠近阵列区105定位的行解码器)及远CMOS组件114b(例如,相对远离阵列区105定位的行解码器)。信号传播中的最差情况延迟可在远单元109b与远CMOS组件114b之间,而最佳情况延迟可在近单元109a与近CMOS组件114a之间。可设计各种方案来减小信号传播延迟的范围,例如将近CMOS组件114a与远单元109b耦合且将远CMOS组件114b与近单元109a耦合,将阵列区105分隔为两个或更多个子区,及/或将CMOS区106分隔为两个或更多个子区,使得阵列区105及CMOS区106的子区可穿插等等。
图1B是根据本技术的实施例的半导体裸片对130a(其还可称为半导体裸片堆叠)的实例示意性横截面视图。半导体裸片对130a包含阵列裸片110(存储器单元阵列108在其前侧上)及布置在阵列裸片110的顶部上的CMOS裸片115(CMOS电路系统113在其前侧上),其中阵列裸片110及CMOS裸片115的前侧在界面120处彼此面对。此外,CMOS裸片115及阵列裸片110的前表面可在界面120处连结。阵列裸片110及CMOS裸片115分别包含衬底104a及104b。在一些实施例中,通过使用研磨、抛光、蚀刻或其它合适工艺步骤,当与衬底104b的厚度相比时,阵列裸片110的衬底104a的厚度可已减小(例如,衬底104a的部分已从阵列裸片110的后侧103a移除)。因此,阵列裸片110的衬底104a包含小于CMOS裸片115的衬底104b的第二厚度(T1b)的第一厚度(T1a),在一些实施例中,第二厚度(T1b)可与包含CMOS裸片115的晶片衬底的厚度大致相同。
在一些情况下,半导体裸片对130a可被视为分离成两件(一件对应于阵列裸片110,且另一件对应于CMOS裸片115)且面对面(存储器单元阵列108面向CMOS电路系统113)耦合在一起的半导体装置101,例如,阵列裸片110的后侧103a及CMOS裸片115的后侧103b各自形成半导体裸片对130a的外表面。因而,阵列裸片110可不包含存取存储器单元阵列108的电路系统,因为CMOS裸片115包含经配置以存取存储器单元阵列108的CMOS电路系统113。以此方式,阵列裸片110及CMOS裸片115可组合地用作全功能半导体装置,例如,具有阵列区105及CMOS区106的半导体装置101。此外,阵列裸片110可包含大于CMOS裸片115的第二占据面积的第一占据面积。
阵列裸片110可包含形成在阵列裸片110的前侧上的一或多个第一导电组件,例如,如图2A中描绘,由第一介电材料225围绕的导电组件220。在一些实施例中,第一导电组件可包含铜(Cu)及/或Cu合金。第一导电组件可与存储器单元阵列108耦合。包含阵列裸片110的第一介电材料225的层还可包含导电迹线,以在存储器单元阵列108与第一导电组件之间分布(路由、引导)电信号。类似地,CMOS裸片115可包含形成在CMOS裸片115的前侧上的一或多个第二导电组件,例如,如图2A中描绘,由第二介电材料235围绕的导电组件230。在一些实施例中,第二导电组件可包含铜及/或Cu合金。第二导电组件可与CMOS电路系统113耦合。包含CMOS裸片115的第二介电材料235的层还可包含导电迹线,以在CMOS电路系统与第二导电组件之间分布(路由、引导)电信号。此外,CMOS裸片115可布置在阵列裸片110上方,使得第二导电组件中的每一者可与第一导电组件中的对应者耦合。以此方式,CMOS电路系统113可通过与(例如,直接接合到)第一导电组件耦合的第二导电组件存取存储器单元阵列108。
在一些实施例中,阵列裸片110的第一导电组件中的每一者可在界面120处直接接合到CMOS裸片115的第二导电组件中的对应者。另外,第一介电材料可在界面120处直接接合到第二介电材料。此接合方案(例如,包含直接接合在一起的两个或更多个材料(铜、氮化物及/或氧化物)的接合界面)可称为组合接合方案。此外,CMOS裸片115及阵列裸片110的前表面可视为在界面120处连结。在其它实施例中,第一导电组件中的每一者可通过导电柱、导电凸块、导电球或类似物连接到第二导电组件中的对应者。
半导体裸片对130a包含阵列裸片110的边缘112a,其延伸超过CMOS裸片115的对应边缘117a,使得阵列裸片110的前侧的部分125暴露(例如,未由CMOS裸片115覆盖)。此外,阵列裸片110的部分125可包含半导体裸片对130a的一或多个接合垫145。此外,半导体裸片对130a包含阵列裸片110的边缘112b,其与CMOS裸片115的对应边缘117b成一直线(例如,齐平)。在一些实施例中,阵列裸片110的部分125的区域可基于半导体裸片对130a的接合垫145的数量,例如,以在部分125的区域内容纳所述数量的接合垫145。在其它实施例中,CMOS裸片115可经布置以远离阵列裸片110的两个或更多个边缘与阵列裸片110耦合,使得阵列裸片110的两个或更多个部分可不被CMOS裸片115所覆盖。阵列裸片110的此多个未覆盖部分125可有利地容纳半导体裸片对130a的大量接合垫145,如参考图3更详细地描述。
如在图1B中描绘,阵列裸片110及CMOS裸片115分别包含衬底104a及衬底104b。在一些情况下,衬底104(例如,衬底104a、衬底104b或两者)可从后侧抛光,以减小半导体裸片对130a的总厚度(在图1B中表示为“T1”)。CMOS裸片115的衬底104b可提供相对于堆叠在CMOS裸片115的顶部上的另一半导体裸片(或半导体裸片堆叠)的空间(间隙),其可促进接合线的形成,如参考图1D更详细地描述。例如,CMOS裸片115可包含大于附接到接合垫145的接合线上升高于阵列裸片110的前侧的高度的厚度。
图1C是根据本技术的实施例的半导体裸片对130b(其还可称为半导体裸片堆叠)的实例示意性横截面视图。半导体裸片对130b可为半导体裸片对130a的实例或包含半导体裸片对130a的方面。半导体裸片对130b可对应于移除阵列裸片110的衬底104a的半导体裸片对130a,即,阵列裸片110可不包括衬底。因而,半导体裸片对130b包含CMOS裸片115及存储器单元阵列108。在一些实施例中,支撑结构135可代替衬底104a接合到(或以其它方式附接到)存储器单元阵列108以提供机械支撑。由于移除衬底104a(或用支撑结构135替换衬底104a),半导体裸片对130b的总厚度(在图1C中表示为“T2”)可小于半导体裸片对130a的厚度(T1)。如果两个或更多个半导体裸片对130b堆叠在彼此顶部上以减小堆叠的高度(因此包含堆叠的封装的高度),那么半导体裸片对130b的厚度的此减小可为有利的。
尽管在前述实例中,描述且说明存储器裸片(例如,第一半导体裸片)及CMOS裸片(例如,第二半导体裸片)以形成半导体裸片对以用作单个存储器装置,但本技术不限于此。换句话说,本技术可应用于具有两个或更多个功能层级及/或块的任何半导体装置,其可被分离成各自包含一或多个功能层级及/或块的对应半导体裸片。例如,CPU裸片可包含算术逻辑区及高速缓存区以及支持CPU的各种功能的其它区。本技术可促进将高速缓存区分离成单独半导体裸片(例如,高速缓存裸片),且接着将高速缓存裸片与算术逻辑裸片(例如,CPU裸片除去高速缓存区)组合,使得高速缓存裸片及算术逻辑裸片可连结在一起以形成作为单个CPU操作的半导体裸片堆叠。在其它实例中,GPU可被分隔为两个部分,例如,包含图形及计算阵列的第一部分及包含各种外围电路系统(例如接口块、控制电路块等)的第二部分。因而,第一半导体裸片(包含图形及计算阵列)及第二半导体裸片(包含各种外围电系统路)可单独产生,使得第一及第二半导体裸片可经组合(例如,面对面地彼此堆叠)以形成作为单个GPU操作的半导体裸片堆叠。
此外,尽管在前述实例中,描述且说明存储器裸片110在尺寸上大于CMOS裸片115(例如,存储器裸片110具有大于CMOS裸片115的占据面积的占据面积),使得存储器裸片110可“承载”CMOS裸片115,且包含半导体裸片对130的接合垫,但本技术不限于此。例如,当半导体装置101是具有占据半导体装置101的相对较小面积的嵌入式存储器的控制器时,CMOS裸片可大于阵列裸片。因此,CMOS裸片(包含控制器的各种功能块)的尺寸可大于存储器裸片(包含嵌入式存储器),使得CMOS裸片可承载存储器裸片并包含用于半导体裸片对的接合垫。
图1D是根据本技术的实施例的包含半导体裸片对堆叠(其还可称为半导体裸片堆叠)的半导体裸片组合件170的实例示意性横截面视图。半导体裸片组合件170包含堆叠中的两个半导体裸片对(例如,半导体裸片对130a-1、半导体裸片对130a-2)。半导体裸片对130a-1及130a-2可为参考图1B描述的半导体裸片对130a的实例或包含其的方面。半导体裸片组合件170进一步包含支撑衬底150,半导体裸片对堆叠附接到支撑衬底150。在一些实施例中,可在两个相邻半导体裸片对之间添加粘合层以形成堆叠,例如,在半导体裸片对130a-1与半导体裸片对130a-2之间添加粘合层140。支撑衬底150包含一或多个衬底接合垫(例如,衬底接合垫155,展示其中的一者)。此外,半导体裸片组合件170包含将半导体裸片对的个别接合垫(例如,半导体裸片对130a-1的接合垫145a、半导体裸片对130a-2的接合垫145b)耦合到对应衬底接合垫155的接合线(例如,接合线160a及160b)。
半导体裸片对的堆叠可经配置以包含空间(在图1D中表示为“S”),使得接合线(例如,接合线160a)可连接到半导体裸片对的接合垫(例如,半导体裸片对130a-1的接合垫145a)而不必干扰定位于上方的半导体裸片(例如,半导体裸片对130a-2的阵列裸片110b)。在一些实施例中,空间经配置以允许线接合头到达接合垫(例如,接合垫145a),而不触碰半导体裸片对130a-2的阵列裸片110b的后侧。通过实例,接合线160a的最高部分与半导体裸片对130a-2的阵列裸片110b的后侧分开达一距离D。在一些情况下,CMOS裸片115可包含大于附接到接合垫145(例如,接合垫145a)的接合线160上升高于阵列裸片110的前侧的高度(表示为“H”)的厚度(表示为“T3”)。在一些情况下,除了CMOS裸片115a的厚度(例如,T3)之外,空间S可包含粘合层140的厚度。只要空间S(T3与粘合层140的厚度的总和)大于H,便可用线接合技术制作到每一半导体裸片对(例如,堆叠中的多个半导体裸片对)的电连接,此可提供经实施以在垂直堆叠的半导体装置中传输信号的TSV的低成本替代方案。
尽管图1D中所描绘的前述实例包含两(2)个半导体裸片对130a,但在其它实施例中,半导体裸片对的堆叠可包含比两个(例如,四(4)、六(6)、八(8)、十二(12)或甚至更多个)更多的数量。此外,尽管图1D中的半导体裸片对堆叠说明堆叠成直线的两(2)个半导体裸片对130a(例如,以最小化堆叠的占据面积),但在其它实施例中,半导体裸片对堆叠可形成为叠瓦式图案(或阶梯式图案)。此外,在一些实施例中,一或多个半导体裸片对130可相对于彼此旋转90度、180度或270度,使得半导体裸片对130a的接合垫可更容易地接取(例如,通过接合线)。
在一些实施例中,半导体裸片组合件可包含第一对裸片(例如,半导体裸片对130a-1),其包含附接到第二裸片(例如,阵列裸片110a)的第一裸片(例如,CMOS裸片115a),其中第一及第二裸片的前表面连结(例如,在界面120a连结),且第二裸片的前表面包含未由第一裸片覆盖的第一延伸部分(例如,延伸部分125a),第一延伸部分包含第一组接合垫(例如,接合垫145a,在图1D中展示其中的一者)。此外,半导体裸片组合件可包含由第一对半导体裸片承载的第二对裸片(例如,半导体裸片对130a-2),所述第二对包含附接到第四裸片(例如,阵列裸片110b)的第三裸片(例如,CMOS裸片115b),其中第三及第四裸片的前表面连结(例如,在界面120b连结),且第四裸片的前表面包含未由第三裸片覆盖的第二延伸部分(例如,延伸部分125b),第二延伸部分包含第二组接合垫(例如,接合垫145b,在图1D中展示其中的一者)。
在一些实施例中,半导体裸片组合件可包含支撑衬底(例如,支撑衬底150),第一对中的第二裸片(例如,阵列裸片110a)的后侧附接到支撑衬底,支撑衬底包含多个衬底接合垫(例如,衬底接合垫155,在图1D中展示其中的一者)。此外,半导体裸片组合件可包含:多个第一接合线(例如,接合线160a,在图1D中展示其中的一者),其将第一组接合垫的个别接合垫(例如,接合垫145a)与多个衬底接合垫的对应衬底接合垫(例如,衬底接合垫155)耦合;及多个第二接合线(例如,接合线160b,在图1D中展示其中的一者),其将第二组接合垫的个别接合垫(例如,接合垫145b)与多个衬底接合垫的对应衬底接合垫(例如,衬底接合垫155)耦合。
在一些实施例中,第二裸片包含第一存储器单元阵列(例如,存储器单元阵列108a),不包括经配置以存取第一存储器单元阵列的电路系统,且第一裸片包含经配置以存取第二裸片的第一存储器单元阵列的第一外围电路系统(例如,CMOS电路系统113a)。在一些实施例中,第一裸片及第二裸片的前表面各自包含多个导电组件(例如,图2A中描绘的导电组件220及230),且第一裸片的个别导电组件与第二裸片的对应导电组件连结。此外,第一裸片的外围电路系统(例如,CMOS电路系统113a)可经配置以通过多个导电组件的一或多个经连结导电组件来存取第二裸片的存储器单元阵列(例如,存储器单元阵列108a)。
类似地,第四裸片包含第二存储器单元阵列(例如,存储器单元阵列108b),不包括经配置以存取第二存储器单元阵列的电路系统,且第三裸片可包含经配置以存取第四裸片的第二存储器单元阵列的第二外围电路系统(例如,CMOS电路系统113b)。此外,第三裸片的外围电路系统(例如,CMOS电路系统113b)可经配置以通过包含在第三及第四裸片的前表面的一或多个经连结导电组件(例如,图2A中描绘的导电组件220及230)来存取第四裸片的存储器单元阵列(例如,存储器单元阵列108b)。
在一些实施例中,第二对的占据面积与第一组接合垫(例如,接合垫145a)重叠,且第一裸片(例如,CMOS裸片115a)的厚度经配置以为多个第一接合线(例如,接合线160a)提供间隙以与第四裸片(例如,阵列裸片110b)的后侧分开达一距离。此外,间隙可包含定位于第四裸片的后侧与第一裸片的后侧之间的粘合剂(例如,粘合层140)的厚度。在一些实施例中,间隙经配置以允许线接合头到达第一组的接合垫(例如,接合垫145a),而不触碰第四裸片的后侧。因此,在形成将第一组的接合垫耦合到多个的对应衬底接合垫(例如,衬底接合垫155)的接合线之前,可形成半导体裸片对130a的堆叠(例如,附接到半导体裸片对130a-1的半导体裸片对130a-2)。
图2A是包含第一半导体裸片210及第二半导体裸片215的半导体裸片堆叠205的实例示意性三维视图。半导体裸片堆叠205可为半导体裸片对130(例如,半导体裸片对130a、半导体裸片对130b)的实例,或包含参考图1A到1D描述的半导体裸片对130的方面。此外,第一半导体裸片210及第二半导体裸片215可分别为存储器裸片110及CMOS裸片115的实例或包含其的方面。第一半导体裸片210包含前表面(或前侧)211及后表面(或后侧)212。类似地,第二半导体裸片215包含前表面(或前侧)216及后表面(或后侧)217。第一半导体裸片210包含延伸部分255(例如,参考图1A到1D描述的部分125)及延伸部分255中的一组接合垫240(例如,参考图1A到1D描述的接合垫145)。
在一些实施例中,第一半导体裸片210可包含存储器单元阵列,不包括经配置以存取存储器单元阵列的电路系统。第二半导体裸片215可包含CMOS电路系统,其经配置以存取第一半导体裸片210的存储器单元阵列,例如,通过经配置以将存储器单元阵列与CMOS电路系统耦合的一或多个导电组件。在一些实施例中,第一半导体裸片210包含在第一半导体裸片210的前侧211上的一或多个第一导电组件220(第一导电组件220的另外细节在放大示意性横截面图206中说明),其中第一导电组件220与第一半导体裸片210的存储器单元阵列耦合。此外,第二半导体裸片215可包含在第二半导体裸片215的前侧216上的一或多个第二导电组件230(第二导电组件230的另外细节在图206中说明),其中第二导电组件230与第二半导体裸片215的CMOS电路系统耦合。此外,第二半导体裸片215经布置在第一半导体裸片210上方,使得第二导电组件230中的每一者直接接合到第一导电组件220中的对应者。
参考图206,在一些实施例中,围绕第一导电组件220中的每一者的第一介电材料225可直接接合到围绕第二导电组件230中的每一者的第二介电材料235。此接合配置(例如,第一半导体裸片210的前侧211与第二半导体裸片215的前侧216之间的界面,包含第一与第二导电组件220及230之间的直接接合界面245以及第一与第二介电材料225及235之间的直接接合界面250)可被称为组合接合配置。在一些实施例中,第一及第二介电材料225及235可包含额外导电特征(例如,金属组件及迹线,包含铜、Cu合金、钨、铝或类似物),以分别将来自存储器单元阵列及CMOS电路系统的电信号分布(例如,路由、引导)到第一导电组件220及第二导电组件230。
此外,第一半导体裸片210的边缘可延伸超过第二半导体裸片215的对应边缘,使得第一半导体裸片210的前侧211的部分(例如,部分255)暴露,其中所述部分包含所述一组接合垫240(例如,接合垫145)。第一半导体裸片210进一步包含导电迹线241,导电迹线241将接合垫240连接到与第二导电组件230耦合的第一导电组件220。在一些实施例中,第二半导体裸片215的CMOS电路系统可通过直接接合到第一导电组件220的第二导电组件230存取第一半导体裸片210的存储器单元阵列。
在一些实施例中,第一半导体裸片210可不包括如参考图1C在半导体裸片对130b中所描述的半导体衬底,即,第一半导体裸片可包含存储器单元阵列(例如,存储器单元阵列108),其可附接到支撑结构(例如,支撑结构135)。在一些实施例中,第二半导体裸片215包含大于附接到所述一组接合垫240的接合线上升高于第一半导体裸片210的前侧211的高度的厚度。在一些实施例中,第一半导体裸片210包含大于第二半导体裸片215的第二占据面积的第一占据面积。在一些实施例中,第一半导体裸片210的后侧212附接到包含多个衬底接合垫(例如,衬底接合垫155)的支撑衬底(例如,支撑衬底150、图2B中描绘的支撑衬底260)。此外,多个接合线(例如,接合线160)可将个别接合垫240与对应衬底接合垫耦合。
图2B是半导体裸片组合件275的实例示意性三维视图,半导体裸片组合件275包含附接到支撑衬底260(例如,支撑衬底150)的半导体裸片堆叠(例如,半导体裸片对130、半导体裸片堆叠205)的堆叠。半导体裸片组合件275可为半导体裸片组合件170的实例或包含半导体裸片组合件170的方面。图2B中描绘的堆叠包含四(4)个半导体裸片堆叠205(例如,半导体裸片堆叠205a到205d),但在其它实施例中,堆叠可包含较少量的半导体裸片堆叠(例如,三(3)、两(2)个)或较大量的半导体裸片堆叠(例如,六(6)、十二(12)或甚至更多个)。如本文中描述,包含面对面堆叠的阵列裸片及CMOS裸片的个别半导体裸片堆叠205可为存储器装置(例如,当与参考图1描述的半导体装置101相比时)提供更小占据面积及改进的性能。此外,包含具有接合垫(例如,接合垫145、接合垫240)的延伸部分255的半导体裸片堆叠205可促进将两个或更多个半导体裸片堆叠205堆叠成直线以减少堆叠的占据面积(例如,当与具有叠瓦堆叠图案的堆叠相比时),以及将接合线(例如,接合线160、接合线270)形成到堆叠中的个别半导体裸片堆叠205,例如,将个别接合垫240与对应衬底接合垫265耦合。
图3说明根据本技术的实施例的半导体裸片堆叠的各种平面视图300。每一图包含第一半导体裸片310(例如,阵列裸片11O、第一半导体裸片210)、第二半导体裸片315(例如,CMOS裸片115、第二半导体裸片215)、一或多个延伸(或暴露)部分355(例如,部分125、部分255)、一组接合垫340(例如,接合垫145、接合垫240)以及一组接合线360(接合线160、接合线270)。图300描绘基于例如以下若干因素在半导体裸片堆叠中形成延伸(暴露)部分的各种选项:第一及第二半导体裸片的裸片尺寸、半导体裸片堆叠的接合接合的数量、半导体裸片堆叠的占据面积、第一半导体裸片310及/或第二半导体裸片315的形状等等。
例如,图300a可对应于半导体裸片对130及/或半导体裸片堆叠205的堆叠配置,例如,产生单个延伸部分355。在一些实施例中,如果接合垫的数量显著大于图300a中所描绘的半导体裸片堆叠的数量,那么图300c可有利于形成半导体裸片堆叠,例如,产生四(4)个延伸部分355a到355d,其具有半导体裸片堆叠的增加的占据面积。在又一实施例中,如果接合垫的数量适度大于图300a中所描绘的半导体裸片堆叠的数量,那么图300b可有利于形成半导体裸片堆叠,例如,产生两(2)个延伸部分355a及355b。
为了说明目的,图300提供形成半导体裸片堆叠的堆叠配置的各种实例,且本技术不限于此。例如,第二半导体裸片315可相对于第一半导体裸片310旋转(例如90度),以为暴露部分355提供更宽区域,即,第二半导体裸片315的一或多个边缘可位于第一半导体裸片310的对应边缘外部。换句话说,半导体裸片堆叠可具有悬垂在第一半导体裸片310的边界之外的第二半导体裸片315的一些部分。在一些情况下,此布置可基于半导体裸片堆叠的接合垫的数量与占据面积(例如,半导体裸片堆叠的总尺寸)之间的折衷。此外,尽管接合垫340被描绘在单个列(及/或行)中,但接合垫340可布置在多个列(及/或行)中。在一些情况下,多列(或行)接合垫中的每一列(或行)可相对于彼此偏移,以提供接合线到接合垫的更容易接取。
图4说明描述根据本技术的实施例的制作半导体裸片堆叠的实例工艺步骤的图400a到c。图400a展示在其前侧包含多个第一裸片场412的第一半导体晶片411及在其前侧包含多个第二裸片场417的第二半导体晶片416。在一些实施例中,第一裸片场412中的每一者对应于第一裸片410(例如,阵列裸片110),其包含存储器单元阵列(例如,存储器单元阵列108),不包括经配置以存取存储器单元阵列的电路系统。此外,第二裸片场417中的每一者可具有与第一裸片场412中的每一者相同的面积。第二裸片场417中的每一者可对应于第二裸片415(例如,CMOS裸片115)及相邻于第二裸片415的第二半导体晶片的片段435(或一部分)。在一些实施例中,第二裸片415包含经配置以存取第一裸片410的存储器单元阵列的CMOS电路系统。此外,第一及第二裸片的前表面中的每一者可包含多个导电组件,例如,分别为第一导电组件220、第二导电组件230。
在一些实施例中,第二半导体晶片416可翻转并带过第一半导体晶片411,使得第一及第二晶片411及416的前侧可彼此面对。随后,包含第一裸片410的第一半导体晶片411可布置在包含第二裸片415的第二半导体晶片416上方(或包含第二裸片415的第二半导体晶片416可布置在包含第一裸片410的第一半导体晶片411上方),使得第一裸片410的导电组件中的每一者对准于第二裸片415的导电组件中的对应者。随后,可将第一半导体晶片411接合到第二半导体晶片416以将第一裸片410的导电组件中的每一者直接接合到第二裸片415的导电组件中的对应者。此外,围绕第一裸片410的导电组件中的每一者的第一介电材料可直接接合到围绕第二裸片415的导电组件中的对应者的第二介电材料(例如,形成参考图2A描述的组合接合配置)。图400b描绘接合完成后的单个裸片场,其中单个裸片场包含接合到第二裸片415的第一裸片410。
在一些实施例中,在接合第一半导体晶片411及半导体晶片416之后,可移除第二半导体晶片416的片段435,以暴露第一裸片410的一组接合垫440(例如,接合垫145、接合垫240、接合垫340)。换句话说,移除片段435产生第一裸片410的延伸部分455(例如,延伸部分125、延伸部分255、延伸部分355),其中所述一组接合垫440如图400c中所描绘般定位。在一些实施例中,移除片段435可包含通过使用切割工艺(例如,通过切割穿过第二裸片415与片段435之间的边界425将片段435与第二裸片415分开),结合利用经配置以分别单粒化第一及第二半导体晶片411及416的个别裸片场412及417的其它切割道而从第二裸片415切断片段435。此后,可(例如)通过使用清洁工艺从第二半导体晶片416(接合到第一晶片411)移除分离的片段435。以此方式,第一及第二裸片410及415在晶片级连结以形成半导体裸片堆叠,其中第一裸片410的前表面与第二裸片415的前表面直接接触,且其中第一裸片410的前表面包含未由第二裸片415覆盖的第一延伸部分455。延伸部分包含一组接合垫440。
在一些实施例中,移除片段435可包含通过使用蚀刻工艺从第二裸片415切断片段435(或以其它方式移除或脱离片段435)。在一些情况下,光刻工艺可用光致抗蚀剂覆盖第二裸片415,同时暴露对应于片段435的区段430。随后,蚀刻工艺可移除未由光致抗蚀剂覆盖的片段435。在其它情况下,光刻工艺可暴露包含边界425的第二半导体晶片416的区段。随后,蚀刻工艺可通过产生沟槽而将片段435与第二裸片415分离,其中沟槽的宽度包含边界425,且沟槽的深度大致对应于第二半导体晶片416的厚度。此后,可使用清洁工艺结合利用其它切割道移除分离的片段435,所述切割道经配置以分别单粒化第一及第二半导体晶片411及416的个别裸片场412及417。
在其它实施例中,第二半导体晶片416的个别第二裸片场417可对应于第二裸片415,例如,无与第二裸片415相邻的片段435。因此,第二裸片场417的面积可小于对应于第一裸片410的第一裸片场412的面积。个别第一裸片410可从第一半导体晶片411单粒化,且个别第二裸片415可从第二半导体晶片416单粒化。此后,第二裸片415可经布置于第一裸片410上方,使得将第一裸片410的导电组件中的每一者对准于第二裸片415的导电组件中的对应者。此外,第二裸片415可接合到第一裸片410以将第一裸片410的导电组件中的每一者直接接合到第二裸片415的导电组件中的对应者以形成半导体裸片堆叠,如在图400c中展示。
图5是示意性说明包含根据本技术的实施例配置的半导体装置组合件的系统570的框图。参考图1B、1C及2A描述的半导体裸片堆叠(例如,半导体裸片堆叠130a、130b、205)可包含在参考图1D及2B描述的半导体装置组合件500(例如,半导体装置组合件170、半导体装置组合件275)中。半导体装置组合件500可并入到大量更大及/或更复杂系统中的任一者中,所述系统的代表性实例是图5中示意性展示的系统570。系统570可包含半导体装置组合件500、电源572、驱动器574、处理器576及/或其它子系统或组件578。
包含在半导体装置组合件500中的半导体裸片堆叠可具有通常类似于包含面对面堆叠的阵列裸片及CMOS裸片的半导体裸片堆叠205的特征,包括用于半导体装置组合件500的更小占据面积及改进的性能(例如,当与半导体装置101相比时)。此外,包含于半导体装置组合件500中的半导体裸片堆叠可包含具有可促进将两个或更多个半导体裸片堆叠堆叠成一直线以减少堆叠的占据面积(例如,当与具有叠瓦堆叠图案的堆叠相比时)以及将接合线形成到堆叠中的个别半导体裸片堆叠(例如,形成TSV的低成本替代方案)的接合垫(例如,接合垫145、接合垫240)的延伸部分。所得系统570可执行多种功能中的任一者,例如存储器存储、数据处理及/或其它适合功能。因此,代表性系统570可包含(但不限于)手持式装置(例如,移动电话、平板计算机、数字阅读器及数字音频播放器)、计算机及电子设备。系统570的组件可容置于单个单元中或分布于多个、互连单元(例如,通过通信网络)上方。系统570的组件还可包含远程装置及多种计算机可读媒体中的任一者。
图6是根据本技术的实施例的制造半导体裸片对的方法的流程图600。流程图600可包含如参考图4描述的方法的方面。
方法包含提供包含存储器单元阵列的第一裸片,不包括经配置以存取存储器单元阵列的电路系统(方框610)。方法进一步包含提供包含经配置以存取第一裸片的存储器单元阵列的CMOS电路系统的第二裸片(方框615)。方法进一步包含:连结第一及第二裸片以形成第一对裸片,其中第一裸片的前表面与第二裸片的前表面直接接触,其中第一裸片的前表面包含未由第二裸片覆盖的第一延伸部分,第一延伸部分包含第一组接合垫,且第一及第二裸片的前表面各自包含多个导电组件,第一裸片的导电组件中的每一者直接接合到第二裸片的导电组件中的对应者,且围绕第一裸片的导电组件中的每一者的第一介电材料直接接合到围绕第二裸片的导电组件中的对应者的第二介电材料(方框620)。方法进一步包含将第一对裸片附接到包含多个衬底接合垫的支撑衬底(方框625)。
在一些实施例中,连结第一及第二裸片包含:将包含第一裸片的第一半导体晶片布置在包含第二裸片的第二半导体晶片上方,使得第一裸片的导电组件中的每一者对准于第二裸片的导电组件中的对应者;将第一半导体晶片接合到第二半导体晶片以将第一裸片的导电组件中的每一者直接接合到第二裸片的导电组件中的对应者;及在将第一半导体晶片接合到第二半导体晶片之后,移除第二半导体晶片的相邻于第二裸片的部分,所述部分对应于第一裸片的第一延伸部分。在一些实施例中,移除第二半导体晶片的所述部分包含:通过使用蚀刻工艺、切割工艺或两者从第二裸片切断所述部分;及从第二半导体晶片移除经切断的部分。在一些实施例中,连结第一及第二裸片包含:将第二裸片布置在第一裸片上方,使得第一裸片的导电组件中的每一者对准于第二裸片的导电组件中的对应者;及将第二裸片接合到第一裸片以将第一裸片的导电组件中的每一者直接接合到第二裸片的导电组件中的对应者。
在一些实施例中,方法可进一步包含:形成多个第一接合线以将第一组接合垫中的个别接合垫与多个衬底接合垫中的对应衬底接合垫耦合;及在形成所述多个第一接合线之后,将第二对裸片附接到所述第一对裸片,第二对包含与第四裸片连结的第三裸片,其中第三及第四裸片的前表面彼此直接接触,且所述第三裸片的前表面包含未由第四裸片覆盖的第二延伸部分,所述第二延伸部分包含第二组接合垫,且所述第三及第四裸片的前表面各自包含多个导电组件,第三裸片的导电组件中的每一者直接接合到第四裸片的导电组件中的对应者,且围绕第三裸片的导电组件中的每一者的第三介电材料直接接合到围绕第四裸片的导电组件中的对应者的第四介电材料。
在一些实施例中,方法可进一步包含将第二对裸片附接到所述第一对裸片,第二对包含与第四裸片连结的第三裸片,其中第三及第四裸片的前表面彼此直接接触,且所述第三裸片的前表面包含未由第四裸片覆盖的第二延伸部分,所述第二延伸部分包含第二组接合垫,且所述第三及第四裸片的前表面各自包含多个导电组件,第三裸片的导电组件中的每一者直接接合到第四裸片的导电组件中的对应者,且围绕第三裸片的导电组件中的每一者的第三介电材料直接接合到围绕第四裸片的导电组件中的对应者的第四介电材料。方法可进一步包含在将第二对裸片附接到第一对裸片之后形成多个第一接合线,以将第一组接合垫的个别接合垫与多个衬底接合垫的对应衬底接合垫耦合。
应注意,上文所描述的方法描述可能实施方案,且操作及步骤可经重新布置或以其它方式修改,且其它实施方案是可行的。此外,可组合来自所述方法中的两者或更多者的实施例。从前文将了解,在本文中已为说明的目的描述本技术的特定实施例,但可在不脱离公开内容的情况下做出各种修改。另外,虽然在所说明的实施例中,特定特征或组件已展示为具有特定布置或配置,但其它布置及配置是可能的。此外,在特定实施例的上下文中描述的本技术的特定方面还可在其它实施例中组合或消除。
本文中论述的装置(包含半导体装置)可形成在半导体衬底(例如硅、锗、硅锗合金、砷化镓、氮化镓等)上。在一些情况中,衬底是半导体晶片。在其它情况中,衬底可为绝缘体上硅(SOI)衬底,例如玻璃上硅(SOG)或蓝宝石上硅(SOP),或在另一衬底上的半导体材料的外延层。可通过使用各种化学物种(包含(但不限于)磷、硼或砷)进行掺杂来控制衬底或衬底的子区的导电性。掺杂可在衬底的初始形成或生长期间通过离子植入或通过任何其它掺杂手段执行。
如本文中所使用(包含在权利要求书中),如在项目列表(例如,以例如“…中的至少一者”或“…中的一或多者”的词组开始的项目列表)中使用的“或”指示包含性列表,使得例如A、B或C中的至少一者的列表意味着A或B或C或AB或AC或BC或ABC(即,A及B及C)。此外,如本文中所使用,词组“基于”不应被解释为参考条件闭集。例如,在不脱离本公开的范围的情况下,描述为“基于条件A”的示范性步骤可基于条件A及条件B两者。换句话说,如本文中使用,词组“基于”应以相同于词组“至少部分基于”的方式来解释。
根据上文,将了解,已出于说明目的在本文中描述本发明的特定实施例,但可在不偏离本发明的范围的情况下作出各种修改。实际上,在以上描述中,论述数种特定细节以提供对本公开的实施例的透彻且实现描述。然而,相关领域的技术人员将认识到,可在不具有特定细节中的一或多者的情况下实践本公开。在其它例子中,未展示或详细描述通常与存储器系统及装置相关联的众所周知结构或操作以避免模糊本公开的其它方面。一般来说,应理解,除本文中公开的特定实施例以外的各种其它装置、系统及方法可在本公开的范围内。
Claims (20)
1.一种半导体裸片组合件,其包括:
第一半导体裸片,其包含存储器单元阵列,不包括经配置以存取所述存储器单元阵列的电路系统;及
第二半导体裸片,其包含互补金属氧化物半导体(CMOS)电路系统,所述电路系统经配置以存取所述第一半导体裸片的所述存储器单元阵列,其中:
所述第一半导体裸片包含一或多个第一导电组件及所述第一半导体裸片的前侧上的一组接合垫,所述第一导电组件与所述存储器单元阵列耦合;
所述第二半导体裸片包含所述第二半导体裸片的前侧上的一或多个第二导电组件,所述第二导电组件与所述CMOS电路系统耦合;
所述第二半导体裸片经布置在所述第一半导体裸片上方,使得所述第二导电组件中的每一者与所述第一导电组件中的对应者直接接合;及
所述第一半导体裸片的边缘延伸超过所述第二半导体裸片的对应边缘,使得所述第一半导体裸片的所述前侧的部分暴露,所述部分包含所述一组接合垫。
2.根据权利要求1所述的半导体裸片组合件,其中围绕所述第一导电组件中的每一者的第一介电材料直接接合到围绕所述第二导电组件中的每一者的第二介电材料。
3.根据权利要求1所述的半导体裸片组合件,其中所述第一半导体裸片不包括半导体衬底。
4.根据权利要求1所述的半导体裸片组合件,其中所述CMOS电路系统通过直接接合到所述第一导电组件的所述第二导电组件存取所述存储器单元阵列。
5.根据权利要求1所述的半导体裸片组合件,其中所述第二半导体裸片包含大于附接到所述一组接合垫的接合线上升高于所述第一半导体裸片的所述前侧的高度的厚度。
6.根据权利要求1所述的半导体裸片组合件,其中所述第一半导体裸片包含大于所述第二半导体裸片的第二占据面积的第一占据面积。
7.根据权利要求1所述的半导体裸片组合件,其进一步包括:
支撑衬底,所述第一半导体裸片的后侧附接到所述支撑衬底,所述支撑衬底包含多个衬底接合垫;及
多个接合线,其将所述一组接合垫中的个别接合垫与所述多个衬底接合垫中的对应衬底接合垫耦合。
8.一种半导体裸片组合件,其包括:
第一对裸片,其包含附接到第二裸片的第一裸片,其中所述第一及第二裸片的前表面连结,且所述第二裸片的所述前表面包含未由所述第一裸片覆盖的第一延伸部分,所述第一延伸部分包含第一组接合垫;
第二对裸片,其由所述第一对半导体裸片承载,所述第二对包含附接到第四裸片的第三裸片,其中所述第三及第四裸片的前表面连结,且所述第四裸片的所述前表面包含未由所述第三裸片覆盖的第二延伸部分,所述第二延伸部分包含第二组接合垫;
支撑衬底,所述第一对的所述第二裸片的后侧附接到所述支撑衬底,所述支撑衬底包含多个衬底接合垫;
多个第一接合线,其将所述第一组接合垫的个别接合垫与所述多个衬底接合垫的对应衬底接合垫耦合;及
多个第二接合线,其将所述第二组接合垫中的个别接合垫与所述多个衬底接合垫中的对应衬底接合垫耦合。
9.根据权利要求8所述的半导体裸片组合件,其中:
所述第一及第二裸片的所述前表面各自包含多个导电组件,且所述第一裸片的个别导电组件与所述第二裸片的对应导电组件连结;及
所述第一裸片的外围电路系统经配置以通过所述多个导电组件中的一或多个经连结导电组件来存取所述第二裸片的存储器单元阵列。
10.根据权利要求8所述的半导体裸片组合件,其中:
所述第二裸片包含第一存储器单元阵列,不包括经配置以存取所述第一存储器单元阵列的电路系统;及
所述第四裸片包含第二存储器单元阵列,不包括经配置以存取所述第二存储器单元阵列的电路系统。
11.根据权利要求8所述的半导体裸片组合件,其中:
所述第一裸片包含经配置以存取所述第二裸片的第一存储器单元阵列的第一外围电路系统;及
所述第三裸片包含经配置以存取所述第四裸片的第二存储器单元阵列的第二外围电路系统。
12.根据权利要求8所述的半导体裸片组合件,其中所述第二对的占据面积与所述第一组接合垫重叠,且所述第一裸片的厚度经配置以为所述多个第一接合线提供间隙以与所述第四裸片的后侧分开达一距离。
13.根据权利要求12所述的半导体裸片组合件,其中所述间隙包含定位于所述第四裸片的所述后侧与所述第一裸片的后侧之间的粘合剂的厚度。
14.根据权利要求12所述的半导体裸片组合件,其中所述间隙经配置以允许线接合头到达所述第一组的所述接合垫,而不触碰所述第四裸片的所述后侧。
15.一种方法,其包括:
提供第一裸片,其包含存储器单元阵列,不包括经配置以存取所述存储器单元阵列的电路系统;
提供第二裸片,其包含互补金属氧化物半导体(CMOS)电路系统,所述电路系统经配置以存取所述第一裸片的所述存储器单元阵列;
连结所述第一及第二裸片以形成第一对裸片,其中:
所述第一裸片的前表面与所述第二裸片的前表面直接接触,且所述第一裸片的所述前表面包含未由所述第二裸片覆盖的第一延伸部分,所述第一延伸部分包含第一组接合垫;及
所述第一及第二裸片的所述前表面各自包含多个导电组件,所述第一裸片的所述导电组件中的每一者直接接合到所述第二裸片的所述导电组件中的对应者,且围绕所述第一裸片的所述导电组件中的每一者的第一介电材料直接接合到围绕所述第二裸片的所述导电组件中的所述对应者的第二介电材料;及
将所述第一对裸片附接到包含多个衬底接合垫的支撑衬底。
16.根据权利要求15所述的方法,其中连结所述第一及第二裸片包含:
在包含所述第二裸片的第二半导体晶片上方布置包含所述第一裸片的第一半导体晶片,使得所述第一裸片的所述导电组件中的每一者对准到所述第二裸片的所述导电组件中的所述对应者;
将所述第一半导体晶片接合到所述第二半导体晶片,以将所述第一裸片的所述导电组件中的每一者直接接合到所述第二裸片的所述导电组件中的所述对应者;及
在将所述第一半导体晶片接合到所述第二半导体晶片之后,移除与所述第二裸片相邻的所述第二半导体晶片的部分,所述部分对应于所述第一裸片的所述第一延伸部分。
17.根据权利要求16所述的方法,其中移除所述第二半导体晶片的所述部分包含:
通过使用蚀刻工艺、切割工艺或两者从所述第二裸片切断所述部分;及
从所述第二半导体晶片移除所述切断部分。
18.根据权利要求15所述的方法,其中连结所述第一及第二裸片包含:
在所述第一裸片上方布置所述第二裸片,使得所述第一裸片的所述导电组件中的每一者对准到所述第二裸片的所述导电组件中的所述对应者;及
将所述第二裸片接合到所述第一裸片,以将所述第一裸片的所述导电组件中的每一者直接接合到所述第二裸片的所述导电组件中的所述对应者。
19.根据权利要求15所述的方法,其进一步包括:
形成多个第一接合线,以将所述第一组接合垫中的个别接合垫与所述多个衬底接合垫中的对应衬底接合垫耦合;及
在形成所述多个第一接合线之后,将第二对裸片附接到所述第一对裸片,所述第二对裸片包含与第四裸片连结的第三裸片,其中:
所述第三及第四裸片的前表面彼此直接接触,且所述第三裸片的所述前表面包含未由所述第四裸片覆盖的第二延伸部分,所述第二延伸部分包含第二组接合垫;及
所述第三及第四裸片的所述前表面各自包含多个导电组件,所述第三裸片的所述导电组件中的每一者直接接合到所述第四裸片的所述导电组件中的对应者,且围绕所述第三裸片的所述导电组件中的每一者的第三介电材料直接接合到围绕所述第四裸片的所述导电组件中的所述对应者的第四介电材料。
20.根据权利要求15所述的方法,其进一步包括:
将第二对裸片附接到所述第一对裸片,所述第二对裸片包含与第四裸片连结的第三裸片,其中:
所述第三及第四裸片的前表面彼此直接接触,且所述第三裸片的所述前表面包含未由所述第四裸片覆盖的第二延伸部分,所述第二延伸部分包含第二组接合垫;及
所述第三及第四裸片的所述前表面各自包含多个导电组件,所述第三裸片的所述导电组件中的每一者直接接合到所述第四裸片的所述导电组件中的对应者,且围绕所述第三裸片的所述导电组件中的每一者的第三介电材料直接接合到围绕所述第四裸片的所述导电组件中的所述对应者的第四介电材料;及
在将所述第二对裸片附接到所述第一对裸片之后形成多个第一接合线,以将所述第一组的个别接合垫与所述多个衬底接合垫中的对应衬底接合垫耦合。
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