CN116633469A

CN116633469A - Time synchronization module and multi-node server

Info

Publication number: CN116633469A
Application number: CN202310348943.2A
Authority: CN
Inventors: 张华�; 江柳
Original assignee: XFusion Digital Technologies Co Ltd
Current assignee: XFusion Digital Technologies Co Ltd
Priority date: 2023-03-31
Filing date: 2023-03-31
Publication date: 2023-08-22

Abstract

The embodiment of the application provides a time synchronization module and a multi-node server, and relates to the technical field of computing equipment. The time synchronization module comprises a phase-locked loop circuit, a receiver, a first input interface and a plurality of output interfaces, wherein the first input interface is connected with the input end of the receiver, the output end of the receiver is connected with the signal input end of the phase-locked loop circuit, the signal output end of the phase-locked loop circuit is connected with each output interface, and the output interfaces are used for being connected with a server node; the receiver is used for receiving a source signal from the satellite positioning system from the first input interface and extracting a clock source from the source signal; the phase-locked loop circuit is used for generating time information synchronizing signals corresponding to the server nodes according to the clock source and outputting the time information synchronizing signals to the corresponding output interfaces so that the server nodes correspondingly perform clock or time synchronization according to the time information synchronizing signals.

Description

Time synchronization module and multi-node server

Technical Field

The present application relates to the field of computing devices, and in particular, to a time synchronization module and a multi-node server.

Background

The popularization of the 5G technology accelerates the arrival of the universal interconnection age, the sinking of the server at the edge side is promoted, the calculation power requirement of the server is continuously improved, and the space at the edge side is limited, so that the multi-node server at the edge side needs to have higher performance. For example, networking scenarios for many latency sensitive services require multi-node servers to have high accuracy time synchronization performance.

However, to expand the marketized application and reasonable control cost, the multi-node server in the current industry is mostly based on a general server design, and generally only supports time synchronization based on network time protocol (network time protocol, NTP), and the synchronization accuracy is in millisecond (ms) level, but cannot meet the requirement of higher accuracy time synchronization.

Disclosure of Invention

The embodiment of the application provides a time synchronization module, a multi-node server, a time synchronization method thereof, a computer storage medium and a computer program product, which can achieve higher-precision clock and time synchronization of the server and have high universality.

In a first aspect, an embodiment of the present application provides a time synchronization module, where the time synchronization module includes a phase-locked loop circuit, a receiver, a first input interface and a plurality of output interfaces, the first input interface is connected to an input end of the receiver, an output end of the receiver is connected to a signal input end of the phase-locked loop circuit, a signal output end of the phase-locked loop circuit is connected to each output interface, and the output interfaces are used to connect to a server node; the receiver is used for receiving a source signal from the satellite positioning system from the first input interface and extracting a clock source from the source signal; the phase-locked loop circuit is used for generating time information synchronous signals corresponding to each server node according to the clock source and outputting the time information synchronous signals to the corresponding output interface.

In this embodiment, the source signal received by the first input interface may include a clock source, a time source, and the like, from which the receiver extracts the clock source and transmits the clock source to the phase-locked loop circuit for locking, so as to serve as a local clock reference source, and then output corresponding time synchronization information for each server node, so as to realize time synchronization of the server nodes. It will be appreciated that the time synchronization information includes at least a synchronization clock and may also include a synchronization time.

In some possible implementations, the time synchronization module further includes a second input interface, where the second input interface is configured to connect the signal input terminal of the phase-locked loop circuit with at least one first server node, and the second input interface is configured to receive a clock source sent by the first server node and transmit the clock source to the phase-locked loop circuit.

In some possible implementations, the time synchronization module further includes a third input interface, the third input interface being configured to connect the phase-locked loop circuit signal input terminal to the at least one second server node, the third input interface being configured to receive a clock source transmitted by the second server node and transmit the clock source to the phase-locked loop circuit.

In some possible implementations, the time synchronization module further includes a frequency processing circuit, and the signal output end of the at least one phase-locked loop circuit is electrically connected to each server node through the frequency processing circuit; the phase-locked loop circuit synthesizes the time information synchronous signals of the frequencies needed by the corresponding server nodes through the corresponding frequency processing circuits.

In a second aspect, an embodiment of the present application provides a multi-node server, where the multi-node server includes a time synchronization module and a plurality of server nodes, the time synchronization module is provided with at least one input interface and a plurality of output interfaces, the time synchronization module is correspondingly connected to each server node through the plurality of output interfaces, and the time synchronization module is configured to generate, according to a clock source input from the input interface, a time information synchronization signal corresponding to each server node, and transmit the time information synchronization signal to each server node through the corresponding output interface.

In some possible implementations, the input interface includes a first input interface, and the time synchronization module further includes a receiver coupled to the first input interface for receiving a source signal from the satellite positioning system via the first input interface and extracting a corresponding clock source from the source signal.

In some possible implementations, the plurality of server nodes includes a first server node, and the input interface of the time synchronization module includes a second input interface; the first server node is provided with a clock source generating module which is connected with the second input interface; the first server node is used for receiving a source signal from the satellite positioning system through the clock source generation module, extracting a corresponding clock source from the source signal and inputting the clock source into the time synchronization module.

In some possible implementations, the plurality of server nodes includes a second server node connection, and the input interface of the time synchronization module includes a third input interface; the second server node is provided with a message processing module which is connected with a third input interface; the second server node is used for receiving timing protocol PTP message from the external clock network through the message processing module, extracting a clock source from the PTP message and inputting the clock source into the time synchronization module.

In some possible implementations, the multi-node server further includes a back plane, on which the first connector and the second connector are disposed, one first connector being connected to at least one second connector; each input interface of the time synchronization module is connected with a first connector, and a second connector is connected with a corresponding server node.

In some possible implementations, the back plane of the multi-node server is also provided with a universal interface; the universal interface is used to connect the server nodes.

In some possible implementations, the multi-node server further includes a system management unit, where the system management unit is electrically connected to the time synchronization module and each server node, and the system management unit is configured to obtain synchronization requirement information of each server node, where the synchronization requirement information is used to characterize a time synchronization requirement and/or a clock synchronization requirement of a corresponding server node; the system management unit is further configured to configure the synchronization requirement information in the time synchronization module, so that the time synchronization module outputs a time information synchronization signal corresponding to the respective synchronization requirement information for each server node.

In some possible implementations, the time synchronization module includes a phase-locked loop circuit, where a plurality of signal input ends of the phase-locked loop circuit are connected to corresponding input interfaces, and the phase-locked loop circuit receives a switching signal sent by the system management unit, and performs clock source switching from clock sources input by each input interface according to the switching signal and a preset clock source priority ranking.

In some possible implementations, the time synchronization module is further configured to switch to a corresponding next clock source according to a preset priority ranking of the clock sources when the monitored state of the current clock source does not reach the health indicator.

In a third aspect, an embodiment of the present application provides a time synchronization method, including: acquiring a source signal, wherein the source signal at least comprises a clock source; and generating a local clock of the multi-node server according to the clock source, and outputting corresponding time information synchronization signals for each server node of the multi-node server based on the local clock.

In some possible implementations, the multi-node server includes a time synchronization module, where the time synchronization module includes a receiver and a phase-locked loop circuit, the obtaining a source signal is obtained by the receiver, and generating a local clock of the multi-node server according to a clock source includes: a clock source extracted from the source signal by the receiver; the local clock is generated from a clock source by a phase-locked loop circuit.

In some possible implementations, the multi-node server includes a time synchronization module, the time synchronization module includes a phase-locked loop circuit, a signal input end of the phase-locked loop circuit is connected with at least one first server node of the multi-node server, the first server node is a server node capable of receiving a source signal, and generating a local clock of the multi-node server according to a clock source includes: a clock source extracted from the source signal by the first server node; the local clock is generated from a clock source by a phase-locked loop circuit.

In some possible implementations, the multi-node server includes a time synchronization module, the time synchronization module includes a phase-locked loop circuit, a signal input end of the phase-locked loop circuit is connected with at least one second server node of the multi-node server, the second server node is a server node having a capability of receiving a timing protocol PTP message from an external clock network and extracting a source signal from the PTP message, and the generating a local clock of the multi-node server according to a clock source includes: a clock source extracted from the source signal by the second server node; the local clock is generated from a clock source by a phase-locked loop circuit.

In some possible implementations, outputting, for each server node of the multi-node server, a corresponding time information synchronization signal based on the local clock, includes: invoking synchronous demand information of each server node, wherein the synchronous demand information is used for representing synchronous clock or time required by the corresponding server node and clock frequency required by the corresponding server node; based on the local clock, outputting time information synchronization signals corresponding to the respective synchronization requirement information for each server node, so that each server node correspondingly performs clock or time synchronization according to the respective time information synchronization signals.

In some possible implementations, there are multiple source signals when the source signals are acquired; after acquiring the source signal, the method comprises: and acquiring a switching signal, sequencing according to the switching signal and a preset clock source priority, and switching the clock sources from the clock sources of the source signals to generate a local clock according to the switched clock sources.

In some possible implementations, after acquiring the source signal, the method includes: determining the health state of a current clock source according to a health index, wherein the health index comprises the existence of the current clock source, and when the clock source exists, the frequency of the clock source is within a preset frequency value; when the health state of the current clock source reaches the health index, determining that the clock source can be used for generating a local clock; and when the monitoring state of the current clock source does not reach the health index, switching to the corresponding next clock source according to the preset priority order of the clock sources.

In some possible implementations, each server node is connected to a downstream device through ethernet communication, and generates a time information synchronization signal of each server node based on the local clock, so that each server node performs clock or time synchronization according to the respective time information synchronization signal, including: each server node generates a timing protocol PTP message according to the corresponding time information synchronizing signal, wherein the timing protocol PTP message comprises a clock or time information of the corresponding time information synchronizing signal;

and sending the timing protocol PTP message to downstream equipment through the Ethernet so that the downstream equipment synchronizes a clock or time according to the corresponding PTP message.

In a fourth aspect, the present application provides an electronic device comprising: at least one memory for storing a program; at least one processor for executing programs stored in the memory; wherein the processor is adapted to perform the method described in the third aspect or any one of the possible implementations of the third aspect, when the program stored in the memory is executed.

In a fifth aspect, the present application provides a computer readable storage medium storing a computer program which, when run on a processor, causes the processor to perform the method described in the third aspect or any one of the possible implementations of the third aspect.

In a sixth aspect, the application provides a computer program product, characterized in that the computer program product, when run on a processor, causes the processor to perform the method described in the third aspect or any one of the possible implementations of the third aspect.

In a seventh aspect, the present application provides a chip, comprising at least one processor and an interface; at least one processor obtains program instructions or data through an interface; at least one processor is configured to execute program line instructions to implement the method described in the third aspect or any one of the possible implementations of the third aspect.

It will be appreciated that the advantages of the second to sixth aspects may be found in the relevant description of the first aspect, and are not described here again.

Drawings

Fig. 1 is a schematic diagram of an application scenario with time synchronization according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a time synchronization module according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a time synchronization module according to another embodiment of the present application;

FIG. 4 is a schematic diagram of a time synchronization module according to another embodiment of the present application;

FIG. 5 is a schematic diagram of a multi-node server according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a multi-node server according to an embodiment of the present application;

FIG. 7 is a signal trace schematic diagram of the multi-node server shown in FIG. 6 for time synchronization;

FIG. 8 is a schematic diagram illustrating a configuration of a multi-node server according to another embodiment of the present application;

FIG. 9 is a signal trace schematic diagram of the multi-node server shown in FIG. 8 for time synchronization;

FIG. 10 is a schematic diagram of a multi-node server according to another embodiment of the present application;

FIG. 11 is a signal trace schematic diagram of the multi-node server shown in FIG. 10 for time synchronization;

FIG. 12 is a flowchart of a time synchronization method according to an embodiment of the present application;

FIG. 13 is a flow chart of a method for time synchronization according to an embodiment of the present application;

FIG. 14 is a flow chart of a method for time synchronization according to an embodiment of the present application;

fig. 15 is a schematic structural diagram of a time synchronization device according to an embodiment of the present application;

fig. 16 is a schematic structural diagram of a chip according to an embodiment of the present application.

Detailed Description

The term "and/or" herein is an association relationship describing an associated object, and means that there may be three relationships, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. The symbol "/" herein indicates that the associated object is or is a relationship, e.g., A/B indicates A or B.

The terms "first" and "second" and the like in the description and in the claims are used for distinguishing between different objects and not for describing a particular sequential order of objects. For example, the first response message and the second response message, etc. are used to distinguish between different response messages, and are not used to describe a particular order of response messages.

In embodiments of the application, words such as "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g." in an embodiment should not be taken as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

In the description of the embodiments of the present application, unless otherwise specified, the meaning of "plurality" means two or more, for example, the meaning of a plurality of processing units means two or more, or the like; the plurality of elements means two or more elements and the like.

In order to facilitate understanding of the technical solution of the present application, technical terms related to the embodiments of the present application are first explained below.

Time synchronization, also called phase synchronization (phase synchronization), means that both the frequency and phase between signals remain consistent, i.e. the phase difference between the signals is constant at zero.

Frequency synchronization (frequency synchronization), also called clock synchronization, refers to the maintenance of a certain strict specific relationship in frequency or phase between signals that occur at the same average rate at their corresponding effective instants to ensure that all devices in the communication network are operating at the same rate, i.e., that a constant phase difference is maintained between the signals.

The high-precision timing protocol (precision timing protocol, PTP) is a time synchronization protocol, which complies with the IEEE1588v2 protocol standard, can be used for high-precision time synchronization between devices, and can also be borrowed for frequency synchronization between devices. The principle is that the PTP protocol establishes a master-slave system among clocks in the system, and the time of the clocks in the system is derived from an optimal master clock (best master clock). The optimal master clock exchanges PTP messages with the slave clock, and the slave clock calculates clock deviation and network delay between the slave clock and the master clock through hardware timestamp information carried in the PTP messages, so that second pulse synchronization can be completed, and the time synchronization precision can reach sub microsecond level.

The global positioning system (global positioning system, GPS), a high-precision radio navigation positioning system based on satellites, provides accurate geographic location and accurate time information anywhere in the world and near earth space.

The network time protocol (network time protocol, NTP) is a protocol used to synchronize computer time, which can synchronize the computer to its server or clock source (e.g., quartz clock, GPS, etc.), and the synchronization accuracy can reach sub-second level.

PCIe, PCI-Express (peripheral component interconnect express), is a high-speed serial computer expansion bus standard. PCIe belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission, where connected devices allocate independent channels, do not share bus bandwidth, and mainly support functions such as active power management, error reporting, end-to-end reliability transmission, hot plug, and quality of service (QOS).

The time synchronization time service card, also called time service card for short, is a PCIe time service board card provided for a computer or a standard time server, and can be suitable for different cases and different operating systems. The time source of the time service card can comprise a GPS, a Beidou satellite navigation system, a CDMA (Code Division Multiple Access) communication system and the like, the time service card receives standard clock signal information, and the computer is automatically time-calibrated through a serial port and simultaneously generates a synchronous pulse signal, such as a 1PPS (second signal) synchronous pulse signal.

Time of day (ToD), which is essentially a serial time interface protocol, generally uses serial RS232/422 to communicate, and may be called ToD as long as the communication protocol contains information such as time of year, month, day, minute, second, etc. The ToD signal is a signal that can represent information such as time of year, month, day, minute, and second.

The general multi-node server is only realized by focusing on the server function, and does not consider the high-precision time synchronization characteristic of the telecommunication scene and does not have the time clock synchronization function, so that the synchronous mode adopted in the service networking is that an NTP clock network can be built in a special external clock server mode. The clock server is in Ethernet communication with a plurality of clients, acquires a clock source from a GPS system, exchanges secondary messages with the clients, determines time deviation of master clock and slave clock, and the clients calibrate local computer time to complete time synchronization. Therefore, the NTP synchronization method mainly completes synchronization of time information through software and algorithm, the main working interval is mainly in the application layer, when the process of transmitting from the physical layer to the application layer or the process of transmitting from the application layer to the physical layer, the synchronization information may be blocked by the process, delay is caused, when a message is transmitted, the transmission time recorded by the message is not accurate time, thus, although a clock server can provide an NTP clock signal with higher precision, if a transmission network between master and slave nodes is a common ethernet network, the final clock synchronization precision can only reach ms precision.

In addition, in other available synchronization modes, a time service card in the form of a PCIe label card can be inserted into a server to perform time service synchronization, but because the server only plays a role of a console, the server can not be effectively used together with other components on the current server, and the high-precision time synchronization function of the multi-node service can not be established.

Therefore, in the networking scenario of delay sensitive services, the server is difficult to achieve higher-precision clock time synchronization.

In order to improve the time synchronization precision of a multi-node server in a delay sensitive service networking scene, the embodiment of the application provides a time synchronization method. The time synchronization module can be arranged on a master node server in a clock network or on a slave node server, and is beneficial to realizing the universal application of the server with time synchronization capability.

In order to facilitate understanding of the technical solution of the embodiment of the present application, at least one application scenario of the embodiment of the present application is first described below.

Fig. 1 is a schematic diagram illustrating a scenario in which an edge side builds a clock network based on a multi-node server according to an embodiment of the present application. As shown in fig. 1, in the clock network, at least one Master node server (hereinafter also referred to as a Master node or Master node) 10 may be included, and a plurality of slave node servers (hereinafter also referred to as slave nodes or slave nodes) 20 may be included, where the Master node 10 communicates with each slave node 20 through an ethernet network, and the Master node 10 may be a server or a server cluster disposed on an edge side, each slave node 20 may be a server or a server cluster on a next stage of the Master node 10, or may be an edge device (such as a personal computer), and the slave node 20 may also connect to the next stage edge device 30 through the ethernet network.

In this example, taking the master node 10 as a multi-node server as an example, a PTP time synchronization module 110 supporting the IEEE1588 protocol may be built in the master node 10, and the PTP time synchronization module 110 may be communicatively connected to each server node (120 a,120b, …) inside the server. As a specific example, the PTP time synchronization module 110 can acquire a high precision source signal (which may be a source time signal or a source clock signal) from the GPS, beidou, etc. satellite positioning system 40, and generate a local clock based on the source signal to synchronize the time (which may include the clock) of each server node (120 a,120b, …) inside. Next, each server node (120 a,120b, …) in the master node 10 may generate a PTP packet based on the synchronized time, and send the PTP packet to the downstream slave node server 20, where the packet carries hardware timestamp information when the generated packet is sent, so that the slave node 20 can calculate clock deviation and network delay with the master node 10 according to the hardware timestamp information carried by the packet, to implement clock and time synchronization. Because the transmission precision of the IEEE1588v2 protocol is high, each node server (10, 20) in the supporting clock network accurately records the hardware time stamp when receiving and transmitting the message, the delay in the message transmission process is very low, and even if partial delay exists, the time stamp information can be adjusted, so that the high-precision clock and time synchronization can be achieved.

In this example, each of the slave node servers 20 may be multi-node servers, and the PTP time synchronization module 210 may be included in the slave node 20. The PTP time synchronization module 210 in the slave node 20 may be communicatively connected to the respective nodes (220 a,220b, …) within it. As a specific example, one server node 220a inside the slave node 20 may obtain the PTP packet (carrying the timestamp information) of the master node 10 from the ethernet port, and extract a high-precision clock from the packet, and send the high-precision clock to the PTP time synchronization module 210 in the slave node 20, where the PTP time synchronization module 210 locks the clock (i.e. is a local clock) and synchronizes the time and clock of other server nodes (220 b, …) inside.

Next, a time synchronization module provided by an embodiment of the present application is described.

Fig. 2 is a schematic structural diagram of a time synchronization module 101 according to an embodiment of the present application. As shown in fig. 2, the time synchronization module 101 includes a phase-locked loop circuit 1011 and a first input interface 1013, and the first input interface 1013 is electrically connected to a signal input terminal of the phase-locked loop circuit 1011. The first input interface 1013 may be configured to obtain a source signal, where the source signal includes at least a clock source, and in other examples, a time source, etc. The phase-locked loop circuit 1011 may generate a local clock of the multi-node server where the module is located according to the source signal input from the first input interface 1013, and then output a corresponding time information synchronization signal for each server node of the multi-node server based on the local clock, where the time information synchronization signal may include a synchronization clock or a synchronization time, so as to correspondingly implement clock or time synchronization of the server nodes. As an example, the multi-node server node where the time synchronization module 101 is located may be a master node in a clock network, such as the master node 10 shown in fig. 1, and then the time synchronization module 101 may be the time synchronization module 110 shown in fig. 1, and the multi-node server node where the time synchronization module 101 is located may also be a slave node in the clock network, such as the slave node 20 shown in fig. 1, and then the time synchronization module 101 may be the time synchronization module 210 shown in fig. 1.

The first input interface 1013 may be an antenna interface, for example. The phase-locked loop circuit 1011 may be an all-digital phase-locked loop (DPLL), but is not limited thereto. The phase-locked loop circuit 1011 may transceive corresponding time and clock signals in compliance with the IEEE1588v2 protocol standard.

In some embodiments, as shown in fig. 3, when the first input interface 1013 is an antenna interface, the time synchronization module 101 further includes a receiver 1012, and the receiver 1012 is electrically connected between the antenna interface and a signal input terminal of the phase-locked loop circuit 1011. The receiver 1012 may be configured to receive a high-precision source signal (including a clock source, a time source, etc.) from a satellite positioning system such as GPS, beidou, etc. via the first input interface 1013 (to which an antenna is connected), and extract a high-precision clock source (which may include a clock and a 1pps pulse signal) from the source signal, and send the extracted high-precision clock source to the phase-locked loop circuit 1011, where the phase-locked loop circuit 1011 may lock the clock source to generate a new local clock. Thus, after the phase-locked loop generates a new local clock, the phase-locked loop can output a synchronous clock with corresponding frequency according to the synchronous requirement of each server node of the server where the module is located. In addition, the time source (which may include the ToD signal) extracted from the source signal of the receiver may be directly used as the synchronization time to be sent from the current module to each server node, or may be used as the local time reference source to generate the local time, and then output the corresponding synchronization time to each server node based on the local time, so as to realize synchronization of the clock and the time.

In some embodiments, as shown in fig. 3, the time synchronization module 101 may also include a second input interface 1014. As an example, the second input interface 1014 may be a serial communication interface such as RS232/422, through which the signal input end of the phase-locked loop circuit 1011 in the time synchronization module 101 may be connected to one or more first server nodes in the server currently located, where the first server nodes are server nodes capable of receiving the source signal, so that the time synchronization module 101 may receive the clock source sent by the first server nodes based on the second input interface 1014 and transmit the clock source to the phase-locked loop circuit 1011. As an example, the first server node may implement the capability to receive the source signal of the satellite positioning system via a time service card or the like, and may extract the clock source and the time source from the source signal and send the clock source and the time source to the time synchronization module 101 via the second input interface 1014, so that the time synchronization module 101 outputs the synchronization time and the time for each server node based on a principle similar to that described above.

In some embodiments, the time synchronization module 101 may further include an input interface (also referred to as a third input interface) such as a cable interface or a backplane connector, through which a signal input of the phase-locked loop circuit 1011 in the time synchronization module 101 may be connected to at least one second server node of the multi-node server, where the second server node is a server node capable of receiving a timing protocol PTP packet from an external clock network and extracting a source signal (including a clock source, a time source, etc.) from the PTP packet. As an example, the second server node may receive, through an ethernet port of the IEEE1588v2 protocol, a PTP packet sent by a master node in the clock network, extract a source signal clock source, a time source, and the like from the PTP packet, and send the same to the time synchronization module 101 via a cable interface or a backplane connector, so that the time synchronization module 101 outputs a synchronization time and a time for each server node based on a principle similar to that described above.

In some embodiments, the time synchronization module 101 may also include a plurality of frequency processing circuits, such as the synthesizers (Synth 1, synth2, …) shown in fig. 4, but is not limited thereto. As an example, referring to fig. 4, signal output terminals of the phase-locked loop circuit 1011 are electrically connected to the server nodes through respective frequency synthesizers (Synth 1, synth2, …), respectively, in one-to-one correspondence; in this way, the phase-locked loop circuit 1011 synthesizes a synchronization signal of a frequency required for the corresponding server node by the corresponding frequency synthesizer (Synth 1, synth2, …).

In some embodiments, at the time synchronization module 101, the signal output end of the phase-locked loop circuit 1011 may be correspondingly connected to a plurality of server nodes through a plurality of output interfaces 1015 to perform transmission time information synchronization signals with the respective server nodes. The output interface 1015 may be a cable interface or a universal connector, and furthermore, in some examples, multiple output interfaces 1015 may be integrated on one connector.

Next, a description will be given of a server provided in an embodiment of the present application.

Fig. 5 shows a schematic structural diagram of a server 100 according to an embodiment of the present application. As shown in fig. 5, the server 100 may include a time synchronization module 101, one or more server nodes (102 a,102b, … …), and a system management unit 103, where each server node (102 a,102b, … …) may be communicatively connected to the time synchronization module 101 via a cable or a backplane, and each server node (102 a,102b, … …) and the time synchronization module 101 may be communicatively connected to the system management unit 103.

The system management unit 103 may be a complete machine controller (rackmanagement control, abbreviated as RMC), and information transmission between the system management unit 103 and each server node (102 a,102b, … …) and the time synchronization module 101 may be implemented through a physical channel (or a cable). The system management unit 103 may be configured to monitor node information (including, but not limited to, node ethernet interface type, applicable clock frequency, node temperature, etc.), status (including, but not limited to, node clock status, ethernet interface status of the node, power allocation status on the node, etc.), etc. of each server node (102 a,102b, … …), and may also be configured to configure signal selection and distribution policies of the time synchronization module 101, etc. In some other examples, the system management unit 103 may also be a management device or management board, such as an out-of-band controller (baseboardmanagement controller, BMC), with similar RMC functionality as described above, but is not limited thereto. By way of example, the following only exemplifies the RMC as the system management unit 103.

Each server node (102 a,102b, … …) may include: processor 1021, memory 1022, and communication interface 1023, memory 1022 and communication interface 1023 may each be communicatively coupled to processor 1021. Wherein: the processor 1021 is a computing core and a control core of a server node, and the processor 1021 may be a central processing unit (central processing unit, CPU), a System On Chip (SOC), an application specific integrated circuit (application specific integrated circuit, ASIC), a field programmable gate array (field programmable gate array, FPGA), a digital signal processor (digital signal processor, DSP), or the like. Memory 1022 is a server node memory device for storing programs and data, such as some node information data, etc. It is appreciated that the memory 1022 may be a high speed RAM memory or a non-volatile memory (non-volatile memory), such as at least one disk memory; memory 1022 provides storage space that stores the operating system and executable program code of the server node, which may include, but is not limited to: windows system, linux system, hong Mony System (Harmony OS), etc., without limitation. The communication interface 1023 may include a standard network interface (such as a wired interface like an ethernet interface or a wireless interface like a mobile communication interface), and may also include a bus interface, such as an RS422 interface, a PCIe bus interface, etc., but is not limited thereto. The communication interface 1023 may be used to transceive, transmit data, for example, to acquire a clock signal of the time synchronization module 101 to send downstream, or to acquire a clock signal transferred by other internal devices to transmit to the time synchronization module 101, etc.

In addition, the server nodes (102 a,102b, … …) may further include one or more PCIe network cards (also referred to as PCIe standard cards or PCIe cards) and open source computing OCP (open compute project) network cards according to the functions to be implemented, so as to enable the self nodes to communicate with other external devices, where these network cards are all connected to the processor through buses.

The respective server nodes (102 a,102b, …) described above may be front-end server nodes, such as, but not limited to, blade server nodes.

The processor 1021 of each server node (102 a,102b, …) may communicate with the system management unit 103 via a backplane or a cable, report or be monitored by the system management unit 103 reading the relevant node information and status information, etc. In addition, each server node (102 a,102b, …) may also be communicatively coupled to the time synchronization module 101 via a backplane or cable. Wherein, the liquid crystal display device comprises a liquid crystal display device,

in this embodiment, the time synchronization module 101 may be a PTP time synchronization module 101 conforming to the IEEE1588v2 protocol standard, which is a core of clock/time management in the server 100 and can be used to control the selection and distribution of clock/time sources. Specifically, the time synchronization module 101 is capable of acquiring a source clock signal or a source time signal, generating a local clock, and synchronizing the clocks and times of local respective server nodes (102 a,102b, …), so that the respective server nodes (102 a,102b, …) can exchange PTP messages (carrying time stamp information for transmitting the messages) downstream, and synchronize the clocks or times downstream. Illustratively, the source signals acquired by the time synchronization module 101 may include clock and time signals from a satellite positioning system such as GPS, beidou, etc., or network timing signals from various server nodes (102 a,102b, …), but are not limited thereto. In addition, the time synchronization module 101 may be deployed as a modularized component on a management board where the system management unit 103 is located, or may be separately and removably deployed in a complete system, and hung on a system management bus to be managed by the system management unit 103 on the management board.

By way of example, the time synchronization module 101 may include at least one input interface, a plurality of output interfaces, and a phase-locked loop circuit 1011, from which the phase-locked loop circuit 1011 may obtain at least one source time signal (i.e., a signal including a clock, a 1pps pulse signal, and a Tod) or a source clock signal (i.e., a clock source including a clock and a 1pps pulse signal), and select one of the source signals to generate a local clock.

The phase-locked loop circuit 1011 may be an all-digital phase-locked loop (DPLL), but is not limited thereto. The phase-locked loop circuit 1011 may transceive corresponding time and clock signals in compliance with the IEEE1588v2 protocol standard. In some specific examples, please continue to refer to the schematic structure of a time synchronization module 101 provided by the embodiment of the present application shown in fig. 4, as shown in fig. 4, a plurality of input terminals of a phase-locked loop circuit 1011 in the time synchronization module 101 may respectively receive a local high-precision clock signal OCXO, a timing signal BITS input from a bus interface (such as an RS422 interface) of a panel where the local high-precision clock signal OCXO is located, a GPS clock signal from a GPS system, a plurality of clock signals Line extracted from PTP messages by server nodes (102 a,102b, …), and the phase-locked loop circuit 1011 may select one of the high-precision clock signals to synchronize the local clock. Then, by means of frequency synthesizers (Synth 1, synth2, …) corresponding to the respective server nodes (102 a,102b, …), clock and time synchronization is realized based on the clock signals and time signals of frequencies required by the nodes synthesized correspondingly based on the updated local clocks. Wherein each frequency synthesizer (Synth 1, synth2, …) may define a plurality of outputs, the relevant definition of which may be referred to in table 1 below.

TABLE 1

As shown in table 1, at least two signal lines may be defined at the output ends of the respective frequency synthesizers (Synth 1, synth2, …) to output as the signals of the aforementioned "1588v2_pps_out", "1588v2_tod_out" and "sync_clk_out", and one signal line may be occupied by each signal, or may be multiplexed with the "1588v2_pps_out" and the "1588v2_tod_out". Correspondingly, corresponding signal lines are also constructed on the PCB board of each server node (102 a,102b, …) to acquire these signals, for example, the "158v2_pps_in", "158v2_tod_in" and "sync_clk_in" signal lines are constructed on the PCB board of each server node (102 a,102b, …) to acquire the three signals IN table 1 output by the corresponding frequency synthesizer.

It will be appreciated that the server 100 shown in fig. 4 may be referred to as the master node 10 shown in fig. 1 and that the time synchronization module 101 and the respective server nodes (102 a,102b, …) in the server 100 may be referred to as the time synchronization module 110 and the respective server nodes (120 a,120b, …) in the master node 10. Of course, the server 100 shown in fig. 5 may serve as the slave node 20 shown in fig. 1 described above, and the time synchronization module 101 and the respective server nodes (102 a,102b, …) in the server 100 may serve as the time synchronization module 210 and the respective server nodes (220 a,220b, …) in the master node 20.

Further, it is understood that the structure of the server 100 shown in fig. 5 does not constitute a limitation of the server 100, and more or fewer components may be included in the server 100, or some components may be combined, or some components may be split, or different component arrangements may be included. For example, the server 100 shown in fig. 5 may further include a power module (PSU), a fan module, and the like, which are removably disposed in the server 100 and collectively managed by the system management unit 103.

Next, based on what has been described above, one possible implementation of the server provided by the embodiment of the present application will be described.

Fig. 6 is a schematic structural diagram of a multi-node server according to an embodiment of the present application. It will be appreciated that the multi-node server 100 may act as a master node server in a clock network, for example as master node 10 shown in fig. 1. Referring to FIG. 6, the multi-node server 100 includes a time synchronization module 101, a plurality of server nodes (102 a,102b,102 c), and an RMC103a, it being understood that more or fewer server nodes may be included in the server 100, and only the nodes 102a,102b,102c are illustrated in FIG. 6.

In this example, the time synchronization module 101 may include a phase-locked loop circuit 1011 and a first input interface (i.e., antenna interface) 1013, and further include a receiver 1012, where the phase-locked loop circuit 1011 is communicatively connected to the receiver 1012, and where the receiver 1012 may receive high-precision source signals from the GPS, beidou, etc. satellite positioning system 40. The receiver 1012 transmits clock sources (clock and 1pps pulses) in advance from the source signal of the satellite positioning system to the phase-locked loop circuit 1011, so that the phase-locked loop circuit 1011 locks one of the clock sources and clock reference sources such as the original local clock signals to generate a new high-precision local clock to synchronize clocks of the respective server nodes (102 a,102b,102 c). The receiver 1012 may also extract the ToD signal from the received source time as a local time reference source to update the local time. The receiver 1022 may be of modular construction and separately managed and status monitored by the RMC103a, and the receiver 1012 may be a GPS receiver, for example, receiving source signals via a GPS antenna on a panel.

In some specific examples, a server node, such as node 102a, may include a processor 1021a, and a PCIe network card 1024 coupled to the processor 1021a via a PCIe bus, the PCIe network card 1024 may be used to connect external devices via an ethernet network. As shown in fig. 6, in the PCB main board where the node is located, a PCIe slot 106 capable of being connected to a connector 1041 on the back board 104 is provided, so that the PCIe slot 106 can be jumped to a PCIe network card 1024 requiring time synchronization or clock synchronization through a cable 105, and then the PCIe network card 1024 can acquire a required synchronization clock and a time signal from the time synchronization module 101 through the back board 104. Thus, if no device requiring time synchronization is arranged on the node 102a, the cable can be disconnected, the design difficulty and cost of the node main board are reduced, and the deployment flexibility of the PCB circuit is improved.

Illustratively, the PCIe network card 1024 on the node 102a may be replaced with an OCP network card, and in this example, the time synchronization function of the current node may be implemented by redefining the PCIe slot and the OCP pin (reserved signal in the OCP3.0 standard) of the OCP network card, by way of example and not limitation, one specific example of pin redefinition is shown in table 2 below.

TABLE 2

As shown in table 2, the pins of the standard PCIE slot and the pins of the serial numbers and names in the standard OCP3.0 pins may be redefined for names, level formats, signal directions, and the like, so as to implement integration of the OCP network card on the node motherboard.

Illustratively, the PCIe network card 1024 on the node 102a may be replaced with a custom card, a riser card, or the like, but is not limited thereto.

In some specific examples, a server node, such as node 102b, may include a processor 1021b, where the processor 1021b is coupled to an OCP network card 1025 via a PCIe bus, where the processor 1021b is further coupled to two 10GE (gigabit) ethernet ports 107, and where the OCP network card 1025 and the ethernet ports 107 may each be used to connect external devices via ethernet. In this example, the processor 1021b may be connected to the PTP time synchronization module 101 through a connector 1041 on the back plane 104, and may have a synchronization clock/time function, and the acquired synchronization clock signal and time signal may be sent to the network card 1025 or the network port 107 with a time synchronization requirement, so as to be used for communicating with an external synchronization time clock network.

In some specific examples, a server node, such as node 102c, may include a processor (which may be a switch chip) 1021c, where the processor 1021c is connected to the PTP time synchronization module 101 through the back plane 104 to have a synchronization clock/time function, and the acquired synchronization clock signal and time signal may be sent to the network port 107 with a time synchronization requirement for communication with an external synchronization time clock network.

The process of time synchronization by the server 100 as a master node in a clock network is described below in conjunction with the time synchronization diagram shown in fig. 7. It will be appreciated that since PTP time synchronization itself includes clock synchronization, all of the time synchronization processes of the embodiments of the present application described herein are also applicable to clock synchronization processes.

In this example, as shown in fig. 7, the receiver 1012 acquires the GPS source time signal X01 of the satellite positioning system 40, and extracts a clock, a 1pps pulse signal, and a ToD signal therefrom, the receiver 1012 transmits the clock and the 1pps pulse signal to the phase-locked loop circuit 1011, the phase-locked loop circuit 1011 locks the clock in the signal X01, and generates a new local clock based on the whole second time indicated by the 1pps pulse signal, and then outputs a synchronization clock of a corresponding frequency and a 1pps synchronization pulse signal according to the frequency characteristics of a device or a portal having a time synchronization requirement on each server node (102 a,102b,102 c). In addition, for the ToD signal extracted by the receiver 1012, if the local time does not need to be updated, the time synchronization module 101 may directly send the ToD signal to each server node (102 a,102b,102 c) together with the synchronization clock, 1pps synchronization pulse, update the local time with the ToD signal as a reference source if the local time has an update requirement, and generate a synchronized ToD signal after the update, and send the synchronized ToD signal to each server node (102 a,102b,102 c) together with the synchronization clock, 1pps synchronization pulse

For example, based on the frequency of the PCIe network card 1024, the phase-locked loop circuit 1011 may distribute the latency signal X02 to one of the ethernet ports 107 on the node 102b and the latency signal X04 to one of the ethernet ports 107 on the node 102c for time synchronization of the PCIe network card 1024 (and the ethernet devices at the next stage thereof). In an example, the synchronous time signals sent by the phase-locked loop circuit 1011 to each server node may include a clock signal, a 1pps synchronization pulse signal, and a ToD signal (or the above synchronous ToD signal), where the clock signal may be set to a corresponding frequency according to the node requirement, and the 1pps synchronization pulse signal and the ToD signal may be selectively sent according to whether time synchronization is to be performed, and if only clock synchronization is performed, the ToD signal may not be sent.

In this way, each node (102 a,102b,102 c) has a time that is synchronized with the time synchronization module 101 with high precision, and then can generate a PTP packet based on the respective obtained synchronization time signals (X02, X03, X04), in which the PTP packet carries hardware timestamp information of the generated packet, which is sent from the ethernet to each of the downstream slave nodes in the external clock network based on the IEEE1588 protocol. The slave node receives the PTP message Wen Shiji and records the hardware time stamp information, analyzes the corresponding synchronous time signal from the PTP message, and performs delay check sum adjustment by utilizing the time stamp recorded by the slave node and the time stamp in the message when receiving the message, thereby obtaining the high-precision slave node local clock time.

In this embodiment, a PTP time synchronization module of the master node may support high precision time clock requirements of multiple server nodes at the same time, so that the integration level is higher, and it is beneficial to construct a clock network with higher performance.

Next, another possible implementation of the server provided by the embodiment of the present application is described based on the above description.

Fig. 8 is a schematic structural diagram of a multi-node server according to an embodiment of the present application. Referring to fig. 8, the server 100 shown in fig. 8 is different from the server 100 shown in fig. 6 in that the time synchronization module 101 in the server 100 in fig. 8 may not include the receiver 1012, and at least one of the plurality of server nodes in the server 100 in fig. 8, such as the node (also referred to herein as the first server node) 102a shown in fig. 8, may be integrated with a time service card 1026, and the time service card 1026 may not be connected to the time synchronization module 101 through the back plane 104.

Specifically, in the server 100 shown in fig. 8, an RS422 interface (also referred to as a second input interface) 108 may be disposed on a PCB where the time synchronization module 101 is located, and the time synchronization module 101 may be connected to the time service card 1026 on the node 102a through the bus via the RS422 interface 108. It can be appreciated that the time service card 1026 is a board card for receiving the source clock and source time signals of the satellite positioning system 40 such as GPS and beidou, and will not be described herein.

In an embodiment, server 100 may be configured as a master node in a clock network, for example as master node 10 shown in fig. 1, via the time card 1026. In time synchronization, the time service card 1026 acquires a GPS source time signal X11 of the satellite positioning system 40, and can extract a clock, a 1pps synchronization pulse, a ToD signal, and the like from the signal X11, which is shown as a signal XX1 in fig. 9, and then transmits the signal XX1 to the phase-locked loop circuit 1011 via the RS422 interface 108, as shown in fig. 9. The phase-locked loop circuit 1011 locks the clock in the signal XX1 and the 1pps synchronization pulse to generate a local clock, and then distributes a synchronization time signal of a corresponding frequency according to the frequency characteristics of the devices or the network ports having time synchronization demands on the respective server nodes (102 b,102 c). For example, the phase-locked loop circuit 1011 may distribute the corresponding synchronization time signal X12 according to the frequency of one of the ethernet ports 107 on the node 102b, for time synchronization of the ethernet port 107 (and the ethernet device of the next stage thereof), and similarly, the phase-locked loop circuit 1011 may distribute the synchronization time signal X13 and the synchronization time signal X14 to the two ethernet ports 107 on the node 102c, respectively.

At this time, the nodes (102 b,102 c) have time synchronized with the current time synchronization module 101 with high precision, and then can generate PTP messages based on the respective obtained synchronized time signals (X12, X13, X14), the PTP messages carrying hardware timestamp information of the generated messages, the PTP messages being transmitted from the ethernet to downstream slave nodes in the external clock network based on the IEEE1588 protocol. The slave node receives the PTP message Wen Shiji and records the hardware time stamp information, analyzes the corresponding synchronous time signal from the PTP message, and performs delay check sum adjustment by utilizing the time stamp recorded by the slave node and the time stamp in the message when receiving the message, thereby obtaining the high-precision slave node local clock time.

In this embodiment, the time synchronization module 101 may utilize a commercial time service card 1026 to construct a master node, which is favorable for implementing the multi-clock source selectable capability when the multi-node server 100 performs clock network networking.

Next, still another possible implementation manner of the server provided by the embodiment of the present application is described based on the foregoing description.

Fig. 10 is a schematic structural diagram of a multi-node server according to an embodiment of the present application. Referring to fig. 10, the server 100 shown in fig. 10 is different from the server 100 shown in fig. 6 in that the time synchronization module 101 of the server 100 in fig. 10 may not include the receiver 1012.

In this example, the server 100 shown in fig. 10 may act as a slave node server in a clock network, such as slave node 20 shown in fig. 1.

Specifically, referring to fig. 11, at least one server node (herein also referred to as a second server node) of the server 100, such as the node 102a, may receive, by using the PCIe network card 1024 thereon, a PTP packet X21 (carrying a hardware timestamp when the master node generates the packet X21 and a synchronization time signal of the high-precision IEEE1588 protocol) sent by a primary master node (such as the master node 10 described above). Next, the PCIe network card 1024 may extract (through the hardware timestamp checksum adjustment) the relevant synchronization time signals, such as clock, 1pps and ToD signals, from the packet X21, and send the relevant synchronization time signals as source signals to the input interface (also referred to herein as a third input interface, which may be a universal connector plugged into the connector 1041) of the PTP time synchronization module 101 through the connector 1041 on the back plane 104, where the phase-locked loop circuit 1011 of the PTP time synchronization module 101 locks the source signals to generate a high precision local clock, and may also generate a local time.

The PTP time synchronization module 101 then generates a local synchronization clock, 1pps pulses, and a synchronized ToD signal for each node based on the local clock, according to the frequency characteristics of the devices or ports on each server node (102 b,102 c) that have time synchronization requirements. For example, phase-locked loop circuit 1011 may distribute corresponding synchronization clock and time signals X22 according to the frequency of one of network cards 1025 on node 102b for time synchronization of that network card 1025 (and its next-stage ethernet device), and similarly phase-locked loop circuit 1011 may distribute synchronization clock and time signals X23 and X24 to two ethernet ports 107 on node 102c, respectively.

Thus, each node (102 b,102 c) has a time that is synchronized with the time synchronization module 101 with high accuracy. Furthermore, each node (102 b,102 c) may also update downstream (e.g. the edge device 30 described above), if any, based on the respective obtained synchronization time signals (X22, X23, X24).

Therefore, the multi-node server 100 with the time synchronization module 101 can be used as a slave node to participate in building a clock network, so that high-precision clock and time synchronization can be realized in the link of the bottom Ethernet, and the universality of the server 100 with the time synchronization capability can be improved.

In other examples, if there are multiple source signals on the node 102a shown in fig. 11, for example, there are PTP messages sent by multiple master nodes, and a GPS clock signal acquired by a time service card, the node 102a may select one from all the received source signals to send to the PTP time module 101. The node 102a may fixedly select a source signal from a certain master node or a satellite positioning system, or may pre-configure priorities of different clock sources (such as a master node, a satellite positioning system, etc.), and select one source signal with the highest clock source priority from all current source signals, which is not described herein.

Next, a time synchronization method provided by the embodiment of the present application is described based on the above description. It will be appreciated that the method is set forth based on what has been described above, some or all of which may be found in the description above.

Referring to fig. 12, fig. 12 is a flowchart of a time synchronization method according to an embodiment of the application. As shown in fig. 12, the time synchronization method may include:

at S1010, the server obtains a source signal including at least a clock source.

In this embodiment, the server may acquire clock signals and time signals from a satellite positioning system such as GPS and beidou, or may acquire PTP messages (including clock information or time information) from other nodes in the clock network, which may be used as source signals to generate a local clock of the server. And the server only uses one source signal to generate a local clock at the same moment, and if the clock signals and the time signals of a plurality of sources exist at the same moment, the local clock can be alternatively used according to a preconfigured selection strategy. It will be appreciated that the server may be the server 100 shown in fig. 5, and that the server 100 is also described by way of example in the following description.

S1020, the time synchronization module 101 in the server generates a local clock according to the clock source in the source signal.

In this embodiment, since the time synchronization module 101 of the server 100 can correspondingly generate a local clock according to the source signal, and obtain the local time. For example, the time synchronization module 101 may synchronize the local clock according to the GPS source clock signal, or synchronize the update local clock with the time signal (including the clock) recovered in the PTP message received from the external network.

S1030, the time synchronization module 101 outputs, for each server node in the server, a corresponding time information synchronization signal based on the local clock, where the time information synchronization signal may include a synchronization clock or a synchronization time.

In this embodiment, the time synchronization module 101 may output corresponding synchronization signals (current clock, 1pps synchronization pulse, etc.), synchronization time (current clock, 1pps synchronization pulse, synchronization ToD signal), etc. for each server node based on the local clock. In addition, in order to ensure that the time synchronization of the server nodes is realized, the synchronization requirement of each server node can be referred when corresponding time information synchronization signals are output, and the synchronization signals with corresponding clock frequencies can be distributed to the server nodes so as to correspondingly perform time and clock synchronization. In this way, a server with time synchronization capability can adaptively accomplish the time synchronization needs in a clock network.

In some possible implementations, the multi-node server 100 may be a master node in a clock network, and a process of performing a time synchronization method provided by an embodiment of the present application by the master node is described below with reference to the accompanying drawings.

Fig. 13 is a schematic flow chart of a time synchronization method according to an embodiment of the present application. It will be appreciated that the method may be performed on a master node, such as the server 100 shown in fig. 6-7, or fig. 8-9. As shown in fig. 13, the time synchronization method may specifically include:

s1100, the RMC performs strategy configuration on the time synchronization module to obtain a corresponding source signal selection strategy and distribution strategy.

In this embodiment, because the types of ethernet ports (e.g., GE and 10GE, but not limited thereto) and the network port connection conditions (e.g., whether the communication connection device, the connected device need time synchronization or clock synchronization, etc.) of the respective server nodes may be different, the synchronization requirements of the respective server nodes may also be different, that is, the frequencies of the time signal, the clock signal, and the clock signal needed by the respective server nodes may be different. Therefore, the RMC may read node information (including the ethernet port type and the network port connection condition) of each server node, and generate a distribution policy of the time synchronization module, where the distribution policy is used to indicate a clock frequency, whether a clock signal is needed, and whether a time signal is needed for each server node in the server 100. It will be appreciated that the clock signal is used for frequency synchronization between devices and the time signal may be used for time synchronization between devices, i.e. the clock information is included in the time signal. The RMC may be the RMC103 shown in fig. 6-7, or fig. 8-9, and the time synchronization module may be the time synchronization module 101 shown in fig. 6-7, or fig. 8-9, which will be described below as an example.

In this embodiment, the RMC103 may also generate a source signal selection policy for the time synchronization module 101, where the policy is used to control the time synchronization module 101 to select one of the plurality of source signals for use. For example, in the source signal selection policy, a priority ranking of source signals may be included, and when multiple source signals are received simultaneously, a candidate source signal with the highest source priority is selected for use according to the priority of the sources of the source signals (such as PTP messages of the native clock, satellite positioning system, clock network, etc.) in the ranking.

Therefore, the time synchronization module supporting various clock input sources can be flexibly configured through strategy configuration, and the automatic selection of the various clock input sources can be realized.

Then, the RMC103a may issue the generated distribution policy and the source signal selection policy to the time synchronization module 101, completing policy configuration of the time synchronization module 101.

S1110, the server acquires a source signal, where the source signal includes at least a clock source.

In this embodiment, the source signal acquired by the server 100 is a high-precision source clock or time signal from a satellite positioning system such as GPS or beidou, and is input to the time synchronization module 101.

In one example, if the server 100 is internally configured as shown in fig. 6-7, the server 100 may receive a GPS source time signal (including a clock signal, a 1pp synchronization pulse signal, and a ToD signal) through an internally integrated GPS receiver 1012, and the GPS receiver 1012 may be capable of extracting the 1pps synchronization pulse signal, the clock signal, and the ToD signal from the GPS source time signal and transmitting the 1pps synchronization pulse signal, the clock signal, and the clock signal to a phase-locked loop circuit 1011 in the time synchronization module 101.

In another example, if the server 100 is internally configured as shown in fig. 8-9, the server 100 may receive the GPS source time signal (including the clock signal, the 1pp synchronization pulse signal and the ToD signal) through the timing card 1026 integrated on the internal node 102a, and the timing card 1026 may extract the 1pp synchronization pulse signal, the clock signal and the ToD signal from the GPS source time signal and transmit the signals to the time synchronization module 101 through the RS 422.

In this embodiment, at the same time, the time synchronization module 101 may acquire a local clock signal OCXO in addition to the clock or time signal (i.e., the source signal) input by the GPS receiver 1012 or the time service card 1026.

Then, as an example, to guarantee the time synchronization quality, after this S1110, it may specifically further include:

S1111, determining the health state of each current source signal by the time synchronization module according to the health index;

in this step, the time synchronization module 101 may monitor the health status of each source signal in real time to determine which source signals are healthy.

In some embodiments, determining the health status of the source signal may be based on the following criteria:

first, there is a clock source in the source signal,

and secondly, the frequency of the clock source is in the range of the set frequency value range.

If the source signal has no clock or the clock frequency does not reach the preset value range, the source signal is judged to be unhealthy and unusable. Otherwise, the source signal has a clock and the clock frequency is normal, and the source signal is available. The available source signals may participate in the source selection to generate a local clock.

Based on this, in some examples, in performing S1111, it may be specifically performed in the receiver 1012 of the time synchronization module 101:

the receiver extracts a clock source from a source signal from the satellite positioning system, and if the clock source is present and the frequency of the clock source is within a predetermined frequency range, the clock source is sent to the phase-locked loop circuit 1011. If the clock source does not exist or the frequency of the clock source is lower than the preset frequency value range, an indication signal representing that the source signal is abnormal is sent to the phase-locked loop circuit 1011.

In some examples, in executing S1111, it may be specifically executed in the phase-locked loop circuit 1011 of the time synchronization module 101:

the signal input end of the phase-locked loop circuit 1011 is monitored whether a clock source is input, and if the clock source is input in the monitoring period and the frequency of the clock source is within a preset frequency value range, the clock source is received to participate in the subsequent source selection. If no clock source is input or the input clock source is lower than the preset frequency value range or the signal input end receives the indication signal in the monitoring period, the source signal input by the signal input end is not used in the monitoring period.

Thus, the source signal which reaches the health index and is available for health is input into the phase-locked loop circuit 1011 to participate in the screening of the subsequent source signal selection strategy, so that the finally obtained reference source is ensured to be a high-quality signal and used for generating the local clock.

S1112, the time synchronization module acquires a switching signal, and according to the switching signal, the clock sources are switched from the clock sources of the source signals according to the preset clock source priority order, so as to generate a local clock according to the switched clock sources.

In this step, there may be multiple clock sources that ultimately enter the pll 1011, possibly with source signals from the satellite positioning system input by the receiver 1012, from the satellite positioning system transmitted by the time service card on the server node, from the original local clock. When the time synchronization module 101 receives a plurality of source signals that are healthy and available at the same time, the phase-locked loop circuit 1011 may trigger the reference source switching based on the switching signal (which may be from the RMC103a or generated by a signal triggering mechanism inside the phase-locked loop circuit 1011), that is, according to the priority ranking in the configured source signal selection policy, select, as the reference source, the clock source with the highest priority from the clock sources of the source signals.

For example, the high-precision GPS clock source with the highest priority in the source signal selection policy is selected as the reference source of the local clock by default, and if the GPS clock source with the highest priority is not available, the local clock source is switched to the original local clock with the priority next to that of the GPS (i.e. the local clock state is maintained) according to the trigger of the switching signal. It will be appreciated that if there are a plurality of available clock sources for the current highest priority level, the first clock source to be locked is taken as the reference source.

In some embodiments, in addition to locking a high quality high precision clock source through the process of S1111 through S1112 described above, locking may be accomplished by:

tracking and monitoring the current locked external clock source, namely, the clock source outside the original local clock;

when the loss of the external clock source is monitored, the current clock state of the local clock is forcedly maintained, or the switching to the designated clock source is forcedly performed.

In this embodiment, if the pll 1011 locks an external clock source, the external clock source may be tracked and monitored in real time by the time synchronization module 101 or the RMC103a, and when the clock source is lost (cannot be monitored), the pll 1011 is forced to keep the current clock state (such as clock frequency) and continue to operate, or the pll 1011 is forced to switch to another designated clock source, for example, a clock source with a higher current priority level, so as to ensure that the time synchronization module 101 can still achieve the time synchronization capability of the server when the locked signal is abnormal.

After locking the high quality available reference source in the various ways described above, the method further comprises:

s1120, the time synchronization module 101 generates a local clock according to the switched clock source.

In this step, the phase-locked loop circuit 1011 of the time synchronization module 101 synchronizes the local clock according to the locked high precision reference source, generates a new local clock with higher precision, and synchronizes the local clock according to the clock and frequency of the GPS source clock signal, for example. Because the source signal is a high-precision clock time signal, the local clock obtained after synchronization is also a high-precision clock, and the precision reaches a subtle level.

S1130, the synchronous demand information of each server node is called, wherein the synchronous demand information is used for representing the synchronous clock or time required by the corresponding server node and the clock frequency required by the corresponding server node.

In this embodiment, because the ethernet interfaces of different server nodes are different, such as GE and 10GE ethernet interfaces, and the synchronization requirements of the respective server nodes in the clock network are different, some of the server nodes may need to synchronize clocks, and the node information may be recorded in the system management unit 103 of the server 100, the time synchronization module 101 may call (obtain from the system management unit 103, or store the location of the information in advance from the time synchronization module 101) the information, so as to facilitate configuring the corresponding synchronization clocks or times for the server nodes according to the requirements of the nodes. The synchronization requirement information is included in the distribution policy generated in S1100.

S1140, the time synchronization module generates a corresponding synchronization signal for each server node in the server based on the local clock.

In this step, the pll circuit 1101 of the time synchronization module 101 may generate, according to a preset distribution policy, a clock signal or a time signal of a required clock frequency through a frequency synthesizer corresponding to each server node, and if a certain server node needs synchronization time, output a synchronization clock of the required frequency, a 1pps synchronization pulse signal, and a synchronization ToD signal to the certain server node as synchronization signals to be distributed to the corresponding server node.

S1150, the server node generates a PTP message according to the synchronous signal and transmits the PTP message to downstream equipment through the Ethernet.

In this step, each server node generates a PTP message of IEEE1588 protocol standard based on the received synchronization signal, where the message carries a hardware timestamp when the message is generated. The message is transmitted to the downstream equipment, such as a slave node, through the Ethernet, so that the downstream equipment can analyze high-precision clock or time information from the PTP message, and accordingly the local clock and time are correspondingly updated, and high-precision synchronization is realized.

In some possible implementations, the multi-node server 100 may be a slave node in a clock network, and a process of performing a time synchronization method provided by an embodiment of the present application by the slave node is described below with reference to the accompanying drawings.

Fig. 14 is a schematic flow chart of a time synchronization method according to an embodiment of the present application. It will be appreciated that the method may be performed on a master node, such as the server 100 shown in fig. 10-11. As shown in fig. 14, the time synchronization method may specifically include:

s1200, performing strategy configuration on the time synchronization module by the RMC to obtain a corresponding source signal selection strategy and distribution strategy.

In this step, the implementation manner may refer to the description of S1100, which is not repeated herein.

S1210, the time synchronization module obtains a source signal, the source signal including at least a clock source.

In this embodiment, the source signal acquired by the server 100 may be a PTP packet including a high precision source clock or time signal transmitted from the ethernet network by the master node.

For example, if the server 100 has the structure shown in fig. 10-11, the server 100 may receive the PTP packet through an internal node, such as the node 102a, and the node 102a may extract the 1pps synchronization pulse signal, the clock signal, the Tod signal, and the like from the PTP packet and transmit the 1pps synchronization pulse signal, the clock signal, the Tod signal, and the like to the time synchronization module 101.

In some examples, at the same time, there may be multiple PTP messages on the node 102a, i.e. multiple clock input sources, and then the node 102a selects one clock input source to input into the pll 1011 according to a preset policy, for example, a message of a certain master node is fixedly selected.

In this embodiment, at the same time, the time synchronization module 101 may acquire a local clock signal OCXO in addition to the source signal of the PTP packet, and at this time, the time synchronization module 101 may perform:

s1211, the time synchronization module 101 determines the health status of each source signal according to the health index.

This step may refer to the description of determining the health status of each current source signal by the pll circuit 1011 in step S1111 in the above embodiment, and will not be described in detail.

S1212, the time synchronization module acquires a switching signal, and according to the switching signal, the clock sources are switched from the clock sources of the source signals according to the preset clock source priority order, so as to generate a local clock according to the switched clock sources.

In this embodiment, the process of switching and locking a high-quality high-precision clock source through S1212 may refer to the description of S1112, and will not be repeated.

S1220, the time synchronization module 101 generates a local clock according to the switched clock source;

s1230, calling the synchronous demand information of each server node, wherein the synchronous demand information is used for representing the synchronous clock or time required by the corresponding server node and the clock frequency required by the corresponding server node;

S1240, the time synchronization module 101 generates corresponding synchronization signals for each server node in the server based on the local clock;

s1250, the server node generates a PTP message according to the synchronous signal and transmits the PTP message to the edge equipment through the Ethernet.

In this step, each server node generates a PTP message of IEEE1588 protocol standard based on the received synchronization signal, where the message carries a hardware timestamp when the message is generated. The message is sent to the downstream equipment, such as the edge equipment, through the Ethernet, so that the downstream equipment can analyze high-precision clock or time information from the PTP message, and accordingly the local clock and time are correspondingly updated, and high-precision synchronization is realized.

Based on the method in the above embodiment, the embodiment of the present application provides a time synchronization device. Referring to fig. 15, fig. 15 is a schematic structural diagram of a pseudo tag frame generating apparatus according to an embodiment of the present application.

As shown in fig. 15, the pseudo tag frame generating apparatus 1300 may include: an acquisition module 1301 and a processing module 1302. The acquiring module 1301 may be configured to acquire a source signal, where the source signal includes at least a clock source. The processing module 1302 may be configured to generate a local clock based on the source signal. In addition, the processing module 1302 may be further configured to output corresponding synchronization signals for each server node in the server based on the local clock, where the synchronization signals may include a clock signal and/or a time signal, and a clock frequency.

In some embodiments, the obtaining module 1301 may be further configured to obtain a source signal selection policy and a distribution policy, where the distribution policy is used to indicate a clock frequency required by each server node in the server 100, whether a clock signal is required, and whether a time signal is required, and the source signal selection policy is used to control selecting one from a plurality of source signals for use. The processing module 1302 may also be configured to determine a source signal from the plurality of source signals based on a configured source signal selection strategy.

It should be understood that, the foregoing apparatus is used to perform the method in the foregoing embodiment, and corresponding program modules in the apparatus implement principles and technical effects similar to those described in the foregoing method, and reference may be made to corresponding processes in the foregoing method for the working process of the apparatus, which are not repeated herein.

Based on the method in the above embodiment, the embodiment of the application provides an electronic device. The electronic device may include: at least one memory for storing a program; at least one processor for executing programs stored in the memory; wherein the processor is adapted to perform the methods of the above embodiments when the program stored in the memory is executed.

Based on the method in the above embodiment, the embodiment of the present application provides a computer-readable storage medium storing a computer program, which when executed on a processor, causes the processor to perform the method in the above embodiment.

Based on the method in the above embodiments, an embodiment of the present application provides a computer program product, characterized in that the computer program product, when run on a processor, causes the processor to perform the method in the above embodiments.

Based on the method in the above embodiment, the embodiment of the present application further provides a chip. Referring to fig. 16, fig. 16 is a schematic structural diagram of a chip according to an embodiment of the application. As shown in fig. 16, chip 1400 includes one or more processors 1401 and interface circuitry 1402. Optionally, chip 1400 may also contain bus 1403. Wherein:

the processor 1401 may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuitry of hardware in the processor 1401 or instructions in the form of software. The processor 1401 as described above may be a general purpose processor, a digital communicator (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. The methods and steps disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The interface circuit 1402 may be used for transmitting or receiving data, instructions or information, and the processor 1401 may process using the data, instructions or other information received by the interface circuit 1402 and may transmit processing completion information through the interface circuit 1402.

Optionally, the chip 1400 also includes memory, which may include read only memory and random access memory, and provides operating instructions and data to the processor. A portion of the memory may also include non-volatile random access memory (NVRAM).

Optionally, the memory stores executable software modules or data structures and the processor may perform corresponding operations by invoking operational instructions stored in the memory (which may be stored in an operating system).

Alternatively, the interface circuit 1402 may be used to output the execution result of the processor 1401.

It should be noted that, the functions corresponding to the processor 1401 and the interface circuit 1402 may be implemented by a hardware design, a software design, or a combination of hardware and software, which is not limited herein.

It will be appreciated that the steps of the method embodiments described above may be performed by logic circuitry in the form of hardware in a processor or instructions in the form of software.

It should be understood that, the sequence number of each step in the foregoing embodiment does not mean the execution sequence, and the execution sequence of each process should be determined by the function and the internal logic, and should not limit the implementation process of the embodiment of the present application. In addition, in some possible implementations, each step in the foregoing embodiments may be selectively performed according to practical situations, and may be partially performed or may be performed entirely, which is not limited herein.

It is to be appreciated that the processor in embodiments of the application may be a central processing unit (central processing unit, CPU), other general purpose processor, digital signal processor (digital signal processor, DSP), application specific integrated circuit (application specific integrated circuit, ASIC), field programmable gate array (field programmable gate array, FPGA) or other programmable logic device, transistor logic device, hardware components, or any combination thereof. The general purpose processor may be a microprocessor, but in the alternative, it may be any conventional processor.

The method steps in the embodiments of the present application may be implemented by hardware, or may be implemented by executing software instructions by a processor. The software instructions may be comprised of corresponding software modules that may be stored in random access memory (random access memory, RAM), flash memory, read-only memory (ROM), programmable ROM (PROM), erasable programmable PROM (EPROM), electrically erasable programmable EPROM (EEPROM), registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted across a computer-readable storage medium. The computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital Subscriber Line (DSL)), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a Solid State Disk (SSD)), or the like.

It will be appreciated that the various numerical numbers referred to in the embodiments of the present application are merely for ease of description and are not intended to limit the scope of the embodiments of the present application.

Claims

1. The time synchronization module is characterized by comprising a phase-locked loop circuit, a receiver, a first input interface and a plurality of output interfaces, wherein the first input interface is connected with the input end of the receiver, the output end of the receiver is connected with the signal input end of the phase-locked loop circuit, the signal output end of the phase-locked loop circuit is connected with each output interface, and the output interfaces are used for being connected with a server node;

the receiver is used for receiving a source signal from a satellite positioning system from the first input interface and extracting a clock source from the source signal;

the phase-locked loop circuit is used for generating time information synchronous signals corresponding to the server nodes according to the clock source and outputting the time information synchronous signals to the corresponding output interfaces.

2. The time synchronization module of claim 1, further comprising a second input interface for connecting the phase-locked loop circuit signal input to at least one server node,

The second input interface is used for receiving a clock source sent by the connected server node and transmitting the clock source to the phase-locked loop circuit.

3. The time synchronization module according to claim 1 or 2, further comprising a frequency processing circuit, wherein a signal output of at least one of the phase-locked loop circuits is electrically connected to each of the server nodes via the frequency processing circuit;

and the phase-locked loop circuit synthesizes the time information synchronous signals with the frequencies required by the corresponding server nodes through the corresponding frequency processing circuits.

4. A multi-node server, characterized in that the multi-node server comprises a time synchronization module and a plurality of server nodes,

the time synchronization module is provided with at least one input interface and a plurality of output interfaces, and is correspondingly connected with each server node through the plurality of output interfaces,

the time synchronization module is used for generating time information synchronization signals corresponding to the server nodes according to clock sources input from the input interfaces, and transmitting the time information synchronization signals to the server nodes through the corresponding output interfaces.

5. The multi-node server of claim 4, wherein the plurality of server nodes includes a first server node and the input interface of the time synchronization module includes a second input interface;

the first server node is provided with a clock source generation module, and the clock source generation module is connected with the second input interface;

the first server node is configured to receive, through the clock source generating module, a source signal from a satellite positioning system, extract a corresponding clock source from the source signal, and input the clock source to the time synchronization module.

6. The multi-node server of claim 4, wherein the plurality of server nodes includes a second server node connection, and wherein the input interface of the time synchronization module includes a third input interface;

the second server node is provided with a message processing module, and the message processing module is connected with the third input interface;

the second server node is configured to receive a timing protocol PTP packet from an external clock network through the packet processing module, extract the clock source from the PTP packet, and input the clock source to the time synchronization module.

7. The multi-node server of any of claims 4-6, further comprising a backplane having a first connector and a second connector, one of the first connectors being coupled to at least one of the second connectors;

each input interface of the time synchronization module is connected with the first connector, and the second connector is connected with a corresponding server node.

8. The multi-node server of any one of claims 4-7, further comprising a system management unit electrically connecting the time synchronization module and each server node,

the system management unit is used for acquiring the synchronous demand information of each server node, and the synchronous demand information is used for representing the time synchronous demand and/or clock synchronous demand of the corresponding server node;

the system management unit is further configured to configure the synchronization requirement information in the time synchronization module, so that the time synchronization module outputs the time information synchronization signal corresponding to the respective synchronization requirement information for each server node.

9. The multinode server of claim 8, wherein the time synchronization module comprises a phase-locked loop circuit having a plurality of signal inputs coupled to the corresponding input interfaces,

And the phase-locked loop circuit receives the switching signals sent by the system management unit, sorts the switching signals according to the preset clock source priority, and switches the clock sources from the clock sources input by the input interfaces.

10. The multi-node server according to any of claims 4-9, wherein the time synchronization module is further configured to switch to a corresponding next clock source according to a preset clock source priority ranking when the monitored state of the current clock source does not reach the health indicator.