CN112398568B - System and method for synchronizing clocks in multiple cells - Google Patents
System and method for synchronizing clocks in multiple cells Download PDFInfo
- Publication number
- CN112398568B CN112398568B CN202011330584.0A CN202011330584A CN112398568B CN 112398568 B CN112398568 B CN 112398568B CN 202011330584 A CN202011330584 A CN 202011330584A CN 112398568 B CN112398568 B CN 112398568B
- Authority
- CN
- China
- Prior art keywords
- synchronization
- service
- slave
- board
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 38
- 230000001360 synchronised effect Effects 0.000 claims abstract description 82
- 230000015654 memory Effects 0.000 claims description 17
- 238000001514 detection method Methods 0.000 claims description 10
- 230000001960 triggered effect Effects 0.000 claims description 8
- 125000004122 cyclic group Chemical group 0.000 claims description 3
- 238000012545 processing Methods 0.000 description 19
- 238000010586 diagram Methods 0.000 description 14
- 230000008569 process Effects 0.000 description 12
- 230000006870 function Effects 0.000 description 11
- 230000006855 networking Effects 0.000 description 9
- 238000004590 computer program Methods 0.000 description 5
- 239000013078 crystal Substances 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 229910052701 rubidium Inorganic materials 0.000 description 2
- IGLNJRXAVVLDKE-UHFFFAOYSA-N rubidium atom Chemical compound [Rb] IGLNJRXAVVLDKE-UHFFFAOYSA-N 0.000 description 2
- 230000003044 adaptive effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 238000005111 flow chemistry technique Methods 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/25—Arrangements specific to fibre transmission
- H04B10/2575—Radio-over-fibre, e.g. radio frequency signal modulated onto an optical carrier
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W56/00—Synchronisation arrangements
- H04W56/001—Synchronization between nodes
- H04W56/0015—Synchronization between nodes one node acting as a reference for the others
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
- H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Mobile Radio Communication Systems (AREA)
Abstract
The invention discloses a multi-cell synchronous clock system, which comprises: the multiple radio frequency remote service boards are used for acquiring multiple synchronous clock sources, wherein the synchronous clock sources comprise: synchronization based on a GPS/Beidou satellite system, IEEE1588v2 synchronization based on Ethernet, SyncE synchronization based on Ethernet and 1588v2 synchronization based on uplink radio remote; and the service flow module is used for connecting a plurality of radio remote service boards in a master-slave synchronization or circulation synchronization mode according to different service scenes to complete multi-synchronization source synchronization among the cells. The method can provide various synchronous sources, and further complete the function of synchronizing the synchronous sources in different modes in a plurality of cells.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a system and a method for synchronizing clocks in multiple cells.
Background
For a communication system composed of multiple cells, frame header synchronization or fixed offset relationship is required between multiple remote radio units, so that a fixed relationship is ensured for timing of distributed remote radio units, and the effect of synchronizing multiple distributed remote radio units must be achieved.
In the conventional method for synchronization, the remote radio unit extracts a recovered clock from a high-speed digital transmission interface of the baseband processing unit as a reference clock of a phase-locked source of the remote radio unit, and then generates various clocks to be transmitted to the digital processing unit and the radio frequency processing unit. For example, as disclosed in chinese patent publication No. CN105515710A, a method and an apparatus for implementing time synchronization are disclosed, which implement time synchronization by networking in a clock server, a baseband processing unit, and a radio remote unit. However, the clock server employed in such a networking manner needs to be specially manufactured and additionally added with components. In addition, the disclosed service flow module is completed in the main unit MU, however, once the MU device fails to work, the other connected RRUs cannot work normally, and it can be seen that the synchronization information is sent on the bus after depending on the MU device service flow processing.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a system and a method for synchronizing clocks in multiple cells, which can overcome the problems in the prior art by using different networking modes, and provide multiple synchronization sources, thereby completing the function of synchronizing multiple synchronization sources in multiple cells in different modes, and greatly improving the working efficiency of the cells.
In order to solve the above technical problem, a first aspect of the present invention discloses a multi-cell synchronous clock system, which includes: a plurality of remote radio service boards, configured to obtain multiple synchronous clock sources, where the synchronous clock source includes: synchronization based on a GPS/Beidou satellite system, IEEE1588v2 synchronization based on Ethernet, SyncE synchronization based on Ethernet and 1588v2 synchronization based on uplink radio remote; and the service flow module is used for connecting the radio remote service boards in a master-slave synchronization or circulation synchronization mode according to different service scenes to complete multi-synchronization source synchronization among the cells.
In some embodiments, a radio remote service panel includes: the second pulse selection module is used for selecting a second pulse signal according to the pulse state of the uplink interface; the first switch is used for selecting the pulse per second signal of the current-stage synchronous clock source; the second pulse generation module is used for generating a second pulse signal through a reference clock pulse; and a second switch for outputting the selected pulse-per-second signal.
In some embodiments, a business process module, comprising: the first service unit is used for configuring the connection of each service board into time service as long as one service board is synchronously connected when a plurality of radio remote service boards are circularly synchronized according to a service scene; wherein the cycle synchronization is triggered by the parallel connection between the service boards.
In some embodiments, a business process module, comprising: a second service unit, configured to, when multiple radio remote service boards are synchronized between a master service board and a slave service board according to a service scenario, synchronize a synchronization signal sent from the master service board to the slave service board after the master service board is synchronized, and sequentially synchronize the slave service boards to a next slave service board after the slave service boards receive the synchronization signal; wherein master-slave synchronization is triggered by the series connection between the service boards.
In some embodiments, the system further comprises: and the pulse detection module is used for detecting whether the currently input pulse is stable.
According to a second aspect of the present invention, there is provided a method of synchronizing clocks in multiple cells, the method comprising: the system of the multi-cell synchronous clock is used for carrying out master-slave synchronization or cycle synchronization on a plurality of synchronous sources among the cells.
In some embodiments, the system utilizing the multi-cell synchronization clock cyclically synchronizes a plurality of synchronization sources between cells, comprising: configuring a GPS/Beidou satellite system, IEEE1588v2 based on Ethernet, SyncE based on Ethernet and a 1588v2 service board based on uplink radio remote into a synchronous state; configuring a mode of cycle synchronization when adjacent service boards are connected in parallel according to the connection mode of each service board; and executing the synchronization of each synchronization source in a plurality of cells according to the circular synchronization mode.
In some embodiments, the system utilizing the multi-cell synchronization clock performs master-slave synchronization on a plurality of synchronization sources between cells, including: configuring a GPS/Beidou satellite system, IEEE1588v2 based on Ethernet, SyncE based on Ethernet and a 1588v2 service board based on uplink radio remote into a synchronous state; configuring a master-slave synchronization mode when adjacent service boards are connected in series according to the connection mode of each service board; after the main service board is synchronized, the main service board sends out a synchronizing signal to the slave service boards, and the slave service boards receive the synchronizing signal and then sequentially synchronize the synchronizing signal to the next slave service board. And executing the synchronization of each synchronization source in a plurality of cells according to the master-slave cycle synchronization mode.
According to a third aspect of the present invention, there is provided a multi-cell synchronized clock apparatus, the apparatus comprising: a memory storing executable program code; a processor coupled with the memory; the processor calls the executable program code stored in the memory to execute the multi-cell synchronous clock method as described above.
According to a fourth aspect of the present invention, there is provided a computer storage medium storing computer instructions which, when invoked, perform a multi-cell synchronous clocking method as described above.
Compared with the prior art, the invention has the beneficial effects that:
the invention can obtain the synchronous clock source mode except the baseband processing unit to the remote radio unit to complete the clock synchronization, and the synchronous clock source comprises: synchronization based on a GPS/Beidou satellite system, IEEE1588v2 synchronization based on Ethernet, SyncE synchronization based on Ethernet and 1588v2 synchronization based on an upper RU, so that timing distribution and synchronization functions among a plurality of radio remote cells are completed, and the realization of diversified synchronization functions among the cells is facilitated.
Drawings
Fig. 1 is a schematic diagram of a single cell synchronization principle according to an embodiment of the present invention;
FIG. 2 is a system diagram of a multi-cell synchronous clock according to an embodiment of the present invention;
FIG. 3 is a system diagram of another multi-cell synchronous clock disclosed in the embodiment of the present invention;
FIG. 4 is a system diagram of another multi-cell synchronous clock disclosed in the embodiment of the present invention;
FIG. 5 is a system diagram of another multi-cell synchronous clock according to an embodiment of the present invention;
FIG. 6 is a system diagram of another multi-cell synchronous clock disclosed in the present invention;
FIG. 7 is a schematic diagram of a pulse detection process of a multi-cell synchronous clock according to an embodiment of the present invention;
FIG. 8 is a flowchart illustrating a method for synchronizing clocks of multiple cells according to an embodiment of the present invention;
FIG. 9 is a flowchart illustrating a method for synchronizing clocks of multiple cells according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of an interactive device of a multi-cell synchronous clock according to an embodiment of the present invention.
Detailed Description
For better understanding and implementation, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "comprises," "comprising," and any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or modules is not necessarily limited to those steps or modules explicitly listed, but may include other steps or modules not expressly listed or inherent to such process, method, article, or apparatus.
As shown in fig. 1, which is a block diagram of a synchronization system of an existing single-cell remote radio module, as shown in fig. 1, the system includes an ethernet/optical port PHY adaptation unit, a digital processing unit, a radio frequency processing unit, and a synchronization unit. The Ethernet PHY provides a recovery clock and 1588& PPS to the synchronization unit, the synchronization unit provides a Frame/Slot Timing to the digital processing unit according to the fixed relation between the reference clock 10MHz and the recovery clock, and simultaneously provides an ADC/DAC reference clock to the radio frequency processing unit.
The embodiment of the invention discloses a method and a system for synchronizing clocks of multiple cells, which can complete clock synchronization by acquiring synchronous clock source modes except a baseband processing unit from a radio remote unit, wherein the synchronous clock sources comprise: synchronization based on a GPS/Beidou satellite system, IEEE1588v2 synchronization based on Ethernet, SyncE synchronization based on Ethernet and 1588v2 synchronization based on an upper RU, so that timing distribution and synchronization functions among a plurality of radio remote cells are completed, and the realization of diversified synchronization functions among the cells is facilitated.
Example one
Referring to fig. 2, fig. 1 is a system block diagram of a multi-cell synchronous clock according to an embodiment of the present invention. As shown in fig. 2, the system of multi-cell synchronized clocks may include:
the multiple radio frequency remote service boards 1 are configured to obtain multiple synchronous clock sources, where the synchronous clock sources include: the system comprises synchronization based on a GPS/Beidou satellite system, IEEE1588v2 synchronization based on Ethernet, SyncE synchronization based on Ethernet and 1588v2 synchronization based on uplink radio remote. Therefore, the clock source of the 1 radio remote service board may be that the radio remote service board is directly connected to the GPS or the beidou satellite module to obtain a clock source. Or may be obtained in a 1588 clock server (fiber time service) between the BBU and the RRU, and further, may also be a SyncE clock for extracting an ethernet from another 1 1588PoE switch (ethernet time service). It should be noted that, in the second networking mode, the 1588 clock server can time the BBU and the RRU simultaneously in the network.
Further, in the prior art, clock synchronization sources are sometimes used from a synchronous clock server. The clock server belongs to a single device, generally 3 paths of gigabit Ethernet interfaces are provided on the single device, wherein the network port 1 and the network port 2 support synchronous Ethernet and PTP, each path of interface can be independently set to be an NTP or a PTP server, and a powerful industrial processor can meet a large-capacity data request. The device supports a single satellite (Beidou and GPS) mode and a mixed mode, calibrates a local clock by receiving satellite signals, outputs an accurate time frequency signal as a high-accuracy NTP/PTP master clock, and can provide accurate time information for the whole network. And meanwhile, various reference inputs are supported, seamless switching of the various reference inputs can be realized, and the time service stability and the system safety are ensured. The clock server can support various reference inputs (1PPS, 1PPS + TOD, GNSS, IRIG-B and 10MHz), has a high-precision digital phase locking function, supports various local oscillators (a highly stable rubidium clock, a small rubidium clock, a constant-temperature crystal oscillator and the like), and has a 1PPS and arbitrary frequency pulse output function (pulse width is adjustable). However, such clock servers need to be specially manufactured and added to adapt to the connection mode requiring networking, but the invention overcomes the networking mode and does not require the special equipment to meet the requirement.
And the service flow module 2 is used for connecting the plurality of radio remote service boards in a master-slave synchronization or circulation synchronization mode according to different service scenes to complete multi-synchronization source synchronization among the cells.
As a specific implementation manner of this embodiment, as shown in fig. 3, the remote rf service board includes: and the pulse per second selection module is used for selecting a pulse per second signal according to the pulse state of the uplink interface, is controlled by a CPLD (complex programmable logic device), and defaults to select uplink RUin _1588& PPS when the power is on or reset. In practical application, whether 1PPS (pulse per second) of the uplink RUin _1588& PPS exists or not needs to be judged, and when the pulse per second of the uplink RUin _1588& PPS exists, the uplink RUin _1588& PP is selected as output. And conversely, when the pulse per second signal of the uplink RUin _1588& PPS does not exist, the GPS/Beidou system is selected as the output. And judging whether the second pulse signal exists or not, detecting through N continuous 1pps pulses, and judging that the 1pps signal exists when the 1pps pulses appear for N times continuously.
The first switch (as shown in the figure, a K1 switch) is used for selecting a pulse per second signal of the current-stage synchronous clock source, and is used for selecting a 1PPS signal of BBU _1588& PPS and GPS/beidou for the current-stage synchronous clock source, and is configured and controlled by OAM (operation, maintenance and management).
And the second pulse generation module is used for generating a second pulse signal by the reference clock pulse. Wherein, in order to ensure that the pulse has no frequency offset, the reference clock is a 40ms or 80ms signal output by the digital processing unit, and then a generated 1pps signal. The reference clock must be used as a pulse generating signal.
A second switch (shown as a K2 switch) for outputting a selected pulse-per-second signal, embodied as output 1588v2& PPS _ OUT for selecting the signal source, selected by the OAM configuration.
OAM reset, which when receiving an OAM reset command, the CPLD all switches resume default values.
As a specific embodiment, the port definition for the synchronization unit may include:
1. the GPS/Beidou is 1pps transmitted by an external GPS/Beidou module;
2. the uplink RUin _1588& PPS is 1PPS obtained from the uplink RU;
3. the downlink RUout _1588& PPS is a 1PPS signal after the selection of the GPS/Beidou or the uplink RUin _1588& PPS;
4. 1588v2& PPS _ IN is 1PPS obtained from Ethernet PHY/optical port adaptation;
5. BBU _1588& PPS is used for timing 1PPS generated by the baseband processing unit;
6. 1588v2& PPS _ OUT is 1PPS obtained from 1588v2& PPS _ IN or 1PPS signal of BBU _1588& PPS output from the baseband processing unit;
7. OAM rest resets CPLD signal when OAM resynchronizes.
For the business process module, the specific implementation is completed by matching upper layer software in RU with FPGA, which comprises the following steps: the first service unit is used for configuring the connection of each service board into time service as long as one service board is synchronously connected when a plurality of radio remote service boards are circularly synchronized according to a service scene; wherein the cycle synchronization is triggered by the parallel connection between the service boards. As shown IN fig. 4, for a system schematic diagram when a plurality of service versions are connected based on a cyclic synchronization manner, each service board can receive and guarantee that timing can be directly transmitted (four pins: 1588v2& PPS _ IN, 1588v2& PPS _ OUT, RUin _1588& PPS of an upper link, RUout _1588& PPS of a lower link), and guarantee that timing can be transmitted as long as one service board can synchronize (GPS/Beidou identifier), and through the cyclic synchronization connection IN this manner, the service boards do not pay attention to a master-slave relationship, thereby simplifying a system structure.
The service flow module 2 further includes a second service unit, configured to synchronize the master service board when the plurality of radio remote service boards are based on master-slave synchronization according to a service scenario, and then send a synchronization signal to the slave service board from the master service board, and after receiving the synchronization signal from the slave service board, sequentially synchronize the slave service board to a next slave service board; wherein master-slave synchronization is triggered by the series connection between the service boards. Fig. 5 is a schematic diagram of a system when a plurality of service versions are connected based on a master-slave synchronization method. Firstly, the service board 1 is synchronized (GPS/Beidou identification), then, the service board 1 sends a synchronization signal to the service board 2 (two pins 1588v2& PPS _ OUT, and a downlink RUout _1588& PPS), after the service board 2 receives second pulse (1PPS) synchronization, the synchronization signal is sent to the service board 3 again, and the synchronization is sequentially synchronized according to the synchronization sequence. Thus, the formation of a closed loop can be avoided by this cascade formation.
Further, as a preferred embodiment, the system further comprises: and the pulse detection module is used for detecting whether the currently input pulse is stable. As shown in fig. 6, the pulse detection module includes 3 sub-functional modules:
and the second pulse detector is used for timing 5 seconds to generate a pulse to the K4 switch.
And the K4 switch is used for selecting a GPS/Beidou system or an uplink RUin _1588& PPS signal and is controlled by the OAM.
The K3 switch is used for selecting an OAM reset signal or a 1PPS signal of the K4 switch and outputting the signal to the switch 1 and the downstream RUout _1588& PPS end; where the synchronization or OAM resets the default value and waits 1 second before gating the input '2' port.
The pulse detection module can detect the pulse stable state of various synchronous sources. Exemplarily, as shown in fig. 7, which is a schematic diagram of a GPS/beidou second pulse detection process, as shown in fig. 7, first, the continuous pulse detection module is turned off by OAM, the switch K4 is configured to the '1' port by default, an external GPS/beidou pulse signal is selected, and a synchronization process is run, and at the same time, the switch K3 selects the '1' by default, and when GPS/beidou is synchronized, after waiting 5 seconds, the switch K3 selects the '2'. And then, starting the pulse detection module, and delaying for T time. The switch K4 switches to the '2' port if no stable input pulse is detected for N consecutive seconds (e.g., set to 5s) and switches to the '1' port if there is a pulse of seconds. Thereafter, the above-described flow is repeated by the switch K4. And finally, when an OAM reset instruction is received (the OAM resets the switch state of the CPLD when resynchronization is needed), all switches of the CPLD recover the default value, and the pulse detection module starts to circulate again.
It should be noted that the service flow module can be independently completed in each RRU, and does not depend on the synchronization information of the baseband processing unit, nor emphasizes that the clock synchronization source of the RRU must be derived from the clock server. Therefore, the resynchronization after the flexible networking can be realized in the multiple service boards (namely multiple cells) of the radio remote unit, for example, after 4, 8, 16 and other service boards exist in one radio remote unit, the synchronization mode of the grouping equipment can still be used, for example, 8 service boards are set as master-slave synchronization, and 8 service boards are set as cycle synchronization; and in the clock server networking, time service can be simultaneously carried out between a plurality of BBUs and a plurality of RRUs, and the RRUs can acquire synchronous information from optical fibers or network ports and do not depend on a processing flow module of an MU in a baseband processing unit.
According to the system provided by this embodiment, the radio remote unit can acquire a synchronous clock source mode other than the baseband processing unit to complete clock synchronization, and the synchronous clock sources include: synchronization based on a GPS/Beidou satellite system, IEEE1588v2 synchronization based on Ethernet, SyncE synchronization based on Ethernet and 1588v2 synchronization based on an upper RU, so that timing distribution and synchronization functions among a plurality of radio remote cells are completed, and the realization of diversified synchronization functions among the cells is facilitated.
Example two
Referring to fig. 8 and 9, fig. 8 and 9 are flowcharts of a method for performing master-slave synchronization or cycle synchronization on multiple synchronization sources between cells by using the multi-cell synchronization clock system according to an embodiment of the present invention.
Illustratively, as shown in fig. 8, the method of synchronizing clocks in multiple cells may include:
step one, synchronizing the GPS/Beidou system, wherein a master board and a slave board contained in the GPS/Beidou system are configured to be GPS/Beidou synchronous, wherein the adopted pulse per second comes from the GPS/Beidou system, and each service board changes the recorded synchronous state into 'GPS/Beidou synchronous'.
Step two, 1588v2/PTP synchronization is carried out, 1588v2/PTP synchronization is configured on both a master board and a slave board, wherein the adopted second pulse is derived from an original PTP synchronization strategy, for example, a boundary clock has 2 or more than 2 ports, one is used as slave for synchronizing with an upper master, and the other is used as master for providing timing for a lower slave. And carrying out frequency synchronization and time synchronization by receiving and transmitting an IP message (carrying a timestamp) between the master and the slave.
And step three, synchronizing the Ethernet PHY, extracting the clock from the serial code stream of the Ethernet line, sending the clock to a device system clock phase-locked loop to track and generate a system clock after a source selection algorithm is carried out, then using the line clock of the port as an Ethernet network segment to send a reference clock through the system clock, and sending out the reference clock in the sent serial code stream. After the ethernet optical port PHY succeeds in adaptive synchronization, each board records that the synchronization state is '1588 synchronization'.
And step four, in a Free oscillation mode, namely a Free run mode, cascade synchronization is configured on the master board and the slave board, the second pulse adopted by the cascade synchronization is derived from the second pulse provided to a PLL (such as Si538x) after the factory calibration of the master board crystal oscillator, and each board records that the synchronization state is Free run.
And step five, setting the cycle synchronization into a parallel triggering mode, namely each service board can execute the synchronization process. The concrete implementation is as follows: the GPS/Beidou synchronization is carried out in a circulating way, and the execution actions of all the plates are consistent; if the timeout times of GPS/Beidou synchronization is 1, executing 1588 synchronization, and after 1588 synchronization is successful, adopting 1PPS of 1588v2& PPS _ IN; if the overtime times are larger than 1, the extended waiting time is T-90 x (N +1) s, the state is switched to a Free run state, and a resynchronization flow is triggered.
And step six, if the GPS/Beidou or 1588 synchronization of one service board fails, performing a GPS/Beidou synchronization process by using uplink RUin _1588& PPS synchronization of other service boards as a synchronization source, wherein the OAM recording synchronization state is 'GPS/Beidou _ IN synchronization'.
Illustratively, as shown in fig. 9, the method of synchronizing clocks in multiple cells based on a master-slave synchronization manner may include:
step one, synchronizing a GPS/Beidou system, configuring GPS/Beidou synchronization for a mainboard and a slave board which comprise the same, wherein the second pulse adopted by the mainboard is derived from a GPS/Beidou module, the second pulse adopted by the slave board is derived from the mainboard, and each board records that the synchronization state is 'GPS/Beidou synchronization'.
Step two, synchronizing 1558v2/PTP, synchronizing the mainboard configuration 1588, synchronizing the slave board configuration in a cascade manner, wherein the second pulse adopted by the mainboard comes from a clock server in the networking network, the second pulse adopted by the slave board comes from the mainboard, the synchronous state recorded by the mainboard is '1588 synchronous', and the synchronous state recorded by the slave board is 'cascade synchronization'.
And step three, in a Free oscillation mode, configuring a Free _ run state by the master board, configuring cascade synchronization by the slave board, wherein the pulse per second adopted by the master board is derived from the pulse per second sent to a PLL (such as Si538x) after the crystal oscillator of the master board leaves factory calibration, the pulse per second adopted by the slave board is derived from the master board, the master board records the synchronization state as 'Free run', and the slave board records the synchronization state as 'cascade synchronization'.
And step four, setting the master-slave synchronization as a serial triggering mode, wherein the master-slave service board needs to execute the synchronization sequence process. The concrete implementation is as follows: in the four service boards, after the main boards are synchronized, the other three service boards trigger the GPS/Beidou or cascade synchronization simultaneously. The GPS/Beidou synchronization circularly executes the synchronous operation, and the execution actions of all the boards are consistent; if the timeout times of GPS/Beidou synchronization is 1, executing 1588 synchronization, and after 1588 synchronization is successful, adopting 1PPS of 1588v2& PPS _ IN; if the overtime times are larger than 1, the extended waiting time is T-90 x (N +1) s, the state is switched to a Free run state, and a resynchronization flow is triggered.
And step five, after the master service board completes synchronization, the slave board executes corresponding operations as shown in fig. 9.
Step six, after the slave board is synchronized, when the master board is converted into a Free run state because the overtime frequency is more than 1, the slave board still sends pulse per second.
And seventhly, in the slave board synchronization process, the no-signal waiting time adopts a counting sequential accumulation prolonging mode, and the slave board reset caused by long master board synchronization time due to the waiting time is avoided.
In other embodiments, when not suitable for master-slave synchronization or cycle synchronization, master-slave synchronization and cycle synchronization may be used in combination according to different application scenarios.
Illustratively, when the source end of the GPS/Beidou signal is switched frequently or the GPS/Beidou signal is weak, the service board can normally synchronize the GPS/Beidou by adopting circulation and master-slave synchronization.
Illustratively, when the GPS/beidou system has no signal, if two of the service boards 1588 are synchronized, the service board of the next stage synchronizes with the service board of the upper stage. If 1588 of the service board 1 and the service board 3 are synchronized, as the switch of the K2 is switched to 1, the service boards 2 and 4 synchronize the service board 1 and the service board 3 respectively; in the second master-slave synchronization mode, the slave board sends the pulse per second to the master service board after the master service board is synchronized, and other slave boards can acquire the pulse per second of the master board within no fixed waiting time and the cascade synchronization is successful.
In the cycle synchronization mode, when all the service boards are not synchronized, as the K2 switch is switched to a '2' port, a closed loop is formed, no signal is output, and 1pps and respective Free run are not generated; the off-sync processing flow of the service board is also as shown in fig. 9, and a count sequential accumulation extension mode is adopted to trigger resynchronization, and a synchronization timeout count is added.
According to the method provided by this embodiment, clock synchronization can be completed by obtaining a synchronous clock source mode other than the baseband processing unit for the remote radio unit, where the synchronous clock source includes: synchronization based on a GPS/Beidou satellite system, IEEE1588v2 synchronization based on Ethernet, SyncE synchronization based on Ethernet and 1588v2 synchronization based on an upper RU, so that timing distribution and synchronization functions among a plurality of radio remote cells are completed, and the realization of diversified synchronization functions among the cells is facilitated.
EXAMPLE III
Referring to fig. 10, fig. 10 is a schematic structural diagram of a multi-cell synchronous clock device according to an embodiment of the present invention. The multi-cell synchronous clock apparatus depicted in fig. 10 may include:
a memory 601 in which executable program code is stored;
a processor 602 coupled to a memory 601;
the processor 602 calls executable program code stored in the memory 601 for executing the multi-cell synchronous clock described in the first embodiment.
Example four
The embodiment of the invention discloses a computer readable storage medium for storing a computer program for electronic data exchange, wherein the computer program enables a computer to execute the multi-cell synchronous clock described in the first embodiment.
EXAMPLE five
An embodiment of the present invention discloses a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to execute the multi-cell synchronous clock method described in the first embodiment or the second embodiment.
The above-described embodiments are only illustrative, and the modules described as separate parts may or may not be physically separate, and the parts displayed as modules may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above detailed description of the embodiments, those skilled in the art will clearly understand that the embodiments may be implemented by software plus a necessary general hardware platform, and may also be implemented by hardware. Based on such understanding, the above technical solutions may be embodied in the form of a software product, which may be stored in a computer-readable storage medium, where the storage medium includes a Read-Only Memory (ROM), a Random Access Memory (RAM), a Programmable Read-Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), a One-time Programmable Read-Only Memory (OTPROM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), a Compact Disc-Read-Only Memory (CD-ROM), or other disk memories, CD-ROMs, or other magnetic disks, A tape memory, or any other medium readable by a computer that can be used to carry or store data.
Finally, it should be noted that: the multi-cell synchronous clock method and apparatus disclosed in the embodiments of the present invention are only preferred embodiments of the present invention, which are only used for illustrating the technical solutions of the present invention, and are not limited thereto; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art; the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (4)
1. A system for synchronizing clocks in multiple cells, said system for synchronizing clocks in multiple cells comprising:
a plurality of remote radio service boards, configured to obtain multiple synchronous clock sources, where the synchronous clock source includes: synchronization based on a GPS/Beidou satellite system, IEEE1588v2 synchronization based on Ethernet, SyncE synchronization based on Ethernet and 1588v2 synchronization based on uplink radio remote, wherein the radio remote service board comprises:
the second pulse selection module is used for selecting a second pulse signal according to the pulse state of the uplink interface;
the first switch is used for selecting the pulse per second signal of the current-stage synchronous clock source;
the second pulse generation module is used for generating a second pulse signal through a reference clock pulse;
a second switch for outputting the selected second pulse signal;
the system further comprises: a service flow module, configured to connect the multiple radio remote service boards according to different service scenarios in a master-slave synchronization or a cyclic synchronization manner, and complete multi-synchronization source synchronization between the cells, where the service flow module includes:
the first service unit is used for configuring the connection of each service board into time service as long as one service board is synchronously connected when a plurality of radio remote service boards are circularly synchronized according to a service scene; wherein, the cycle synchronization is triggered by the parallel connection between the service boards;
a second service unit, configured to, when multiple radio remote service boards are synchronized between a master service board and a slave service board according to a service scenario, synchronize a synchronization signal sent from the master service board to the slave service board after the master service board is synchronized, and sequentially synchronize the slave service boards to a next slave service board after the slave service boards receive the synchronization signal; wherein, the master-slave synchronization is triggered by the serial connection between the service boards;
the system further comprises: and the pulse detection module is used for detecting whether the currently input pulse is stable.
2. A method for synchronizing clocks in multiple cells, the method comprising:
the system of multi-cell synchronization clocks as claimed in claim 1, wherein multiple synchronization sources between cells are cyclically synchronized by:
configuring a GPS/Beidou satellite system, IEEE1588v2 based on Ethernet, SyncE based on Ethernet and a 1588v2 service board based on uplink radio remote into a synchronous state;
configuring a mode of cycle synchronization when adjacent service boards are connected in parallel according to the connection mode of each service board;
according to the circulation synchronization mode, each synchronization source is synchronized in a plurality of cells;
or
The system of multi-cell synchronous clocks as claimed in claim 1 is used to perform master-slave synchronization of multiple synchronization sources between cells, and is implemented as follows:
configuring a GPS/Beidou satellite system, IEEE1588v2 based on Ethernet, SyncE based on Ethernet and a 1588v2 service board based on uplink radio remote into a synchronous state;
configuring a master-slave synchronization mode when adjacent service boards are connected in series according to the connection mode of each service board;
after synchronizing the main service board, the main service board sends a synchronizing signal to the slave service boards, and the slave service boards receive the synchronizing signal and then sequentially synchronize the synchronizing signal to the next slave service board;
and executing the synchronization of each synchronization source in a plurality of cells according to the master-slave cycle synchronization mode.
3. A multi-cell synchronous clock apparatus, the apparatus comprising:
a memory storing executable program code;
a processor coupled with the memory;
the processor calls the executable program code stored in the memory to perform the method of multi-cell synchronous clocking as claimed in claim 2.
4. A computer storage medium storing computer instructions for performing the method of multi-cell synchronous clocking of claim 2 when called.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011330584.0A CN112398568B (en) | 2020-11-24 | 2020-11-24 | System and method for synchronizing clocks in multiple cells |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011330584.0A CN112398568B (en) | 2020-11-24 | 2020-11-24 | System and method for synchronizing clocks in multiple cells |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112398568A CN112398568A (en) | 2021-02-23 |
| CN112398568B true CN112398568B (en) | 2021-08-17 |
Family
ID=74607727
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011330584.0A Active CN112398568B (en) | 2020-11-24 | 2020-11-24 | System and method for synchronizing clocks in multiple cells |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112398568B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113904748A (en) * | 2021-09-24 | 2022-01-07 | 济南浪潮数据技术有限公司 | Clock synchronization method, system, device and medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106209291A (en) * | 2016-08-30 | 2016-12-07 | 京信通信技术(广州)有限公司 | Clock source list update, clock synchronizing method and the system that base station clock synchronizes |
| CN108064080A (en) * | 2018-01-02 | 2018-05-22 | 京信通信系统（中国）有限公司 | The clock synchronizing method and device of base station equipment |
| US10257798B1 (en) * | 2018-05-18 | 2019-04-09 | OPNT Holding B.V. | Synchronizing clocks in a wireless system |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101923315A (en) * | 2009-06-17 | 2010-12-22 | 华东电力试验研究院有限公司 | Time synchronization method of electric power system and device thereof |
| EP3035569B1 (en) * | 2014-12-12 | 2023-11-22 | Net Insight AB | Method of time tansfer in a communication network |
| CN108260200A (en) * | 2018-02-27 | 2018-07-06 | 广州钟鼎木林网络技术有限公司 | The method and system that a kind of more synchronisation sources synchronize |
-
2020
- 2020-11-24 CN CN202011330584.0A patent/CN112398568B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106209291A (en) * | 2016-08-30 | 2016-12-07 | 京信通信技术(广州)有限公司 | Clock source list update, clock synchronizing method and the system that base station clock synchronizes |
| CN108064080A (en) * | 2018-01-02 | 2018-05-22 | 京信通信系统（中国）有限公司 | The clock synchronizing method and device of base station equipment |
| US10257798B1 (en) * | 2018-05-18 | 2019-04-09 | OPNT Holding B.V. | Synchronizing clocks in a wireless system |
Non-Patent Citations (1)
| Title |
|---|
| 《基于IEEE1588实现电网多时钟源时间同步系统》;徐开;《动力与电气工程》;20101123;正文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112398568A (en) | 2021-02-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102237941B (en) | Time synchronization system and method | |
| EP2469765B1 (en) | Method and system for implementing time synchronization in local area network (lan) | |
| EP2467976B1 (en) | Synchronization distribution in microwave backhaul networks | |
| CN111162862B (en) | Distributed multi-network element clock transmission system | |
| CN102598556B (en) | For the method and apparatus of optimizing packet timing transport | |
| CN102104476B (en) | Clock synchronization device and method | |
| US6816818B2 (en) | Method, clock generator module and receiver module for synchronizing a receiver module | |
| CN102013931B (en) | Time synchronization method and system, salve timing device and main timing device | |
| US8689035B2 (en) | Communication system, communication interface, and synchronization method | |
| EP2595331A2 (en) | Communication apparatus for performing time synchronization | |
| CN107896134A (en) | High-precision modularized time synchronization equipment | |
| JPH0267033A (en) | Network synchronizing system | |
| CN102932083B (en) | A kind of method and apparatus during microwave synchronization pair | |
| US4926446A (en) | Method and apparatus for precision time distribution in telecommunication networks | |
| WO2012075881A1 (en) | Ieee1588-based sampled value multi-interface synchronization system for multiple slave clocks | |
| CN103684727B (en) | A kind of method for synchronizing time and device of optical transfer network asynchronous network | |
| CN106301378B (en) | A kind of high-speed DAC synchronous method and circuit | |
| CN111954295B (en) | Time and precision considered synchronization maintaining method and system for TDD-LTE (time division Duplex-Long term evolution) equipment | |
| CN109495203A (en) | A kind of recovery system of PTP from clock | |
| CN112398568B (en) | System and method for synchronizing clocks in multiple cells | |
| US9893826B2 (en) | Method for retaining clock traceability over an asynchronous interface | |
| EP2837117B1 (en) | Clock switching algorithm based on preferred clock source | |
| Schwartz et al. | Modern trends in the development of network synchronization systems. From plesiochronous to coherent networks | |
| US20230050042A1 (en) | Clock determining method and related apparatus | |
| US11835999B2 (en) | Controller which adjusts clock frequency based on received symbol rate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20231227 Address after: Building A, Runhui Science and Technology Park, No. 18 Shenzhou Road, Huangpu District, Guangzhou City, Guangdong Province, 510663 (self numbered 301, 3rd floor) Patentee after: Guangzhou New Generation Chip Technology Co.,Ltd. Address before: No.23 Nanxiang 2nd Road, Huangpu District, Guangzhou, Guangdong 510656 Patentee before: GUANGDONG NEW GENERATION COMMUNICATION AND NETWORK INNOVATION INSTITUTE |
|
| TR01 | Transfer of patent right |