CN116633282B - Bias circuit and power amplifier - Google Patents

Bias circuit and power amplifier Download PDF

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Publication number
CN116633282B
CN116633282B CN202310717314.2A CN202310717314A CN116633282B CN 116633282 B CN116633282 B CN 116633282B CN 202310717314 A CN202310717314 A CN 202310717314A CN 116633282 B CN116633282 B CN 116633282B
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nmos tube
bias voltage
voltage
nmos
current source
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CN116633282A (en
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王伟威
刘国政
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Shanghai Taorun Semiconductor Co ltd
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Shanghai Taorun Semiconductor Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/447—Indexing scheme relating to amplifiers the amplifier being protected to temperature influence
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/522—Indexing scheme relating to amplifiers the bias or supply voltage or current of the gate side of a FET amplifier being controlled to be on or off by a switch

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

The invention discloses a bias circuit and a power amplifier, wherein the bias circuit comprises: the power supply circuit comprises a first adjustable current source, a first bias voltage module and a second bias voltage module, wherein the first adjustable current source, the first bias voltage module and the second bias voltage module are arranged between a power supply voltage and ground; the first bias voltage module is externally connected with an adjustable reference voltage at one input end and connected with the first adjustable current source at the other input end; under the control of the adjustable reference voltage and the first adjustable current source, outputting a first bias voltage; the second bias voltage module is characterized in that one input end of the second bias voltage module is externally connected with an adjustable reference voltage, the other input end of the second bias voltage module is connected with the current mirrored by the first adjustable current source, and the second bias voltage is output under the control of the adjustable reference voltage and the first adjustable current source; the first bias voltage is less than the second bias voltage. The invention can reduce the influence of PVT variation on the performance of the power amplifier and improve the reliability of the bias circuit.

Description

Bias circuit and power amplifier
Technical Field
The invention relates to the field of integrated circuit design, in particular to a bias circuit and a power amplifier.
Background
With the continuous development and progress of deep submicron process technology, the voltage-resisting capability of the MOS transistor is smaller and smaller, but for a power amplifier used in a wireless communication system, a higher power supply voltage is required in order to output higher power, and in order to avoid damage to devices caused by overpressure during operation of the transistor, a common-source common-gate (cascoded) structure is generally adopted, wherein a common-source transistor uses a thin gate transistor, and a common-gate transistor uses a thick gate transistor.
Bao Shanguan can only withstand lower voltages, and thick gate tubes can generally withstand higher voltages. Such a bias voltage of the cascode PA is unsuitable, and the performance changes greatly when the Process Voltage Temperature (PVT) changes.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a bias circuit and a power amplifier.
Specifically, the technical scheme of the invention is as follows:
in one aspect, a bias circuit includes a first adjustable current source established between a supply voltage and ground, a first bias voltage module, a second bias voltage module;
the first bias voltage module is externally connected with an adjustable reference voltage at one input end and connected with the first adjustable current source at the other input end; under the control of the adjustable reference voltage and the first adjustable current source, outputting a first bias voltage;
The second bias voltage module is characterized in that one input end of the second bias voltage module is externally connected with the adjustable reference voltage, the other input end of the second bias voltage module is connected with the current mirrored by the first adjustable current source, and the second bias voltage is output under the control of the adjustable reference voltage and the first adjustable current source; the first bias voltage is less than the second bias voltage.
In some embodiments, an overvoltage protection module is also included,
The overvoltage protection module is connected with the first adjustable current source and is used for shunting the first adjustable current source when the overvoltage protection module is in an on state in the process of powering on the first bias voltage module and the second bias voltage module by the first adjustable current source;
when the first adjustable current source finishes electrifying the first bias voltage module, and the overvoltage protection module is in a closed state, the first bias voltage module outputs the first bias voltage, and the second bias voltage module outputs the second bias voltage.
In some embodiments, the first bias voltage module includes a first operational amplifier, a second NMOS transistor;
The drain electrode of the second NMOS tube is connected with the positive input end of the first operational amplifier, the grid electrode of the second NMOS tube is connected with the output end of the first operational amplifier, the source electrode of the second NMOS tube is grounded, and the negative input end of the first operational amplifier is connected with the adjustable reference voltage;
The first adjustable current source is respectively connected with the drain electrode of the second NMOS tube and the positive input end of the first operational amplifier, and the first adjustable current source provides current for the second NMOS tube so that the grid electrode of the second NMOS tube generates the first bias voltage under the control of the first adjustable current source and the adjustable reference voltage.
In some embodiments, the current mirror further comprises a first NMOS tube, wherein the first NMOS tube and the second NMOS tube form a current mirror;
The grid electrode of the first NMOS tube is connected with the output end of the first operational amplifier, and the grid electrode of the first NMOS tube outputs the first bias voltage;
the drain electrode of the first NMOS tube is connected with the second bias voltage module;
and the source stage of the first NMOS tube is grounded.
In some embodiments, the second bias voltage module includes a second operational amplifier and a third NMOS transistor,
The source electrode of the third NMOS tube is connected with the drain electrode of the first NMOS tube, the drain electrode of the third NMOS tube is connected with the power supply voltage, and the grid electrode of the third NMOS tube is connected with the output end of the second operational amplifier;
The negative input end of the second operational amplifier is connected with the source electrode of the third NMOS tube and the drain electrode of the second NMOS tube, and the positive input end of the second operational amplifier is connected with the adjustable reference voltage;
The third NMOS tube and the first NMOS tube are in a common-gate common-source structure, the current of the third NMOS tube is equal to that of the first NMOS tube, and the grid electrode of the third NMOS tube outputs the second bias voltage under the control of the first adjustable current source and the adjustable reference voltage.
In one embodiment, the overvoltage protection module comprises a second adjustable current source, an adjustable capacitor and an inverter submodule which are sequentially connected between a power supply voltage and ground, and a switch submodule;
the second adjustable current source is connected with the adjustable capacitor and is used for charging the adjustable capacitor through the enabling of the second adjustable current source in the power-on process of the first bias voltage module and providing a first voltage for the inverter submodule;
the inverter submodule is used for inverting the received first voltage in the power-on process of the first bias voltage module so as to enable the switch submodule to be in a working state and shunt the first adjustable current source;
After the first adjustable current source finishes powering up the first bias voltage module, the second adjustable current source provides a second voltage to the inverter submodule by charging the adjustable capacitor to be close to a power supply voltage value; and the inverter submodule inverts the received second voltage to enable the switch submodule to be in a closed state, so that the first bias voltage module outputs the first bias voltage and the second bias voltage module outputs the second bias voltage.
In some embodiments, the inverter submodule includes a first PMOS transistor and a fourth NMOS transistor,
The grid electrode of the first PMOS tube and the grid electrode of the fourth NMOS tube are connected with the adjustable capacitor, the source electrode of the first PMOS tube is connected with the power supply voltage, and the drain electrode of the first PMOS tube and the drain electrode of the fourth NMOS tube are connected with the switch submodule;
The source electrode of the fourth NMOS tube is grounded;
When the voltage values of the grid electrode of the first PMOS tube and the grid electrode of the fourth NMOS tube are smaller than a preset value, the fourth NMOS tube is cut off, the first PMOS tube is conducted, and the drain electrode of the first PMOS tube and the drain electrode of the fourth NMOS tube output the value of the power supply voltage; when the voltage values of the grid electrode of the first PMOS tube and the grid electrode of the fourth NMOS tube are larger than a preset value, the first PMOS tube is cut off, the fourth NMOS tube is conducted, and the voltage values of the drain electrode of the first PMOS tube and the drain electrode of the fourth NMOS tube are zero.
In some embodiments, the switch submodule includes a fifth NMOS transistor and a sixth NMOS transistor;
The grid electrode of the fifth NMOS tube is connected with the drain electrode of the first PMOS tube and the drain electrode of the fourth NMOS tube, the source electrode of the fifth NMOS tube is grounded, and the drain electrode of the fifth NMOS tube is connected with the source electrode of the sixth NMOS tube;
The grid electrode of the sixth NMOS tube is connected with the drain electrode of the sixth NMOS tube, and the drain electrode of the sixth NMOS tube is connected with the drain electrode of the second NMOS tube;
when the drain electrode of the first PMOS tube and the drain electrode of the fourth NMOS tube output the value of the power supply voltage, the fifth NMOS tube is conducted, the sixth NMOS tube shunts the current of the first adjustable current source so that the drain voltage of the second MOS tube does not exceed a preset peak voltage, wherein the gate voltage of the second MOS tube is lower than a first preset bias voltage value, and the drain voltage of the second MOS tube is lower than a second preset bias voltage value;
when the voltage value output by the drain electrode of the first PMOS tube and the drain electrode of the fourth NMOS tube is zero, the fifth NMOS tube is cut off, and the sixth NMOS tube does not shunt the first current, so that the gate voltage of the second MOS tube is equal to a first preset bias voltage value, and the drain voltage of the second MOS tube is equal to a second preset bias voltage value.
On the other hand, the invention also provides a power amplifier, which comprises any one of the bias circuits in the embodiment, an amplifying circuit, a first transformer and a second transformer;
The bias circuit is connected with the amplifying circuit and is used for providing bias voltage for the amplifying circuit so that the amplifying circuit works in a saturation region;
The first transformer is connected with the amplifying circuit and is used for providing a first signal for the amplifying circuit;
The amplifying circuit is used for amplifying the first signal to generate a second signal under the action of the bias voltage, wherein the second signal is larger than the first signal in power;
The second transformer is connected with the amplifying circuit and is used for receiving the second signal and outputting the second signal to the antenna equipment.
In some embodiments, the amplifying circuit includes a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor, where the seventh NMOS transistor and the eighth NMOS transistor are common source transistors, and the ninth NMOS transistor and the tenth NMOS transistor are common gate transistors;
The grid electrode of the seventh NMOS tube and the grid electrode of the eighth NMOS tube are connected with the grid electrode of the first NMOS tube through the first transformer, the drain electrode of the seventh NMOS tube is connected with the source electrode of the ninth NMOS tube, the drain electrode of the eighth NMOS tube is connected with the source electrode of the tenth NMOS tube, the source electrodes of the seventh NMOS tube and the eighth NMOS tube are grounded, and the ratio of the width to length of the first NMOS tube to the ratio of the second NMOS tube to the ratio of the seventh NMOS tube to the ratio of the width to length of the eighth NMOS tube are 1: n;
The grid electrode of the ninth NMOS tube and the grid electrode of the tenth NMOS tube are connected with the grid electrode of the third NMOS tube, the drain electrode of the ninth NMOS tube and the drain electrode of the tenth NMOS tube are connected with the power supply voltage through the second transformer, and the ratio of the width to the length of the third NMOS tube to the ratio of the width to the length of the ninth NMOS tube to the ratio of the width to the length of the tenth NMOS tube is 1: n.
Compared with the prior art, the invention has the following beneficial effects:
the invention further controls the output of the bias voltage by precisely controlling the current source and the reference voltage of the bias circuit, thereby reducing the influence of PVT variation on the performance of the power amplifier, and simultaneously, the invention designs a power-on overvoltage protection circuit to improve the reliability of the bias circuit.
Drawings
The above features, technical features, advantages and implementation of the present invention will be further described in the following description of preferred embodiments with reference to the accompanying drawings in a clear and easily understood manner.
FIG. 1 is a circuit block diagram of one embodiment of a bias circuit of the present invention;
FIG. 2 is a schematic diagram of the power-up process voltage of a bias circuit according to one embodiment of the present invention;
FIG. 3 is a schematic diagram of the power-up process voltage of a bias circuit according to one embodiment of the present invention;
Fig. 4 is a circuit configuration diagram of an embodiment of a power amplifier of the present invention.
Detailed Description
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will explain the specific embodiments of the present invention with reference to the accompanying drawings. It is evident that the drawings in the following description are only examples of the invention, from which other drawings and other embodiments can be obtained by a person skilled in the art without inventive effort.
For simplicity of the drawing, only the parts relevant to the invention are schematically shown in each drawing, and they do not represent the actual structure thereof as a product. Additionally, in order to simplify the drawing for ease of understanding, components having the same structure or function in some of the drawings are shown schematically with only one of them, or only one of them is labeled. Herein, "a" means not only "only this one" but also "more than one" case.
It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
In this context, it should be noted that the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected, unless explicitly stated or limited otherwise; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
In addition, in the description of the present application, the terms "first," "second," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.
In one embodiment, referring to fig. 1 of the specification, the bias circuit provided by the invention comprises a first adjustable current source I1, a first bias voltage module 10 and a second bias voltage module 20, wherein the first adjustable current source I1 is arranged between a power supply voltage and ground;
The first bias voltage module 10 is externally connected with an adjustable reference voltage Vref at one input end and connected with a first adjustable current source I1 at the other input end; under the control of an adjustable reference voltage Vref and a first adjustable current source I1, outputting a first bias voltage V1; the second bias voltage module 20, one input end is externally connected with an adjustable reference voltage Vref, the other input end is connected with the current mirrored by the first adjustable current source I1, and the second bias voltage V2 is output under the control of the adjustable reference voltage Vref and the first adjustable current source I1; the first bias voltage V1 is smaller than the second bias voltage V2.
In this embodiment, the output of the first bias voltage V1 and the second bias voltage V2 is further controlled by precisely controlling the adjustable current sources I1 of the first bias voltage module 10 and the second bias voltage module 20 and the adjustable reference voltage Vref, so as to reduce the performance influence of PVT variation on the power amplifier.
In one embodiment, referring to fig. 1 of the specification, the first bias voltage module 10 includes a first operational amplifier OPA1 and a second NMOS transistor MN2; the drain electrode of the second NMOS tube MN2 is connected with the positive input end of the first operational amplifier OPA1, the grid electrode of the second NMOS tube MN2 is connected with the output end of the first operational amplifier OPA1, the source electrode of the second NMOS tube MN2 is grounded, and the negative input end of the first operational amplifier OPA1 is connected with the adjustable reference voltage Vref; the first adjustable current source I1 is connected to the drain of the second NMOS MN2 and the positive input terminal of the first operational amplifier OPA1, respectively, and the first adjustable current source I1 provides current for the second NMOS MN2, so that the gate of the second NMOS MN2 generates the first bias voltage V1 under the control of the first adjustable current source I1 and the adjustable reference voltage Vref.
In one embodiment, the first bias voltage module 10 further includes a first NMOS transistor MN1, where the first NMOS transistor MN1 and the second NMOS transistor MN2 form a current mirror; the second bias voltage module 20 includes a second operational amplifier OPA2 and a third NMOS transistor MN3, a gate of the first NMOS transistor MN1 is connected to an output end of the first operational amplifier OPA1, and a gate of the first NMOS transistor MN1 outputs a first bias voltage V1; the drain electrode of the first NMOS tube MN1 is connected with the second bias voltage module 20, and the current of the first NMOS tube MN1 is equal to the current of the third NMOS tube MN 3; the source of the first NMOS tube MN1 is grounded; the source electrode of the third NMOS tube MN3 is connected with the drain electrode of the first NMOS tube MN1, the drain electrode of the third NMOS tube MN3 is connected with the power supply voltage, and the grid electrode of the third NMOS tube MN3 is connected with the output end of the second operational amplifier OPA 2; the negative input end of the second operational amplifier OPA2 is connected with the source electrode of the third NMOS tube MN3 and the drain electrode of the first NMOS tube MN1, and the positive input end of the second operational amplifier OPA2 is connected with the reference voltage Vref; the third NMOS tube MN3 and the first NMOS tube MN1 are in a common-gate common-source structure, the current of the third NMOS tube MN3 is equal to that of the first NMOS tube MN1, and the grid electrode of the third NMOS tube MN3 outputs a second bias voltage V2 under the control of the first adjustable current source and the reference voltage Vref.
Specifically, the bias circuit of the invention comprises mirror proportion thin gate tubes MN2 and MN1, a thick gate tube MN3, an adjustable current source I1, an adjustable reference voltage Vref, an operational amplifier OPA1 for assisting in generating V1 and an operational amplifier OPA2 for assisting in generating V2. The sizes of V1 and V2 can be adjusted by controlling the sizes of I1 and Vref, so that the PA is biased under proper voltage, the direct current of the PA accurately mirrors the size of the current source I1, and the influence of PVT variation on the PA is reduced; the V1 and V2 are produced with the aid of OPA1 and OPA2, and the specific V1 and V2 production method is as follows: assuming that the magnitude of the current source I1 is Idc1, the gate voltage Vbias1 generated by MN2 is injected into MN2, the gate voltage Vbias1 generated by MN2 is connected with the gate electrode and V1 of MN1, the drain voltage of MN2 is equal to Vref by the operational amplifier OPA1, the drain voltage of MN 1/source voltage of MN3 is equal to Vref by the operational amplifier OPA2, MN2 and MN1 are the same in size and the gate, source and drain voltages are the same, MN2 and MN1 are precisely mirror images, the flowing currents are the same, MN3 and MN1 form a common-source common-gate structure, the flowing current of MN3 is equal to the current of MN1, and Vgs of MN3 is determined, so that the gate voltage vg=vref+vgs of MN3, the gate voltage of MN3 is equal to Vbias2 and is connected to V2.
Specifically, in this embodiment, for example, referring to fig. 2 of the specification, at time T1, the I1 current is turned on, the current level 0 becomes Idc1, the gate voltage of MN2 at time T1 is equal to 0, idc1 charges the drain port capacitance of MN2, the drain voltage and gate voltage of MN2 rise in the period of time T1-T2, the drain voltage rising speed is determined by Idc1, the node capacitance of N1 and the gate voltage level of MN2, and the gate voltage rising speed is determined by the loop bandwidth of the feedback circuit formed by OPA1 and MN 2; at the time of T2, the drain voltage of MN2 reaches Vref, but the gate voltage of MN2 is smaller than Vbias1, the leakage current of MN2 is smaller than Idc1, and the period of T2-T3 is that I1 continuously charges the N1 node capacitor, and the drain voltage of MN2 continuously rises; at time T3, the gate voltage of MN2 reaches Vbias1, the leakage current of MN2 is equal to Idc1, the leakage voltage of MN2 reaches a peak, the magnitude of the leakage voltage is Vpak 1, and the period of T3-T4, due to the action of a feedback circuit, the gate voltage of MN2 can rise to be higher than the value of Vpak 1, the leakage current of MN2 is larger than Idc1, the capacitance of N1 node discharges, the leakage voltage of MN2 drops, finally, at time T4, the gate voltage and the leakage voltage of MN2 respectively reach final values Vpas 1 and Vref, and during the power-on process, the leakage voltage of MN2 can reach the value of Vpak 1, and the magnitude of Vpak 1 is related to the magnitude of the power supply voltage VDD2 of a bias circuit, the magnitude of Idc1 and the loop bandwidth fed back by OPA1 and MN 2.
In one embodiment, and with reference to fig. 1 of the drawings, the bias circuit further comprises an overvoltage protection module 30,
The overvoltage protection module 30 is connected with the first adjustable current source I1, and is configured to shunt the first adjustable current source I1 when the overvoltage protection module 30 is in an on state during the power-on process of the first and second bias voltage modules 10 and 20 by the first adjustable current source I1; when the first adjustable current source I1 completes the power-up of the first bias voltage module 10, the overvoltage protection module 30 is in the off state, so that the first bias voltage module 10 outputs the first bias voltage V1, and the second bias voltage module 20 outputs the second bias voltage V2.
In one embodiment, referring to fig. 1 of the specification, the overvoltage protection module 30 includes a second adjustable current source, an adjustable capacitor, an inverter sub-module, and a switch sub-module, which are sequentially connected between a power supply voltage and ground; the second adjustable current source I2 and the adjustable capacitor C2 are connected to each other, and are used for charging the adjustable capacitor C2 through the second adjustable current source I2 during the power-up process of the first bias voltage module 10, and providing the first voltage to the inverter submodule; the inverter submodule is used for inverting the received first voltage in the power-on process of the first bias voltage module 10 so as to enable the switch submodule to be in a working state and shunt the first adjustable current source I1; after the first adjustable current source I1 completes the power-up of the first bias voltage module 10, the second adjustable current source I2 provides the second voltage to the inverter submodule by charging the adjustable capacitor C2 to a value close to the power supply voltage; the inverter sub-module inverts the received second voltage to make the switch sub-module in an off state, so that the first bias voltage module 10 outputs the first bias voltage V1 and the second bias voltage module 20 outputs the second bias voltage V2.
In one embodiment, referring to fig. 1 of the specification, the inverter submodule includes a first PMOS transistor MP1 and a fourth NMOS transistor MN4, where a gate of the first PMOS transistor MP1 and a gate of the fourth NMOS transistor MN4 are connected to the adjustable capacitor C2, a source of the first PMOS transistor MP1 is connected to a supply voltage, and a drain of the first PMOS transistor MP1 and a drain of the fourth NMOS transistor MN4 are connected to the switch submodule; the source electrode of the fourth NMOS tube MN4 is grounded; when the voltage values of the gates of the first PMOS transistor MP1 and the fourth NMOS transistor MN4 are smaller than the preset value, the fourth NMOS transistor MN4 is turned off, the first PMOS transistor MP1 is turned on, and the drains of the first PMOS transistor MP1 and the fourth NMOS transistor MN4 output the value of the power supply voltage; when the voltage values of the gates of the first PMOS transistor MP1 and the fourth NMOS transistor MN4 are greater than the preset value, the first PMOS transistor MP1 is turned off, the fourth NMOS transistor MN4 is turned on, and the voltage values of the drains of the first PMOS transistor MP1 and the fourth NMOS transistor MN4 are zero.
In one embodiment, the switch submodule includes a fifth NMOS transistor MN5 and a sixth NMOS transistor MN6; the grid electrode of the fifth NMOS tube MN5 is connected with the drain electrode of the first PMOS tube and the drain electrode of the fourth NMOS tube, the source electrode of the fifth NMOS tube MN5 is grounded, and the drain electrode of the fifth NMOS tube MN5 is connected with the source electrode of the sixth NMOS tube MN6; the grid electrode of the sixth NMOS tube MN6 is connected with the drain electrode of the sixth NMOS tube MN6, and the drain electrode of the sixth NMOS tube MN6 is connected with the drain electrode of the second NMOS tube MN 2; when the drain electrode of the first PMOS transistor MP1 and the drain electrode of the fourth NMOS transistor MN4 output the value of the power supply voltage, the fifth NMOS transistor MN5 is turned on, and the sixth NMOS transistor MN6 shunts the current of the first adjustable current source I1 so that the drain voltage of the second NMOS transistor MN2 does not exceed the preset peak voltage, wherein the gate voltage of the second NMOS transistor MN2 is lower than the first preset bias voltage value, and the drain voltage of the second NMOS transistor MN2 is lower than the second preset bias voltage value; when the voltage value output by the drain electrode of the first PMOS transistor MP1 and the drain electrode of the fourth NMOS transistor MN4 is zero, the fifth NMOS transistor MN5 is turned off, and the sixth NMOS transistor MN6 does not shunt the first current, so that the gate voltage of the second MOS transistor MN2 is equal to the first preset bias voltage value, and the drain voltage of the second NMOS transistor MN2 is equal to the second preset bias voltage value.
Specifically, for example, referring to fig. 3 of the specification, the embodiment includes an adjustable current source I2, an adjustable capacitor C2, and thick gate transistors MN5, MN6, MP1, MN4, and the diode structure formed by MN6 suppresses the increase of the N1 voltage during the power-up process; and when the power-on is finished, the MN6 is closed, and the core part of the biasing circuit is not influenced, so that the function of protecting the MN2 tube is achieved, and the reliability of the circuit is improved.
In the power-on process, an I2 current source charges C2, the voltage of an N3 node is slowly increased, the increasing speed is dependent on the capacitance of the N3 node and the size of I2, the power-on speed of the N3 node can be controlled by adjusting the sizes of the C2 and I2, in the period of T1-T5, the output of an inverter formed by MP1 and MN4 is VDD2, namely MN5 and MN6 are in an on state, an MN6 forms a diode structure MOS tube, the higher the voltage of the N1 node is, the larger the current flowing through MN6 is, the Idc1 current is divided into a part, the increase of the voltage of the N1 node is further inhibited, and in the moment of T3, the voltage of the N1 node, namely the MN2 drain voltage reaches the maximum Vpak 2; at time T4, the gate and drain voltages of MN2 are stable and smaller than the target values Vbias1 and Vref, which is the result of the shunting of MN6, at time T5, the outputs of the inverters formed by MP1 and MN4 are 0, MN5 and MN6 are closed, MN6 is not shunted any more, the gate and drain voltages of MN2 are finally stable to the target values Vbias1 and Vref, and the proper size of MN6 is designed so that Vpak 2 cannot exceed the preset voltage, thereby avoiding the overvoltage of the voltage between the drain gate and the drain source of MN2 and improving the reliability of the circuit.
In one embodiment, the present invention further provides a power amplifier, referring to fig. 4 of the specification, including a bias circuit as described in any one of the above embodiments, and further including an amplifying circuit 40, a first transformer 50, and a second transformer 60; a bias circuit connected to the amplifying circuit 40 for providing a bias voltage to the amplifying circuit 40 to operate the amplifying circuit 40 in a saturation region; a first transformer 50 connected to the amplifying circuit 40 for providing a first signal to the amplifying circuit 40; an amplifying circuit 40 for amplifying the first signal to generate a second signal under the action of the bias voltage, wherein the second signal is larger than the first signal in power; the second transformer 60 is connected to the amplifying circuit 40, and is configured to receive the second signal and output the second signal to the antenna device.
Specifically, the amplifying circuit 40 includes a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, and a tenth NMOS transistor, where the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 are common source transistors, and the ninth NMOS transistor MN9 and the tenth NMOS transistor MN10 are common gate transistors; the grid electrode of the seventh NMOS tube MN7 and the grid electrode of the eighth NMOS tube MN8 are connected with the grid electrode of the first NMOS tube MN1 through a first transformer, the drain electrode of the seventh NMOS tube MN7 is connected with the source electrode of the ninth NMOS tube MN9, the drain electrode of the eighth NMOS tube MN8 is connected with the source electrode of the tenth NMOS tube, the source electrode of the seventh NMOS tube MN7 and the source electrode of the eighth NMOS tube MN8 are grounded, and the ratio of the width to length of the first NMOS tube MN1, the second NMOS tube MN2 to the width to length of the seventh NMOS tube MN7 to the eighth NMOS tube MN8 is 1: n; the gate of the ninth NMOS transistor MN9 and the gate of the tenth NMOS transistor MN10 are connected to the gate of the third NMOS transistor MN3, the drain of the ninth NMOS transistor MN9 and the drain of the tenth NMOS transistor MN10 are connected to the power supply voltage through the second transformer 60, and the ratio of the width to length of the third NMOS transistor MN3 to the ratio of the width to length of the ninth NMOS transistor MN9 to the ratio of the width to length of the tenth NMOS transistor MN10 are 1: n.
In this embodiment, MN2/MN1 and MN7/MN8 are thin gate tubes, the ratio of W/L of MN2/MN1 to W/L of MN7/MN8 is 1:N, mn3 and MN9/MN10 are thick gate tubes, and the ratio of W/L of MN3 to W/L of MN9/MN10 is 1:N. The channel length modulation effect of the deep submicron process is usually not negligible, the channel length modulation effect can affect the accuracy of current mirror image, the current mirror image of the cascode structure can be regarded as a more accurate mirror image method, MN1/MN3 flows through current equal to Idc1, and then MN7 and MN9 flow through current more accurately equal to nc 1. The performance of the PA, the size of the flowing direct current and the bias voltage have a strong relation, the performance of the PA can be optimized and improved by adjusting and controlling the sizes of Idc1 and Vref, the Idc1 is flexibly designed, idc1 is designed into a current Proportional To Absolute Temperature (PTAT) or a current inversely proportional to absolute temperature (CTAT), the influence of temperature on the PA can be eliminated, the Idc1 can be calibrated to obtain a value which does not change along with the process, the influence of the process change on the PA can be eliminated, the influence of the power supply voltage on Idc1 is small, and therefore, the bias structure can reduce the influence of PVT change on the performance of the PA. V1 and OPA1 are connected together, assuming that the open loop output impedance of OPA1 is R out1 and the loop gain of the feedback structure formed by MN2 is A close1, the closed loop output impedance of OPA1 isR out1 is designed to be lower, meanwhile, a larger closed loop gain A close1 is designed, and the low output impedance of the bias circuit of the V1 node can be obtained. V2 and OPA2 are connected together, assuming that the open loop output impedance of OPA2 is R out2 and the loop gain of the feedback structure formed by MN3 is a close2, the closed loop output impedance of OPA1 isR out2 is designed to be lower, meanwhile, a larger closed loop gain A close2 is designed, so that the low output impedance of the bias circuit of the V2 node can be obtained, and the lower output impedance is beneficial to the improvement of the performance of the PA.
It should be noted that the above embodiments can be freely combined as needed. The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.

Claims (9)

1. The bias circuit is characterized by comprising a first adjustable current source, a first bias voltage module and a second bias voltage module, wherein the first adjustable current source, the first bias voltage module and the second bias voltage module are arranged between a power supply voltage and ground;
the first bias voltage module is externally connected with an adjustable reference voltage at one input end and connected with the first adjustable current source at the other input end; under the control of the adjustable reference voltage and the first adjustable current source, outputting a first bias voltage;
the second bias voltage module is characterized in that one input end of the second bias voltage module is externally connected with the adjustable reference voltage, the other input end of the second bias voltage module is connected with the current mirrored by the first adjustable current source, and the second bias voltage is output under the control of the adjustable reference voltage and the first adjustable current source; the first bias voltage is less than the second bias voltage;
further comprises: the overvoltage protection module is arranged on the upper surface of the base,
The overvoltage protection module is connected with the first adjustable current source and is used for shunting the first adjustable current source when the overvoltage protection module is in an on state in the process of powering on the first bias voltage module and the second bias voltage module by the first adjustable current source;
when the first adjustable current source finishes electrifying the first bias voltage module, and the overvoltage protection module is in a closed state, the first bias voltage module outputs the first bias voltage, and the second bias voltage module outputs the second bias voltage.
2. The bias circuit of claim 1 wherein said first bias voltage module comprises a first operational amplifier, a second NMOS transistor;
The drain electrode of the second NMOS tube is connected with the positive input end of the first operational amplifier, the grid electrode of the second NMOS tube is connected with the output end of the first operational amplifier, the source electrode of the second NMOS tube is grounded, and the negative input end of the first operational amplifier is connected with the adjustable reference voltage;
The first adjustable current source is respectively connected with the drain electrode of the second NMOS tube and the positive input end of the first operational amplifier, and the first adjustable current source provides current for the second NMOS tube so that the grid electrode of the second NMOS tube generates the first bias voltage under the control of the first adjustable current source and the adjustable reference voltage.
3. The bias circuit of claim 2 wherein said first bias voltage module further comprises a first NMOS transistor, said first NMOS transistor and said second NMOS transistor forming a current mirror;
The grid electrode of the first NMOS tube is connected with the output end of the first operational amplifier, and the grid electrode of the first NMOS tube outputs the first bias voltage;
the drain electrode of the first NMOS tube is connected with the second bias voltage module;
and the source stage of the first NMOS tube is grounded.
4. A biasing circuit according to claim 3, wherein said second bias voltage module comprises a second operational amplifier and a third NMOS transistor,
The source electrode of the third NMOS tube is connected with the drain electrode of the first NMOS tube, the drain electrode of the third NMOS tube is connected with the power supply voltage, and the grid electrode of the third NMOS tube is connected with the output end of the second operational amplifier;
the negative input end of the second operational amplifier is connected with the source electrode of the third NMOS tube and the drain electrode of the first NMOS tube, and the positive input end of the second operational amplifier is connected with the adjustable reference voltage;
The third NMOS tube and the first NMOS tube are in a common-gate common-source structure, the current of the third NMOS tube is equal to that of the first NMOS tube, and the grid electrode of the third NMOS tube outputs the second bias voltage under the control of the first adjustable current source and the adjustable reference voltage.
5. The bias circuit of claim 1 wherein said overvoltage protection module includes a second adjustable current source, an adjustable capacitor, an inverter sub-module, and a switch sub-module connected in sequence between said supply voltage and ground;
the second adjustable current source is connected with the adjustable capacitor and is used for charging the adjustable capacitor through the enabling of the second adjustable current source in the power-on process of the first bias voltage module and providing a first voltage for the inverter submodule;
the inverter submodule is used for inverting the received first voltage in the power-on process of the first bias voltage module so as to enable the switch submodule to be in a working state and shunt the first adjustable current source;
After the first adjustable current source finishes powering up the first bias voltage module, the second adjustable current source provides a second voltage to the inverter submodule by charging the adjustable capacitor to be close to a power supply voltage value; and the inverter submodule inverts the received second voltage to enable the switch submodule to be in a closed state, so that the first bias voltage module outputs the first bias voltage and the second bias voltage module outputs the second bias voltage.
6. The biasing circuit of claim 5, wherein the inverter submodule includes a first PMOS tube and a fourth NMOS tube,
The grid electrode of the first PMOS tube and the grid electrode of the fourth NMOS tube are connected with the adjustable capacitor, the source electrode of the first PMOS tube is connected with the power supply voltage, and the drain electrode of the first PMOS tube and the drain electrode of the fourth NMOS tube are connected with the switch submodule;
The source electrode of the fourth NMOS tube is grounded;
When the voltage values of the grid electrode of the first PMOS tube and the grid electrode of the fourth NMOS tube are smaller than a preset value, the fourth NMOS tube is cut off, the first PMOS tube is conducted, and the drain electrode of the first PMOS tube and the drain electrode of the fourth NMOS tube output the value of the power supply voltage; when the voltage values of the grid electrode of the first PMOS tube and the grid electrode of the fourth NMOS tube are larger than a preset value, the first PMOS tube is cut off, the fourth NMOS tube is conducted, and the voltage values of the drain electrode of the first PMOS tube and the drain electrode of the fourth NMOS tube are zero.
7. The biasing circuit of claim 6, wherein said switch submodule includes a fifth NMOS transistor and a sixth NMOS transistor;
The grid electrode of the fifth NMOS tube is connected with the drain electrode of the first PMOS tube and the drain electrode of the fourth NMOS tube, the source electrode of the fifth NMOS tube is grounded, and the drain electrode of the fifth NMOS tube is connected with the source electrode of the sixth NMOS tube;
The grid electrode of the sixth NMOS tube is connected with the drain electrode of the sixth NMOS tube, and the drain electrode of the sixth NMOS tube is connected with the first adjustable current source;
When the drain electrode of the first PMOS tube and the drain electrode of the fourth NMOS tube output the value of the power supply voltage, the fifth NMOS tube is conducted, the sixth NMOS tube shunts the current of the first adjustable current source so that the drain voltage of the second NMOS tube of the first bias voltage module does not exceed a preset peak voltage, wherein the gate voltage of the second NMOS tube is lower than a first preset bias voltage value, and the drain voltage of the second NMOS tube is lower than a second preset bias voltage value;
When the voltage value output by the drain electrode of the first PMOS tube and the drain electrode of the fourth NMOS tube is zero, the fifth NMOS tube is cut off, and the sixth NMOS tube does not shunt the current of the first adjustable current source, so that the gate voltage of the second NMOS tube is equal to a first preset bias voltage value, and the drain voltage of the second NMOS tube is equal to a second preset bias voltage value.
8. A power amplifier comprising a bias circuit according to any one of claims 1 to 7, further comprising an amplifying circuit, a first transformer and a second transformer;
The bias circuit is connected with the amplifying circuit and is used for providing bias voltage for the amplifying circuit so that the amplifying circuit works in a saturation region;
The first transformer is connected with the amplifying circuit and is used for providing a first signal for the amplifying circuit;
The amplifying circuit is used for amplifying the first signal to generate a second signal under the action of the bias voltage, wherein the second signal is larger than the first signal in power;
The second transformer is connected with the amplifying circuit and is used for receiving the second signal and outputting the second signal to the antenna equipment.
9. The power amplifier of claim 8, wherein the amplifying circuit comprises a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor, the seventh NMOS transistor and the eighth NMOS transistor being common source transistors, the ninth NMOS transistor and the tenth NMOS transistor being common gate transistors;
The grid electrode of the seventh NMOS tube and the grid electrode of the eighth NMOS tube receive the first bias voltage through the first transformer, the drain electrode of the seventh NMOS tube is connected with the source electrode of the ninth NMOS tube, the drain electrode of the eighth NMOS tube is connected with the source electrode of the tenth NMOS tube, and the source electrodes of the seventh NMOS tube and the eighth NMOS tube are grounded;
The grid electrode of the ninth NMOS tube and the grid electrode of the tenth NMOS tube receive the second bias voltage, and the drain electrode of the ninth NMOS tube and the drain electrode of the tenth NMOS tube are connected with a power supply voltage through the second transformer.
CN202310717314.2A 2023-06-16 2023-06-16 Bias circuit and power amplifier Active CN116633282B (en)

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CN111130473A (en) * 2019-12-24 2020-05-08 华东师范大学 76-81GHz CMOS full-integration power amplifier

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CN1398031A (en) * 2001-07-16 2003-02-19 松下电器产业株式会社 Mains
KR100635167B1 (en) * 2005-08-08 2006-10-17 삼성전기주식회사 Temperature compensated bias source circuit
TWI430565B (en) * 2010-12-10 2014-03-11 Novatek Microelectronics Corp Adaptive amplification circuit
CN204425299U (en) * 2015-01-09 2015-06-24 昆腾微电子股份有限公司 Power on/off detects reset circuit
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CN108123685A (en) * 2016-11-29 2018-06-05 意法半导体有限公司 Adjusting to RF amplifiers
CN111130473A (en) * 2019-12-24 2020-05-08 华东师范大学 76-81GHz CMOS full-integration power amplifier

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