CN116633280A

CN116633280A - Low noise amplifier and RF front-end module

Info

Publication number: CN116633280A
Application number: CN202310760490.4A
Authority: CN
Inventors: 赖志国; 杨清华
Original assignee: Suzhou Huntersun Electronics Co Ltd
Current assignee: Suzhou Huntersun Electronics Co Ltd
Priority date: 2023-06-26
Filing date: 2023-06-26
Publication date: 2023-08-22

Abstract

The embodiment of the application provides a low-noise amplifier and a radio frequency front-end module, wherein the low-noise amplifier comprises: the first signal input end, the first signal output end, the logic control unit and the first amplifying circuit and the second amplifying circuit are connected in parallel between the first signal input end and the first signal output end; the first amplifying circuit is used for amplifying the signal in a first gain mode; the first amplifying circuit comprises a two-stage amplifying unit for two-stage amplifying the signal; the second amplifying circuit is used for amplifying the signal in a second gain mode; the gain of the second gain mode is less than the gain of the first gain mode; the second amplifying circuit comprises a third amplifying unit; the logic control unit is used for controlling the first amplifying circuit or the second amplifying circuit to be conducted so as to select a first gain mode or a second gain mode to amplify the signal. The gain range of the low noise amplifier is ensured, and the linearity of the low gain gear can be improved.

Description

Low noise amplifier and RF front-end module

Technical Field

The present application relates to the field of radio frequency technologies, and in particular, to a low noise amplifier and a radio frequency front end module.

Background

The low noise amplifier (LowNoiseAmplifier, LNA) acts as a key module for the RF receiver, and its gain coverage and linearity are key indicators affecting its performance. Conventional low noise amplifiers typically employ passive attenuation structures to achieve low gain gears, but such structures are relatively simple and have insufficient linearity. The linearity of the amplifier can also be improved to some extent by increasing the bias voltage of the amplifier. But this approach adds additional power consumption.

How to improve the linearity of the corresponding gain gear while increasing the gain range of the LNA is an important technical problem that the art is constantly working to solve.

Disclosure of Invention

Accordingly, embodiments of the present application provide a low noise amplifier and a radio frequency front end module for solving at least one of the problems in the prior art.

In a first aspect, an embodiment of the present application provides a low noise amplifier, including: the first signal input end, the first signal output end, the logic control unit and the first amplifying circuit and the second amplifying circuit are connected in parallel between the first signal input end and the first signal output end; wherein,

the first signal input end is used for receiving signals;

The first signal output end is used for outputting a signal;

the first amplifying circuit is used for amplifying the signal in a first gain mode; the first amplifying circuit comprises a two-stage amplifying unit and is used for carrying out two-stage amplification on the signal; the first amplifying circuit includes: a first-stage amplifying unit and a second-stage amplifying unit;

the second amplifying circuit is used for amplifying the signal in a second gain mode; the second amplifying circuit comprises a first amplifying unit for amplifying the signal at one stage; the gain of the second gain mode is less than the gain of the first gain mode; the second amplifying circuit comprises a third amplifying unit;

the logic control unit is used for controlling the first amplifying circuit or the second amplifying circuit to be conducted so as to select the first gain mode or the second gain mode to amplify the signal.

With reference to the first aspect of the present application, in an optional implementation manner, the first stage amplifying unit includes a first common source tube, a first common gate tube and a first transistor; the second-stage amplifying unit comprises a second common-source tube, a second common-gate tube and a second transistor; the first transistor and the second transistor are used for receiving a conduction control signal of the logic control unit so as to respectively control whether the first-stage amplifying unit and the second-stage amplifying unit are conducted or not.

With reference to the first aspect of the present application, in an alternative implementation manner, a drain electrode of the first common source tube is connected to a source electrode of the first common gate tube, a source electrode of the first common source tube is connected to a drain electrode of the first transistor, and a gate electrode of the first common source tube is connected to the first signal input end; the source electrode of the first transistor is grounded; the drain electrode of the first common grid tube is connected with a power supply; the drain electrode of the second common source tube is connected with the source electrode of the second common gate tube, and the source electrode of the second common source tube is connected with the drain electrode of the second transistor; the drain electrode of the second common source tube is connected with the first signal output end; the grid electrode of the second common source tube is connected with the drain electrode of the first common gate tube; the source electrode of the second transistor is grounded; the drain electrode of the second common grid tube is connected with a power supply; the grid electrode of the first transistor and the grid electrode of the second transistor are used for receiving a conduction control signal of the logic control unit.

With reference to the first aspect of the present application, in an alternative embodiment, the third amplifying unit includes a third common-source transistor, a third common-gate transistor, a third transistor, a fourth transistor, and a fifth transistor; the drain electrode of the third common source tube is connected with the source electrode of the third common gate tube, the grid electrode of the third common source tube is connected with the drain electrode of the third transistor, and the source electrode of the third transistor is connected with the drain electrode of the fourth transistor; the source electrode of the third transistor is connected with the first signal input end; the source electrode of the fourth transistor is grounded; the drain electrode of the third common grid tube is connected with the source electrode of the fifth transistor; the drain electrode of the fifth transistor is respectively connected with a power supply and the first signal output end; the grid electrode of the third transistor, the grid electrode of the fourth transistor and the grid electrode of the fifth transistor are used for receiving a conduction control signal of the logic control unit so as to control whether the third amplifying unit is conducted or not.

With reference to the first aspect of the present application, in an optional implementation manner, the low noise amplifying circuit further includes a bias circuit, where the bias circuit is configured to output an operating voltage to the first stage amplifying unit, the second stage amplifying unit, and/or the third amplifying unit; the bias circuit is used for changing the working voltage under the control of the logic control unit so as to adjust the gain gear of the first gain mode and/or the second gain mode.

With reference to the first aspect of the present application, in an optional implementation manner, the low noise amplifying circuit further includes an attenuator, configured to adjust a gain gear of the low noise amplifying circuit under the control of the logic control unit; the attenuator is arranged between the second amplifying circuit and the first signal output end and/or between the first amplifying circuit and the first signal output end.

With reference to the first aspect of the present application, in an alternative embodiment, the attenuator includes at least two gain adjustment units, and the at least two gain adjustment units include different gain stages; the logic control unit is used for controlling the working state of the attenuator so as to adjust the gain gear of the low noise amplifier.

With reference to the first aspect of the present application, in an alternative implementation manner, the attenuator includes a switch assembly and at least one attenuation network, and the switch assembly is used for controlling an operating state of the at least one attenuation network under the control of the logic controller, so as to adjust a gain gear of the attenuator.

With reference to the first aspect of the present application, in an optional implementation manner, the at least one attenuation network includes: the T-shaped attenuation network comprises a first resistor, a second resistor and a third resistor, wherein the first resistor and the second resistor are connected in series, one end of the third resistor is connected between the first resistor and the second resistor, and the other end of the third resistor is connected with the radio frequency ground; or alternatively, the first and second heat exchangers may be,

the at least one attenuation network comprises: the pi-type attenuation network comprises a fourth resistor, a fifth resistor and a sixth resistor; the fifth resistor is connected between one end of the fourth resistor and one end of the sixth resistor, and the other end of the fourth resistor and the other end of the sixth resistor are connected with radio frequency ground.

With reference to the first aspect of the present application, in an optional implementation manner, the at least one attenuation network includes a first attenuation network and a second attenuation network;

The first attenuation network includes a thirty-first resistor, a thirty-second resistor, and a thirty-third resistor; the thirty-second resistor is connected between one end of the thirty-first resistor and one end of the thirty-third resistor, and the other end of the thirty-first resistor and the other end of the thirty-third resistor are grounded in a radio frequency manner;

the second attenuation network includes a thirty-fourth resistor, a thirty-fifth resistor, and a thirty-sixth resistor; the thirty-fifth resistor is connected between one end of the thirty-fourth resistor and one end of the thirty-sixth resistor, and the other end of the thirty-fourth resistor and the other end of the thirty-sixth resistor are grounded in a radio frequency manner; the thirty-second resistor and the thirty-fifth resistor are connected in series between the signal output terminal of the second-stage amplifying circuit and the first signal output terminal.

With reference to the first aspect of the present application, in an alternative embodiment, the switching assembly includes a thirty-first transistor, a thirty-third transistor, a thirty-fourth transistor, a thirty-fifth transistor, a thirty-sixth transistor, and a thirty-seventh transistor; the source electrode of the thirty-first transistor is connected with the signal output end of the second-stage amplifying circuit; the drain electrode of the thirty-first transistor is connected with the first signal output end; the source electrode of the thirty-second transistor is connected with the signal output end of the second-stage amplifying circuit; the drain electrode of the thirty-fifth transistor is connected with the source electrode of the thirty-fifth transistor; the drain electrode of the thirty-fifth transistor is connected with the first signal output end; the thirty-first resistor is connected between the source and the drain of the thirty-second transistor; the drain electrode of the thirty-third transistor is connected with the source electrode of the thirty-second transistor through the thirty-second resistor, and the source electrode of the thirty-third transistor is grounded in radio frequency; the drain electrode of the thirty-fourth transistor is connected with the drain electrode of the thirty-second transistor through the thirty-third resistor, and the source electrode of the thirty-fourth transistor is grounded in radio frequency; the thirty-fifth resistor is connected between the source and the drain of the thirty-fifth transistor; the drain electrode of the thirty-sixth transistor is connected with the source electrode of the thirty-fifth transistor through the thirty-fourth resistor, and the source electrode of the thirty-sixth transistor is grounded in radio frequency; the drain electrode of the thirty-seventh transistor is connected with the drain electrode of the thirty-fifth transistor through the thirty-sixth resistor, and the source electrode of the thirty-seventh transistor is grounded in radio frequency; the gate of the thirty-first transistor, the gate of the thirty-second transistor, the gate of the thirty-third transistor, the gate of the thirty-fourth transistor, the gate of the thirty-fifth transistor, the gate of the thirty-sixth transistor, and the gate of the thirty-seventh transistor are configured to receive a turn-on control signal of the logic control unit.

With reference to the first aspect of the present application, in an optional implementation manner, an input matching network is disposed between the first stage amplifying unit and the first signal input end, and the input matching network includes an input matching adjustment circuit for adjusting an input impedance of the first gain mode.

With reference to the first aspect of the present application, in an alternative implementation manner, the input matching adjustment circuit includes a sixth transistor and a third capacitor, a source electrode of the sixth transistor is connected to a gate electrode of the common source tube of the first stage amplifying unit, a drain electrode of the sixth transistor is connected to a source electrode of the common source tube of the first stage amplifying unit through the third capacitor, and a gate electrode of the sixth transistor is used for receiving a conduction control signal of the logic control unit.

In a second aspect, an embodiment of the present application provides a radio frequency front end module, including the low noise amplifier according to any one of the preceding aspects.

The low-noise amplifier and the radio frequency front end module provided by the embodiment of the application amplify the signal in a high-gain gear (a first gain mode) by adopting the first amplifying circuit comprising the two-stage amplifying unit, amplify the signal in a low-gain gear (a second gain) by adopting the second amplifying circuit comprising the one-stage amplifying unit, and ensure the gain coverage of the low-noise amplifier and improve the linearity of the low-gain gear by utilizing the characteristic that the linearity of the one-stage amplifying circuit is better. Thus, the defect that the traditional low-noise amplifier cannot achieve both the gain range and the linearity is overcome. By adopting the attenuator and the bias circuit, the adjustable of a plurality of gain gears is realized, and the gain adjusting range of the low noise amplifier is enlarged.

Additional aspects and advantages of the application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the application.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:

FIG. 1 is a schematic diagram of a low noise amplifier according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a low noise amplifier according to an embodiment of the application;

FIG. 3 is a schematic diagram III of a low noise amplifier according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a first bias circuit according to an embodiment of the application;

FIG. 5 is a schematic diagram of a second bias circuit according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a third bias circuit according to an embodiment of the present application;

FIG. 7 is a schematic diagram of an attenuator according to an embodiment of the present application;

FIG. 8a is a schematic diagram of a second attenuator according to an embodiment of the present application;

FIG. 8b is a schematic diagram of an attenuator according to an embodiment of the present application;

FIG. 8c is a schematic diagram of an attenuator according to an embodiment of the present application;

Fig. 9 is a schematic diagram of an attenuator according to an embodiment of the present application.

Detailed Description

In order to make the technical solution and the beneficial effects of the present application more obvious and understandable, the technical solution in the embodiments of the present application will be clearly and completely described by way of example only, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that the terms first, second, etc. as used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. For example, a first resistance may be referred to as a second resistance, and similarly, a second resistance may be referred to as a first resistance, without departing from the scope of the application. Both the first resistor and the second resistor are resistors, but they are not the same resistor. When "first" is described, it does not necessarily mean that "second" is present; and when "second" is discussed, it does not necessarily indicate that the application necessarily resides in a first element, component, region, layer or section. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The meaning of "a plurality of" is two or more, unless specifically defined otherwise. It will be further understood that the terms "comprises" and "comprising," when used in this specification, specify the presence of stated features, but do not preclude the presence or addition of one or more other features. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

It is to be understood that in the context of the present application, "connected" means that the connected end and the connected end have electrical signals or data transferred therebetween, and may be understood as "electrically connected", "communicatively connected", etc. In the context of the present application, "a is directly connected to B" means that no other components than wires are included between a and B.

An embodiment of the present application provides a low noise amplifier, referring to fig. 1, including: the first amplifying circuit 10 and the second amplifying circuit 20 are connected in parallel between the first signal input terminal 01, the first signal output terminal 02, the logic control unit 30, and the first signal input terminal 01 and the first signal output terminal 02. The first signal input terminal 01 is used for inputting signals. The first signal output terminal 02 is for outputting a signal. The input signal may be a radio frequency signal. Optionally, the first signal output 02 is connected to a load.

The first amplifying circuit 10 is configured to amplify a signal in a first gain mode. The first amplification circuit 10 includes a two-stage amplification unit, a first-stage amplification unit 11 and a second-stage amplification unit 12 for sequentially performing two-stage amplification on signals. By adopting the two-stage amplifying circuit, the high-gain amplification of the input signal is realized, and the noise adjustable space is improved.

The second amplifying circuit 20 is configured to amplify the signal in a second gain mode. The second amplifying circuit 20 includes a first amplifying unit and a third amplifying unit for performing first-stage amplification on the signal. The gain of the second gain mode is less than the gain of the first gain mode.

The logic control unit 30 is configured to control the first amplifying circuit 10 or the second amplifying circuit 20 to be turned on, so as to select the first gain mode or the second gain mode to amplify the signal. When the signal needs to be amplified in the first gain mode (high gain mode), the logic control unit 30 controls the first amplifying circuit 10 to be turned on; when the signal needs to be amplified in the second gain mode (low gain mode), the logic control unit 30 controls the second amplifying circuit 20 to be turned on.

The working procedure of the low noise amplifier of this embodiment is as follows: the signal is amplified in a first gain mode and a second gain mode using a first amplification circuit 10 and a second amplification circuit 20, respectively. When the signal needs to be amplified in the first gain mode, the logic control unit 30 controls the first amplifying circuit 10 to be conducted, and the second amplifying circuit 20 to be non-conducted; when the signal needs to be amplified in the second gain mode, the logic control unit 30 controls the second amplifying circuit 20 to be conductive, and the first amplifying circuit 10 to be non-conductive. The first amplification circuit 10 includes two-stage amplification units, and sequentially amplifies signals in two stages, and is capable of amplifying signals in a high gain mode. The second amplifying circuit 20 adopts a first-stage amplifying unit to amplify the signal, and can amplify the signal in a low-gain mode, and simultaneously improve the linearity of a low-gain stage.

High gain amplification of a signal is achieved by amplifying the signal in a high gain mode (first gain mode) with a first amplifying circuit including a two-stage amplifying unit; the second amplifying circuit comprising the first amplifying unit is used for amplifying the signal in a low gain mode (second gain mode), and the linearity of the first amplifying circuit is better, so that the gain coverage range of the low noise amplifier is enlarged, and the linearity of the low gain mode is improved. The gain of the low-noise amplifier reaches more than 21dB under the frequency of 3.3G-4.2 GHz (the post-simulation result), and the input matching and the output matching are good. At 3.8GHz frequency, the gain can reach 23.5dB. The 1dB compression point reaches-23 dBm. Noise is within 1.4dB, and the matching is good.

The transistor in the embodiment of the present application is described by taking an insulated gate field effect transistor (MOSFET, simply referred to as MOS transistor) as an example, but the embodiment of the present application is not limited thereto, and other types of transistors, such as a junction transistor (BJT) or a Junction Field Effect Transistor (JFET), may be used, which is not limited thereto.

Referring to fig. 2, in an alternative embodiment, the first stage amplifying unit 11 includes a first common source transistor M11, a first common gate transistor M12, and a first transistor M13. The second-stage amplifying unit 12 includes a second common-source transistor M21, a second common-gate transistor M22, and a second transistor M23. M13 and M23 are used for receiving the on control signal of the logic control unit 30 to control whether the first stage amplifying unit 11 and the second stage amplifying unit 12 are on or off, respectively.

In an alternative embodiment, the drain of M11 is connected to the source of M12, the source of M11 is connected to the drain of M13, and the gate of M11 is connected to the first signal input terminal 01 to receive the input signal. The source of M13 is grounded. The drain of M12 is connected to power supply VDD. The drain electrode of M21 is connected with the source electrode of M22, and the source electrode of M21 is connected with the drain electrode of M23. The drain of M21 is connected to the first signal output 02. The source of M23 is grounded. The drain of M22 is connected to power supply VDD. The gate of M21 is connected to the drain of M12. The gate of M13 and the gate of M23 are used for receiving the on control signal va_buf of the logic control unit 30. Optionally, the source of M13 is grounded through a first inductor L51. When va_buf is at high level and higher than the on voltage of M13 and M23, M13 and M23 are turned on, and the first stage amplifying unit 11 and the second stage amplifying unit 12 are turned on to start operation. When va_buf is at a low level, lower than the on voltage of M13 and M23, or when the on control signal is not received, M13 and M23 are not turned on, and the first stage amplifying unit 11 and the second stage amplifying unit 12 are not turned on and do not operate. The gates of M11, M12, M21, and M22 are for receiving bias voltages VG1D, VG1U, VG D and VG2U, respectively.

In an alternative embodiment, the second amplifying circuit 20 includes a third amplifying unit 21 including a third common-source transistor M31, a third common-gate transistor M32, a third transistor M33, a fourth transistor M34, and a fifth transistor M35. The drain electrode of M31 is connected with the source electrode of M32, the grid electrode of M31 is connected with the drain electrode of M33, and the source electrode of M33 is connected with the drain electrode of M34; the source electrode of M33 is connected with the first signal input end 01; the source electrode of M34 is grounded; the drain electrode of M32 is connected with the source electrode of M35; the drain electrode of the M35 is respectively connected with the power supply VDD and the first signal output end 02; the grid of M33, the grid of M34 and the grid of M35 are used for receiving the conduction control signals of the logic control unit so as to control the third amplifying unit to be conducted or not. Optionally, the source of M23 is grounded through a first inductor L51. Optionally, the drain of M33 is connected to the gate of M31 through a fifth capacitor C31.

When the on control signals va_buf_inv received by the gates of M33, M34 and M35 are high, which is higher than the on voltages of M33, M34 and M35, M33, M34 and M35 are turned on, and the third stage amplifying unit 13 is turned on to start operation. When the gates of M33, M34 and M35 receive the on control signal va_buf_inv at a low level, lower than the on voltage of M33, M34 and M35, or when the on control signal va_buf_inv is not received, M33, M34 and M35 are not turned on, and the third amplifying unit 21 is not turned on and is in a non-operating state.

Alternatively, the level of va_buf is inverted from that of va_buf_inv, when va_buf is high, va_buf_inv is low, and when va_buf is low, va_buf_inv is high. In this way, selective conduction of the first amplification circuit 10 and the second amplification circuit 20 is achieved. Alternatively, the power supply voltage VDD is 1 to 3V. Alternatively, the supply voltage VDD is about 1.2V.

Because the second amplifying circuit 20 adopts the primary amplifying structure, the linearity of the primary amplifying structure is much better than that of the secondary amplifying circuit, and especially when the bias current is low, the gain amplification condition of the secondary amplifying circuit can occur. The primary amplifying structure ensures the gain value of the high gain mode and improves the linearity of the low gain mode.

In an alternative embodiment, referring to fig. 3, the low noise amplifier further includes a bias circuit for outputting an operating voltage to the first stage amplification unit 11, the second stage amplification unit 12, and/or the third amplification unit 21. Optionally, the bias circuits include a first bias circuit 15, a second bias circuit 16, and a third bias circuit 22 for outputting the operating voltages to the first-stage amplifying unit 11, the second-stage amplifying unit 12, and the third amplifying unit 21, respectively. Referring to fig. 4, the first bias circuit 15 includes a reference current input terminal Iref1, an operating voltage output terminal, a voltage converting unit, a tenth transistor M151, an eleventh transistor M152, a twelfth transistor M153, and a thirteenth transistor M154. The voltage conversion unit is used for converting the current received through the reference current input end Iref1 into an operating voltage and outputting the operating voltage to M11 and M12. It will be appreciated that the number of operating voltage outputs matches the number of common source and common gate. Taking fig. 2 as an example, the first stage amplifying unit 11 includes a first common source tube M11 and a first common gate tube M12, and the voltage converting unit outputs a first operating voltage VG1D and a second operating voltage VG1U to the gates of the first common source tube M11 and the second common gate tube M12, respectively.

Optionally, the MOS transistors M151 and M152 are connected by using a diode connection manner, so as to form a first MOS diode M151 and a second MOS diode M152. The MOS diode is used for releasing static electricity and improving the quality and reliability of the circuit. The drain and the source of the MOS transistor M153 are connected to form a first MOS capacitor M153. The drain and the source of the MOS transistor M154 are connected to form a second MOS capacitor M154. The MOS capacitor acts as a filter. The voltage conversion unit comprises at least one resistor, and the input current forms voltage drop after flowing through the voltage conversion unit, so that the current is converted into working voltage.

As shown in fig. 4, the voltage conversion unit of the first bias circuit 15 includes a first resistor R151, a second resistor R152, a third resistor R153, a fourth resistor R154, and a fifth resistor R155. The drain and gate of M151 are connected to the reference current input Iref 1. The source of M151 is connected to the drain and gate of M152. The gate of M151 is connected to the output terminal of the second operating voltage VG1U through R151 and R152 in sequence. The source of M152 is connected to analog ground GND1. The gate of M152 is connected to the output of the first operating voltage VG1D through R153, R154 and R155 in sequence. The gate of M153 is connected between R154 and R155. The gate of M154 is connected to the output terminal of the second operating voltage VG 1U. The drains and sources of M153 and M154 are connected to analog ground GND1. Alternatively, R151 and R152 are replaced with a resistor. R153 and R154 are replaced by a resistor.

Alternatively, the first bias circuit 15 and the second bias circuit 16 are identical in structure. Referring to fig. 5, the second bias circuit 16 includes a reference current input terminal Iref2, an operating voltage output terminal, a voltage converting unit, a fifteenth transistor M161, a sixteenth transistor M162, a seventeenth transistor M163, and an eighteenth transistor M164. The voltage conversion unit is used for converting the current received through the reference current input end Iref2 into an operating voltage and outputting the operating voltage to M21 and M22. It will be appreciated that the number of operating voltage outputs matches the number of common source and common gate tubes of the second stage amplifying unit 12. Taking fig. 2 as an example, the second-stage amplifying unit 12 includes a second common-source tube M21 and a second common-gate tube M22, and the second bias circuit 16 outputs a third operating voltage VG2D and a fourth operating voltage VG2U to the gates of the M21 and the M22, respectively.

Optionally, the voltage conversion unit of the second bias circuit 16 includes a sixth resistor R161, a seventh resistor R162, an eighth resistor R163, a ninth resistor R164, and a tenth resistor R165. The connection relationship is the same as in the first bias circuit 15. Alternatively, R161 and R162 are replaced with a resistor. R163 and R164 are replaced with a resistor.

Optionally, the second bias circuit 16 and the first bias circuit 15 are the same bias circuit, the output end of the first operating voltage VG1D is the same as the output end of the third operating voltage VG2D, and the output end of the second operating voltage VG1U is the same as the output end of the fourth operating voltage VG 2U. Optionally, reference current inputs Iref1 and Iref2 are connected to logic control unit 30.

Referring to fig. 6, the third bias circuit 22 includes a reference current input terminal Iref3, an operating voltage output terminal, a voltage converting unit, a nineteenth transistor M221, a twentieth transistor M222, a twenty first transistor M223, and a twenty second transistor M224. The voltage conversion unit of the third bias circuit 22 is configured to convert the current received through the reference current input terminal Iref3 into an operating voltage, and output the operating voltage to the common source and the common gate of the third amplifying unit 21. Optionally, the reference current input Iref3 is connected to the logic control unit 30. The current circuit is controlled by the logic control unit 30 to provide a reference current to the third bias circuit 22. It will be appreciated that the number of operating voltage outputs matches the number of common source and common gate. Taking fig. 2 as an example, the third amplifying unit 21 includes a third common-source tube M31 and a third common-gate tube M32, and the voltage converting unit outputs the fifth operating voltage VG3D and the sixth operating voltage VG3U to the gates of the M31 and the M32, respectively.

Optionally, the MOS transistors M221 and M222 are connected by a diode to form a fifth MOS diode M221 and a sixth MOS diode M222. The MOS diode is used for releasing static electricity and improving the quality and reliability of the circuit. The drain and the source of the MOS transistor M223 are connected to form a fifth MOS capacitor M223. The drain and the source of the MOS transistor M224 are connected to form a sixth MOS capacitor M224. The MOS capacitor acts as a filter. The voltage conversion unit comprises at least one resistor, and the input current forms voltage drop after flowing through the voltage conversion unit, so that the current is converted into working voltage.

As shown in fig. 6, the voltage conversion unit of the third bias circuit 22 includes an eleventh resistor R221, a twelfth resistor R222, a thirteenth resistor R223, and a fourteenth resistor R224. The drain and gate of M221 are connected to the reference current input Iref 3. The source of M221 is connected to the drain and gate of M222. The gate of M221 is connected to the sixth operating voltage VG3U output through R221 and R222 in turn. The source of M222 is connected to analog ground GND1. The gate of M222 is connected to the fifth operating voltage VG3U output through R223 and R224 in turn. The gate of M223 is connected to the output of the fifth operating voltage VG 3U. The gate of M224 is connected to the output of the sixth operating voltage VG 3U. The drains and sources of M223 and M224 are connected to analog ground GND1. Alternatively, R221 and R222 are replaced with a resistor. R223 and R224 are replaced with a resistor.

The magnitudes of the reference currents Iref1, iref2, iref3 provided by the current circuits are controlled by the logic control unit 30, thereby changing the operating voltages outputted by the first, second, and third bias circuits to adjust the mode/gear of the low noise amplifier. Each gain stage is adjustable. Alternatively, the logic control unit 30 employs a MIPI digital controller. The current circuit is controlled by three-bit control words of 3 registers, 3 paths of 8 current values can be provided, the reference current of the bias circuit is further changed, and the working voltages provided by the bias circuit to the first amplifying circuit 10 and the second amplifying circuit 20 are changed, so that adjustment of different gain values is realized. Alternatively, the reference current is 10-20 mA, for example 15.5mA. Alternatively, the reference current of the first bias circuit 11 is 10mA, and the reference current of the second bias circuit 12 is 6mA, thereby realizing high gain amplification and improving noise adjustable space. The three-way bias circuit is also used for respectively improving the grid voltages of the three amplifying units.

Referring to fig. 2 and 3, in an alternative embodiment, the low noise amplifier further comprises an attenuator 40 disposed between the second amplifying circuit 20 and the first signal output 02 and/or between the first amplifying circuit 10 and the first signal output 02 for adjusting the gain stage of the low noise amplifier under the control of the logic control unit 30. The logic control unit is also used to control the operating state of the attenuator 40 to adjust the gain stage of the low noise amplifier. The adjustment of the gain gear may be performed for the first gain mode and the second gain mode, respectively. The attenuator 40 in fig. 2 is arranged between the signal output 222 of the first amplifying circuit 10 and the first signal output 02, and between the signal output of the second amplifying circuit 20 and the first signal output 02, and is capable of adjusting the gain steps for the first gain mode and the second gain mode. The signal output terminal of the second amplifying circuit 20 may be directly connected to the first signal output terminal 02, i.e. the drain of the M35 is directly connected to the first signal output terminal 02, and the attenuator 40 may only perform the adjustment of the gain stage for the first gain mode.

Optionally, the attenuator 40 comprises a passive attenuator. The attenuator 40 comprises at least two gain adjustment units, including different gain stages. The impedance values of the different gain adjustment units are different. By controlling the working states of the different gain adjusting units, different degrees of attenuation of the signal in the first gain mode or the second gain mode are realized. If the first gain adjusting unit 41 in the attenuator 40 is in an operating state, the first gain adjusting unit 41 is used for attenuating the signal, and if the second gain adjusting unit 42 is in an operating state, the second gain adjusting unit 42 is used for attenuating the signal, so that the gain of the low noise amplifier is adjustable.

Alternatively, the number of gain adjustment units may be adjusted as desired. Fig. 7 shows an example including four gain adjustment units, including a first gain adjustment unit 41, a second gain adjustment unit 42, a third gain adjustment unit 43, and a fourth gain adjustment unit 44, which receive control signals of the logic control unit 30 through control signals S1, S2, S3, and S4 input terminals, respectively, to control whether the first gain adjustment unit 41, the second gain adjustment unit 42, the third gain adjustment unit 43, and the fourth gain adjustment unit 44 are in an operating state. The gains of the first gain adjustment unit 41, the second gain adjustment unit 42, the third gain adjustment unit 43, and the fourth gain adjustment unit 44 are different. The signal input 401 of the attenuator 40 is connected to the signal output of the first amplifying circuit 10 and/or to the signal output of the second amplifying circuit 20. The signal output 402 is connected to the first signal output 02. Optionally, the signal input 401 of the attenuator 40 is connected to the signal input of the output matching network 60.

The working procedure of the low noise amplifier of this embodiment is as follows: the input signal is amplified in a first gain mode (high gain) by a two-stage amplification circuit of the first amplification circuit 10, and amplified in a second gain mode (low gain) by a one-stage amplification circuit of the second amplification circuit 20. The signal passing through the first amplification circuit 10 or the second amplification circuit 20 is attenuated by the attenuator 40. The attenuator 40 includes at least two different gain units, each corresponding to a different gain gear. When the gain stage of the low noise amplifier needs to be adjusted, the logic control unit 30 controls the working state of the attenuator 40, and selects different gain stages to perform the first gain mode and/or the second gain mode gain adjustment on the signal. The impedance of the different gain adjustment units is different, so that the degree of attenuation of the signal by the different gain adjustment units is also different. The logic control unit 30 attenuates the signal to different extents by controlling the operating states of the different gain adjustment units to achieve adjustment of different gain modes or gain steps. For example, when the first gain adjustment unit 41 is turned on, the signal is subjected to the first gain stage processing by the first gain unit adjustment unit 41; when the second gain unit adjusting unit 42 is turned on, the signal implements a second gain stage process through the second gain unit adjusting unit 42; when the third gain adjusting unit 43 is turned on, the signal realizes a third gain stage process through the third gain adjusting unit 43; when the fourth gain adjustment unit 44 is turned on, the signal is subjected to fourth gain stage processing by the fourth gain adjustment unit 44. Thus, the low-noise amplifier of the embodiment realizes the adjustment of a plurality of gain gears while improving the gain coverage range, and greatly improves the adjustment range of the gain gears.

Referring to fig. 8 and 9, in an alternative embodiment, the attenuator 40 includes a switching assembly and at least one attenuation network, the switching assembly being configured to control the operating state of the attenuation network under the control of the logic control unit 30 to select the gain gear of the attenuator, thereby achieving adjustment of different gain gears. Optionally, the attenuation network comprises a pi-type attenuation network or a T-type attenuation network.

Fig. 8a and 8b show a possible embodiment of an attenuator 40 comprising a switching assembly and an attenuation network having two gain stages, the selection of the two gain modes being achieved by controlling whether the attenuation network is operated by controlling the switching assembly on or off. Referring first to fig. 8a, the switching assembly includes a thirty-first transistor M41. M41 constitutes a first gain adjustment unit. The attenuation network adopts a T-shaped attenuation network and comprises a thirty-first resistor R41, a thirty-second resistor R42 and a thirty-third resistor R43. R41 and R42 are connected in series and then connected between the signal input terminal 401 and the signal output terminal 402 of the attenuator 40. One end of R43 is connected between R41 and R42, and the other end of R43 is connected with radio frequency ground GNDRFX. The source of M41 is connected to the signal input 401 of attenuator 40 and the drain of M41 is connected to the signal output 402 of attenuator 40. R41, R42, and R43 constitute a second gain adjustment unit. The gate of M41 receives the on control signal of the logic control unit 30 via the control signal S1 input.

Referring to fig. 8b, the damping network employs a pi-type damping network including a thirty-fourth resistor R44, a thirty-fifth resistor R45, and a thirty-sixth resistor R46. R45 is connected between one end of R44 and one end of R46. The other end of R44 and the other end of R44 are connected to the radio frequency ground GNDRFX. The source of M41 is connected to the signal input 401 of attenuator 40 and the drain of M41 is connected to the signal output 402 of attenuator 40. R44, R45, and R46 constitute a second gain adjustment unit. The gate of M41 receives the on control signal of the logic control unit 30 via the control signal S1 input.

When the level of the turn-on control signal received by M41 is greater than the turn-on voltage of M41, M41 turns on, and a signal flows from the signal input terminal 401 through the source and drain of M41 and is output from the signal output terminal 402. At this time, the signal is not attenuated, and the gain is zero for the first gain stage of the attenuator 40. When the level of the on control signal received by M41 is smaller than the on voltage of M41, M41 is turned off, and the signal flows from the signal input terminal 401, is attenuated via the T-type attenuation network formed by R41, R42, and R43, and/or the pi-type attenuation network formed by R44, R45, and sixth resistor R46, and is output from the signal output terminal 402. At this time, the second gain stage of the attenuator 40, the signal is attenuated. The gain value of the second gain stage may be set by the resistance values of R41, R42 and R43.

In another possible embodiment, the first switching component includes a first transistor M41, a second transistor M42 and a third transistor M43, respectively connected in parallel to the three resistors of the attenuation network, for controlling the operating state of the attenuation network. Taking the T-type attenuator network of fig. 8a as an example, referring to fig. 8c, the source and the drain of M41 are respectively connected to two ends of R41, the source and the drain of M42 are respectively connected to two ends of R42, and the source and the drain of M43 are respectively connected to two ends of R43. The gates of M41, M42, and M43 are for receiving control signals S1, S2, and S3, respectively. When the S1, S2 and S3 levels are high levels and are higher than the conduction voltages of M41, M42 and M43, the attenuation network is not in operation, and the signal is not attenuated at the moment and is the first gain gear of the attenuator 40; when the levels S1, S2 and S3 are low and lower than the on-voltages of M41, M42 and M43, the attenuation network operates to attenuate the signal, which is the second gain stage of the attenuator 40. For the case where the attenuation network is pi-type, the three transistors are connected in the same manner as in fig. 9 below.

Fig. 9 shows a possible embodiment of an attenuator comprising two attenuation networks, comprising a first attenuation network and a second attenuation network, with four gain steps. The first attenuation network includes a thirty-first resistor R41, a thirty-second resistor R42, and a thirty-third resistor R43. R42 is connected between one end of R41 and one end of R43. The other end of R41 and the other end of R43 are connected to the radio frequency ground GNDRFX. The second attenuation network includes a thirty-fourth resistor R44, a thirty-fifth resistor R45, and a thirty-sixth resistor R46. R45 is connected between one end of R44 and one end of R46. The other end of R44 and the other end of R46 are connected to the radio frequency ground GNDRFX. R42 and R45 are connected in series between the signal input 401 and the signal output 402 of the attenuator 40.

Fig. 9 shows that both the first and second attenuation networks employ pi-type attenuation networks. Alternatively, the first attenuation network and the second attenuation network may both employ T-type attenuation networks; or the first attenuation network adopts a T-type attenuation network, and the second attenuation network adopts a pi-type attenuation network; or the first attenuation network adopts a pi-type attenuation network, and the second attenuation network adopts a T-type attenuation network. Optionally, the number of attenuation networks is more than three, for example, a third attenuation network and/or a fourth attenuation network are further included, and the attenuation networks are selected according to needs. The topology of the attenuation network can be T-type or pi-type.

The switching components include a thirty-first transistor M41, a thirty-second transistor M42, a thirty-third transistor M43, a thirty-fourth transistor M44, a thirty-fifth transistor M45, a thirty-sixth transistor M46, and a thirty-seventh transistor M47. The source electrode of the M41 is connected with the signal output end of the second-stage amplifying circuit through the signal input end 401; the drain electrode of the M41 is connected with the first signal output end 02 through the signal output end 402; the source electrode of M42 is connected with the signal output end of the second-stage amplifying circuit through the signal input end 401; the drain electrode of M42 is connected with the source electrode of M45; the drain electrode of M45 is connected with the first signal output end 02; r41 is connected between the source and drain of M42. The drain electrode of M43 is connected with the source electrode of M42 through R42, and the source electrode of M43 is grounded with the radio frequency GNDRFX. The drain electrode of M44 is connected with the drain electrode of M42 through R43, and the source electrode of M44 is grounded with the radio frequency GNDRFX. R45 is connected between the source and drain of M45. The drain electrode of M46 is connected with the source electrode of M45 through R44, and the source electrode of M46 is grounded with the radio frequency GNDRFX; the drain electrode of M47 is connected with the drain electrode of M45 through R46, and the source electrode of M47 is grounded with the radio frequency GNDRFX. The gate of M41, the gate of M42, the gate of M43, the gate of M44, the gate of M45, the gate of M46, and the gate of M47 are respectively used for receiving the on control signal of the logic control unit 30.

The gate of M41 receives the on control signal S1 of the logic control unit 30. The gate of M42 receives the on control signal s2_inv of the logic control unit 30. The gate of M43 and the gate of M44 receive the on control signal S2 of the logic control unit 30. The gate of M45 receives the on control signal s3_inv of the logic control unit 30. The gate of M46 and the gate of M47 receive the on control signal S3 of the logic control unit 30. Alternatively, s2_inv is inverted to S2, and when s2_inv is high, S2 is low; when s2_inv is low, S2 is high. S3_inv is opposite to S3, and when s3_inv is high, S3 is low; when s3_inv is low, S3 is high.

M41 constitutes a first gain adjustment unit 41. M42, M43, M44, R41, R42, R43 constitute the second gain adjustment unit 42. M45, M46, M47, R44, R45, R46 constitute the third gain adjustment unit 43. M42, M43, M44, M45, M46, M47, R41, R42, R43, R44, R45, R46 constitute a fourth gain adjustment unit 44.

Optionally, the gate of M41 is connected to the input terminal of the control signal S1 through a fifteenth resistor R411. The gate of M42 is connected to the input terminal of the control signal s2_inv through the sixteenth resistor R421. The gate of M43 is connected to the input of control signal S2 through seventeenth resistor R424. The gate of M44 is connected to the input of control signal S2 through eighteenth resistor R426. The gate of M45 is connected to the control signal s3_inv input through a nineteenth resistor R431. The gate of M46 is connected to the input of control signal S3 through a twentieth resistor R434. The gate of M47 is connected to the input of control signal S3 through a twenty-first resistor R435. R411, R421, R424, R426, R431, R434 and R435 can prevent M41, M42, M43, M44, M45, M46 and M47 from burning out due to excessive charge and discharge current on the one hand; on the other hand, the charge and discharge speed of the transistor can be adjusted. The equivalent time constant of the gate resistance determines the switching time of the transistor switch. As the gate resistance increases, the transistor switch switching speed slows down. And the charge and discharge speed is increased by selecting a proper grid resistance value.

The attenuator 40 operates as follows: in the first gain gear, S1 is at a high level, which is higher than the on voltage of M41, M41 is turned on, the first gain adjusting unit 41 is turned on, a signal flows in from the signal input terminal 401, and is output from the signal output terminal 402 after passing through the source and drain of M41, and the attenuator 40 does not attenuate the signal, so that the first gain gear processing of the signal is realized.

In the second gain gear, S1 is low, S2 is high, s2_inv is low, and S3 is low, s3_inv is high, the first gain adjustment unit 41 is not turned on, M42, M43, M44, and M45 are turned on, the second gain adjustment unit 42 is in an operating state, and the third gain adjustment unit 43 is not operated. After the signal is transmitted from the signal input terminal 401 through the source and drain of M42, the signal is output from the signal output terminal 402 through the attenuation network formed by R41, R42, and R43. The second gain stage processing of the signal is achieved by attenuation through the second gain adjustment unit 42. Alternatively, the gain of the second gain stage is, for example, -3dB.

In the third gain gear, S1 is low, S2 is low, s2_inv is high, and S3 is high, s3_inv is low, the first gain adjustment unit 41 is not turned on, M42, M45, M46, and M47 are turned on, the third gain adjustment unit 43 is in an operating state, and the second gain adjustment unit 42 is not operated. After the signal is transmitted from the signal input terminal 401 through the source and drain of M42, the signal is output from the signal output terminal 402 through the attenuation network formed by R44, R45, and R46. The third gain stage processing of the signal is achieved by attenuation by the third gain adjustment unit 43. The gain of the third gain stage is different from the gain of the second gain stage. Optionally, the gain of the third gain stage is, for example, -6dB.

In the fourth gain gear, S1 is low, S2 is high, S3 is high, s2_inv and s3_inv are low, and the second gain adjustment unit 42 and the third gain adjustment unit 43 are in operation. The signal is outputted from the signal input terminal 401 through the attenuation network formed by R41, R42, and R43, and the attenuation network formed by R44, R45, and R46 in this order, from the signal output terminal 402. The fourth gain stage processing of the signal is achieved by attenuation by the second gain adjustment unit 42 and the third gain adjustment unit 43. Optionally, the gain of the fourth gain stage is, for example, -9dB.

As described above, by implementing adjustment of a plurality of gain stages by using the attenuator 40, the gain adjustable stage and adjustment range are enlarged while high gain amplification is implemented. The gain gear is directly adjusted by the control logic control unit 30 without changing the reference current of the bias circuit, and the attenuator 40 is simply and directly controlled to adjust the gain gear, so that the adjustment of the gain gear is simplified, and the flexibility of the adjustment of the gain gear is improved. Gain adjustment of-3 dB to-9 dB, such as-3 dB, -6dB, and-9 dB gain attenuation, can be achieved by control of the attenuator 40. Optionally, the gain values of the respective gain adjustment units or the different gain steps are set by setting the impedance of the attenuation network of the respective gain adjustment units. Optionally, the size of the switch assembly is adjusted to reduce the impact of the attenuator 40 on the performance of the first stage amplification unit 11 and the second stage amplification unit 12.

Possible adjustment modes of the gain gear according to the embodiment of the application include: the logic control unit 30 controls the first amplification circuit 10 to be in an operating state, and the second amplification circuit 20 to be in a non-operating state, at which time the amplification in the first gain mode (high gain mode) is performed by the first amplification circuit 10. The logic control unit 30 controls the second amplifying circuit 20 to be in an operating state, and the first amplifying circuit 10 to be in a non-operating state, at which time the second gain mode (low gain mode) is amplified by the second amplifying circuit 20.

In the first gain mode and the second gain mode, the logic control unit 30 adjusts bias voltages output to the first-stage amplifying unit 11, the second-stage amplifying unit 12, and the third amplifying unit 21 by adjusting different reference currents, thereby achieving adjustment of different gain stages. The three-bit control word of each of the two registers is adopted to control the current source circuit, 3 paths of 8 current values can be output, the reference current of the bias circuit is further changed, and the working voltage provided by the bias circuit to the first amplifying circuit 10 and the second amplifying circuit 20 is changed, so that adjustment of different gain gears is realized.

In another possible way, the logic control unit 30 outputs a predetermined bias voltage by setting the reference current first, and then adjusts the different gain stages by controlling the operation states of the different gain adjustment units of the attenuator 40. In another possible way, the logic control unit 30 effects the adjustment of the different gains by adjusting the bias current, e.g. reducing the bias current, in combination with controlling the operating states of the different gain adjustment units of the attenuator 40. Alternatively, the first three gain stages may be directly controlled by the attenuator 40 to achieve a gain decrease, and the later gain stages may be adjusted by reducing the bias current value in conjunction with the attenuator 40.

Alternatively, the reference current is 10-20 mA, for example 15.5mA. Optionally, the reference current of the first bias circuit is 10mA, the reference current of the second bias circuit is 6mA, high gain is achieved, and noise adjustable space is improved. Alternatively, R155 and R165 have a resistance of 10KΩ to 30KΩ, for example, 20KΩ.

Optionally, the lowest gear gain of the low noise amplifier of the embodiment of the application reaches-7 dB, the input and output are well matched, the power consumption is almost not consumed, the 1dB compression point reaches-1 dBm, and the input third-order intermodulation intercept point (IIP 3) reaches 4.4dBm.

Referring to fig. 2 and 3, in an alternative embodiment, an input matching network 50 is provided between the first stage amplification circuit 10 and the first signal input 01. The input matching network 24 includes an input matching adjustment circuit for effectively adjusting the input matching of the low gain gear. Alternatively, the low gain gear is other gain gears than the highest gain gear. The input matching adjustment circuit includes a sixth transistor M51 and a third capacitor C51 connected in series. The source of M51 is connected to the gate of M11, the drain of M51 is connected to the source of M11 through C51, and the gate of M51 is used for receiving the on control signal of logic control unit 30.

A logic control bit is introduced into the input matching network 50, M51 is conducted under the control of the logic control unit 30, C51 is connected between the grid electrode and the source electrode of M11, and the capacitance between the grid electrode and the source electrode of M11 is increased, so that the input matching of the middle gain gear of the low-noise amplifier can be effectively regulated. Optionally, the input matching adjustment circuit is controlled to perform input matching adjustment in other lower gain gear than the highest gain gear.

The input matching network 50 further comprises a second inductance L52 and a fourth capacitance C53. L52 and C53 are serially connected in turn between the first signal input 01 and the gate of M11. Optionally, the second inductor L22 is placed off-chip (die) for noise reduction. Alternatively, L22 employs a patch inductance. Alternatively, a higher Q inductance, e.g., 3nH, is used.

Referring to fig. 2 and 3, in an alternative embodiment, an output matching network 60 is provided between the second stage amplifying unit 12 and the first signal output 02, and includes a fourth inductance L61, a fifth inductance L62, and a sixth capacitance C61. L61 is connected between the drain of M12 and voltage VDD. L62 is connected between M22 and voltage VDD. C61 is connected between the signal output 222 of the second-stage amplifying unit 12 and the first signal output 02. Or C61 is connected between the signal output 222 of the second stage amplification unit 12 and the attenuator 40. C61 is also connected between the drain of M35 and the first signal output 02. Or C61 is also connected between the drain of M35 and attenuator 40.

Referring to fig. 2 and 3, in an alternative embodiment, an inter-stage matching circuit 13 is provided between the first-stage amplification unit 11 and the second-stage amplification unit 12 for achieving impedance matching between the first-stage amplification unit 11 and the second-stage amplification unit 12. The inter-stage matching circuit 13 includes a first capacitor C11 disposed between the drain of M12 and the gate of M21. A compensation circuit 14 is provided between the inter-stage matching circuit 13 and the signal output terminal 222 of the second-stage amplifying unit 12 for adjusting the output matching of the low-noise amplifying circuit, and the high-frequency gain. Optionally, the compensation circuit 14 comprises a miller compensation unit comprising a second capacitance C12. Optionally, the miller compensation unit further comprises a twenty-second resistor R11, which is connected in series with the second capacitor C12.

In a second aspect, an embodiment of the present application provides a radio frequency front end module, including the low noise amplifier according to any one of the preceding aspects. Optionally, the rf front-end FEM chip may further include a Power Amplifier (PA), a single pole double throw Switch (SPDT). Optionally, the rf front-end module chip is implemented by adopting a Global Foundry SOI process.

The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.

Claims

1. A low noise amplifier, comprising: the first signal input end, the first signal output end, the logic control unit and the first amplifying circuit and the second amplifying circuit are connected in parallel between the first signal input end and the first signal output end; wherein,

The first signal input end is used for receiving signals;

the first signal output end is used for outputting a signal;

2. The low noise amplifier of claim 1, wherein the first stage amplification unit comprises a first common source, a first common gate, and a first transistor; the second-stage amplifying unit comprises a second common-source tube, a second common-gate tube and a second transistor; the first transistor and the second transistor are used for receiving a conduction control signal of the logic control unit so as to respectively control whether the first-stage amplifying unit and the second-stage amplifying unit are conducted or not.

3. The low noise amplifier of claim 2, wherein a drain of the first common-source is connected to a source of the first common-gate, a source of the first common-source is connected to a drain of the first transistor, and a gate of the first common-source is connected to the first signal input; the source electrode of the first transistor is grounded; the drain electrode of the first common grid tube is connected with a power supply; the drain electrode of the second common source tube is connected with the source electrode of the second common gate tube, and the source electrode of the second common source tube is connected with the drain electrode of the second transistor; the drain electrode of the second common source tube is connected with the first signal output end; the grid electrode of the second common source tube is connected with the drain electrode of the first common gate tube; the source electrode of the second transistor is grounded; the drain electrode of the second common grid tube is connected with a power supply; the grid electrode of the first transistor and the grid electrode of the second transistor are used for receiving a conduction control signal of the logic control unit.

4. The low noise amplifier according to claim 1, wherein the third amplifying unit includes a third common-source transistor, a third common-gate transistor, a third transistor, a fourth transistor, and a fifth transistor; the drain electrode of the third common source tube is connected with the source electrode of the third common gate tube, the grid electrode of the third common source tube is connected with the drain electrode of the third transistor, and the source electrode of the third transistor is connected with the drain electrode of the fourth transistor; the source electrode of the third transistor is connected with the first signal input end; the source electrode of the fourth transistor is grounded; the drain electrode of the third common grid tube is connected with the source electrode of the fifth transistor; the drain electrode of the fifth transistor is respectively connected with a power supply and the first signal output end; the grid electrode of the third transistor, the grid electrode of the fourth transistor and the grid electrode of the fifth transistor are used for receiving a conduction control signal of the logic control unit so as to control whether the third amplifying unit is conducted or not.

5. The low noise amplifier according to claim 1, wherein the low noise amplifying circuit further comprises a bias circuit for outputting an operating voltage to the first stage amplifying unit, the second stage amplifying unit, and/or the third amplifying unit; the bias circuit is used for changing the working voltage under the control of the logic control unit so as to adjust the gain gear of the first gain mode and/or the second gain mode.

6. The low noise amplifier according to claim 1, wherein the low noise amplifying circuit further comprises an attenuator for adjusting a gain gear of the low noise amplifying circuit under the control of the logic control unit; the attenuator is arranged between the second amplifying circuit and the first signal output end and/or between the first amplifying circuit and the first signal output end.

7. The low noise amplifier of claim 6, wherein the attenuator comprises at least two gain adjustment units, the at least two gain adjustment units comprising different gain stages; the logic control unit is used for controlling the working state of the attenuator so as to adjust the gain gear of the low noise amplifier.

8. The low noise amplifier of claim 6, wherein the attenuator comprises a switch assembly and at least one attenuation network, the switch assembly being configured to control an operating state of the at least one attenuation network under control of the logic controller to adjust a gain gear of the attenuator.

9. The low noise amplifier of claim 8, wherein the at least one attenuation network comprises: the T-shaped attenuation network comprises a first resistor, a second resistor and a third resistor, wherein the first resistor and the second resistor are connected in series, one end of the third resistor is connected between the first resistor and the second resistor, and the other end of the third resistor is connected with the radio frequency ground; or alternatively, the first and second heat exchangers may be,

10. The low noise amplifier of claim 8, wherein the at least one attenuation network comprises a first attenuation network and a second attenuation network;

11. The low noise amplifier of claim 10, wherein the switching component comprises a thirty-first transistor, a thirty-third transistor, a thirty-fourth transistor, a thirty-fifth transistor, a thirty-sixth transistor, and a thirty-seventh transistor; the source electrode of the thirty-first transistor is connected with the signal output end of the second-stage amplifying circuit; the drain electrode of the thirty-first transistor is connected with the first signal output end; the source electrode of the thirty-second transistor is connected with the signal output end of the second-stage amplifying circuit; the drain electrode of the thirty-fifth transistor is connected with the source electrode of the thirty-fifth transistor; the drain electrode of the thirty-fifth transistor is connected with the first signal output end; the thirty-first resistor is connected between the source and the drain of the thirty-second transistor; the drain electrode of the thirty-third transistor is connected with the source electrode of the thirty-second transistor through the thirty-second resistor, and the source electrode of the thirty-third transistor is grounded in radio frequency; the drain electrode of the thirty-fourth transistor is connected with the drain electrode of the thirty-second transistor through the thirty-third resistor, and the source electrode of the thirty-fourth transistor is grounded in radio frequency; the thirty-fifth resistor is connected between the source and the drain of the thirty-fifth transistor; the drain electrode of the thirty-sixth transistor is connected with the source electrode of the thirty-fifth transistor through the thirty-fourth resistor, and the source electrode of the thirty-sixth transistor is grounded in radio frequency; the drain electrode of the thirty-seventh transistor is connected with the drain electrode of the thirty-fifth transistor through the thirty-sixth resistor, and the source electrode of the thirty-seventh transistor is grounded in radio frequency; the gate of the thirty-first transistor, the gate of the thirty-second transistor, the gate of the thirty-third transistor, the gate of the thirty-fourth transistor, the gate of the thirty-fifth transistor, the gate of the thirty-sixth transistor, and the gate of the thirty-seventh transistor are configured to receive a turn-on control signal of the logic control unit.

12. The low noise amplifier of claim 1, wherein an input matching network is provided between the first stage amplification unit and the first signal input, the input matching network comprising an input matching adjustment circuit for adjusting an input impedance of the first gain mode.

13. The low noise amplifier according to claim 12, wherein the input matching adjustment circuit includes a sixth transistor and a third capacitor, a source of the sixth transistor is connected to a gate of the common source of the first stage amplifying unit, a drain of the sixth transistor is connected to a source of the common source of the first stage amplifying unit through the third capacitor, and a gate of the sixth transistor is configured to receive the on control signal of the logic control unit.

14. A radio frequency front end module comprising the low noise amplifier of any of claims 1-13.