CN116632953A - Adapter device and related electronic device - Google Patents
Adapter device and related electronic device Download PDFInfo
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- CN116632953A CN116632953A CN202210572880.4A CN202210572880A CN116632953A CN 116632953 A CN116632953 A CN 116632953A CN 202210572880 A CN202210572880 A CN 202210572880A CN 116632953 A CN116632953 A CN 116632953A
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- 230000001360 synchronised effect Effects 0.000 claims description 10
- 230000006872 improvement Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 9
- 238000004891 communication Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0013—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries acting upon several batteries simultaneously or sequentially
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application provides an adapter device and an electronic device, comprising a power output module, n protocol chips and n universal serial interfaces, wherein n is a positive integer greater than 1; the power output module is connected with the n protocol chips, the n protocol chips are connected with the corresponding n universal serial interfaces, and the n protocol chips are connected to a first node; any protocol chip is used for determining the number of the charging devices connected to the universal serial interface according to the voltage of the first node, and controlling the output voltage and the output current of the universal serial interface according to the number of the charging devices and the charging requirement. All protocol chips can be connected through a single pin, information synchronization of the protocol chips in the adapter device can be realized in a hardware improvement mode, and flexible charging strategies are provided for the electronic device and meanwhile cost is reduced.
Description
Technical Field
The application relates to the technical field of charging, in particular to adapter equipment and electronic equipment.
Background
With the development of technology, the application of "quick charging" of electronic devices during charging is also becoming more and more popular, and the adapter device is also required to be improved correspondingly as an intermediate device for connecting a power supply and the electronic device to be charged.
In the existing adapter device with multiple output ports, because the total output power has a certain upper limit, the output power of the output ports is higher when the adapter device is charged quickly, under the condition that the sum of the output powers of the multiple output ports cannot exceed the limit of the total output power, when a plurality of electronic devices are connected into the adapter device, a 'quick charging' strategy cannot be executed on each electronic device, in the existing mode, a protocol chip is generally arranged at each output port, and the protocol chip is configured as a master protocol chip and a slave protocol chip, and further, information synchronization between the master protocol chip and the slave protocol chip is realized by formulating a corresponding communication protocol so as to identify whether the corresponding output port has electronic device connection.
Disclosure of Invention
In view of this, the present application provides an adapter device and an electronic device, which can realize information synchronization of a protocol chip in the adapter device in a hardware improved manner, and reduce cost while providing a flexible charging policy for the electronic device.
In a first aspect, the present application provides an adapter device, including a power output module, n protocol chips, n universal serial interfaces, n being a positive integer greater than 1;
the power output module is connected with the n protocol chips, the n protocol chips are connected with the n corresponding universal serial interfaces, and the n protocol chips are connected through a first node;
any protocol chip is used for determining the number of the charging devices connected to the universal serial interface according to the voltage of the first node, and controlling the output voltage and the output current of the universal serial interface according to the number of the charging devices and the charging requirement.
In a second aspect, the application provides an electronic device comprising an adapter device according to the first aspect of the application.
The adapter device and the electronic device comprise a power output module, n protocol chips and n universal serial interfaces, wherein n is a positive integer greater than 1; the power output module is connected with the n protocol chips, the n protocol chips are connected with the corresponding n universal serial interfaces, and the n protocol chips are connected to a first node; any protocol chip is used for determining the number of the charging devices connected to the universal serial interface according to the voltage of the first node, and controlling the output voltage and the output current of the universal serial interface according to the number of the charging devices and the charging requirement. All protocol chips can be connected through a single pin, information synchronization of the protocol chips in the adapter device can be realized in a hardware improvement mode, and flexible charging strategies are provided for the electronic device and meanwhile cost is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of an adapter device according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a protocol chip according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of another protocol chip according to an embodiment of the present application;
fig. 4 is a schematic connection diagram of n protocol chips according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The terms first, second and the like in the description and in the claims and in the above-described figures are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
It should be understood that the term "and/or" is merely an association relationship describing the associated object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. In this context, the character "/" indicates that the front and rear associated objects are an "or" relationship. The term "plurality" as used in the embodiments of the present application means two or more.
The "connection" in the embodiment of the present application refers to various connection manners such as direct connection or indirect connection, so as to implement communication between devices, which is not limited in the embodiment of the present application.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an adapter device according to an embodiment of the present application, where the adapter device 100 includes a power output module 110, a protocol chip 120, and a universal serial interface 130, where n protocol chips 120 and n universal serial interfaces 130 corresponding to each protocol chip 120 one by one exist, and n is a positive integer greater than 1.
The power output module 110 is connected to the n protocol chips 120 and the n universal serial interfaces 130, the n protocol chips 120 are connected to the n corresponding universal serial interfaces 130, and the n protocol chips are connected through the first node 121.
Any one of the protocol chips 120 is configured to determine the number of charging devices connected to the universal serial interface 130 according to the voltage of the first node 121, and control the output voltage and the output current of the universal serial interface 130 according to the number of charging devices and the charging requirement.
Specifically, the power output module 110 may be an AC-DC power supply, which indicates the maximum power, the maximum current and the maximum voltage of the adapter device 100, the protocol chip 120 may control the power output module 110 to output the voltage required by the charging device connected to the usb interface from the corresponding usb interface 130, it may be understood that the n protocol chips 120 and the n usb interfaces are in one-to-one correspondence, and the protocol chip 120 and the usb interface 130 may be numbered, for example, the protocol chip 1 is connected to the corresponding usb interface 1, the protocol chip 2 is connected to the corresponding usb interface 2, and so on, the protocol chip n is connected to the corresponding usb interface n, which will not be described herein. The n protocol chips 120 are connected with each other through the first node 121, and each protocol chip 120 can determine whether the corresponding universal serial interface 130 has a charging device connected to it, and can also determine the number of charging devices currently connected to the universal serial interface 130 by detecting the voltage of the first node 121, so that the output voltage and the output current of the corresponding universal serial interface can be controlled according to the number of charging devices and the charging requirement.
Therefore, through the adapter device, all protocol chips can be connected through a single pin, and the information synchronization of the protocol chips in the adapter device is realized in a hardware improvement mode, so that flexible charging strategies are provided for the electronic device, and meanwhile, the cost is reduced.
For easy understanding, since each protocol chip has the same structure, the structure of one protocol chip in the embodiment of the present application will be described with reference to fig. 2, and fig. 2 is a schematic structural diagram of one protocol chip provided in the embodiment of the present application, where the protocol chip 120 includes a chip voltage terminal VDD, a first triode Q1, a second triode Q2, a current source terminal I, a processor CMP, an information synchronization switch S, an information synchronization pin SEL, a first resistor R1, a second resistor R2, and an output terminal PUT.
The chip voltage terminal VDD is respectively connected to the first end of the first triode Q1, the first end of the second triode Q2, and one end of the first resistor R1, the current source terminal I is connected to the second end of the first triode Q1, the third end of the first triode Q1 is connected to the third end of the second triode Q2, the second end of the second triode Q2 is connected to one end of the processor CMP and one end of the information synchronization switch S, the other end of the processor CMP is connected to the other end of the first resistor R1 and one end of the second resistor R2, the other end of the second resistor R2 is grounded, the other end of the information synchronization switch S is connected to the information synchronization pin SEL, and it can be understood that the output terminal PUT is connected to a corresponding universal serial interface 130.
Specifically, the current source terminal I is a constant current source generated inside the protocol chip 120, io is a current source after the current mirror is turned over, and the information synchronization switch S is a function switch of the information synchronization pin SEL.
Specifically, the output port PUT may include a VBUS pin, a DM pin, a DP pin, a CC pin, and the like, where the VBUS pin, the DM pin, the DP pin, the CC pin, and the like are respectively connected to the universal serial interface 130, that is, the corresponding universal serial interface 130 also includes signal lines corresponding to the VBUS pin, the DM pin, the DP pin, the CC pin, and the like.
For convenience of understanding, the structure of another protocol chip in the embodiment of the present application will be described with reference to fig. 3, and fig. 3 is a schematic structural diagram of another protocol chip provided in the embodiment of the present application, it can be understood that the protocol chip 120 has a current detection loop 310, a first current detection pin CSN, a second current detection pin CSP, a ground pin GND, and a current detection resistor Rn added to the protocol chip provided in fig. 2;
one end of the current detection loop 310 is connected with the first current detection pin CSN, the other end of the current detection loop 310 is connected with the second current detection pin CSP, the first current detection pin CSN is connected with one end of the current detection resistor Rn, one end of the current detection resistor Rn is also connected with the grounding pin GND, and the other end of the current detection resistor Rn is connected with the second current detection pin CSP and grounded;
the current detection loop 310 is configured to detect a real-time current of the universal serial interface 130 corresponding to the protocol chip 120.
The above-mentioned parts not described in detail may refer to the protocol chip described in fig. 2, and are not described herein.
After describing the configuration of the protocol chips 120, the connection relationship between the protocol chips may be further described, it may be understood that each protocol chip 120 is connected to the first node 121 through the information synchronization pin SEL, and the first node 121 is further connected to one end of a pull-down resistor Rs, and the other end of the pull-down resistor Rs is grounded;
the arbitrary protocol chip 120 determines the number of charging devices connected to the n usb interfaces 130 by detecting the voltage of the first node 121, and determines the output voltage of the output terminal PUT according to the number of charging devices and the requirement of the charging devices.
For easy understanding, referring to fig. 4 for illustrating the connection relationship between protocol chips, fig. 4 is a schematic connection diagram of n protocol chips according to an embodiment of the present application, it can be seen that the information synchronization pin SEL of the protocol chip 1 and the information synchronization pin SEL of the protocol chip n are both connected to the same first node 121, the voltage of the first node is Vsel, and the first node is connected to one end of the pull-down resistor Rs, while the other end of the pull-down resistor Rs is grounded.
For ease of understanding, the function and circuit flow of the protocol chip are further described below:
in one possible embodiment, when no charging device accesses the universal serial interface corresponding to the protocol chip, the protocol chip controls the information synchronous switch of the protocol chip to be turned off.
In a possible embodiment, when the charging device is connected to the universal serial interface corresponding to the protocol chip, the protocol chip controls the information synchronous switch of the protocol chip to be closed, then the number of the charging devices is determined according to the voltage of the first node, the number of the charging devices comprises 1, and when the number of the charging devices is 1, the protocol chip is controlled to output a first output voltage and a first output current according to the charging requirement of the charging device and the real-time current; when the number of the charging devices is x, x is a positive integer greater than 1, the universal serial interface corresponding to the protocol chip is controlled to output a second output voltage and a second output current according to the charging requirement of each charging device and the real-time current, and the output of the universal serial interface is connected in parallel, so that the values of the second output voltages of the output voltages of each universal serial interface are the same, the second output currents with different configuration values are different according to the charging requirement of each charging device, when the charging device is charged, the charging device is charged by default of 5V, and when the charging device is charged by fast charging, the charging device can apply for high-voltage charging of more than 5V, for example, assuming that the maximum power which can be output by the power adapter is 50W, the maximum voltage is 10V, and the maximum current is 5A; when the number of the charging devices is 1, the maximum charging voltage of the charging device 1 is 10V, the maximum charging current is 5A, and the charging device 1 can request the maximum power to the power adapter, then a charging strategy within 10V and 5A (including 10V and 5A) can be provided for the charging device 1 according to the actual charging requirement of the charging device 1; when the number of the charging devices is 3, the maximum voltage which can be supported by the 3 charging devices is not necessarily consistent, and under the premise that the power output is only one, at this time, as the protocol chip corresponding to each universal serial interface can know that the number of the current charging devices is 3 through the voltage of the first node, the default output voltage of the adapter device when the adapter device provides common charging is 5V, the adapter device is not supported to request quick charging of other than 5V, at this time, charging strategies within 5V and 5A (including 5V and 5A) can be provided for the charging devices 1 to 3 according to the actual charging requirements of the charging devices 1 to 3, and charging currents are allocated according to the charging requirements of the charging devices 1 to 3, and the sum of currents requested by the 3 charging devices is not more than 5A; if charging device 1 requested 1A current and charging device 2 requested 2A current, charging device 3 requested 1A current, the total output current was 4A, and the total output power was 20w, and the maximum output power of the adapter device was not exceeded.
It may be appreciated that the foregoing examples are not meant to be limiting of the embodiments of the present application, and the adapter device of the present application may have different default output voltages according to the scene requirements, and may provide a fast charging policy and a normal charging policy for a charging device accessing a universal serial interface when the sum of fast charging powers corresponding to the fast charging requirements required for the charging device accessing the universal serial interface is not greater than the maximum power supported by the adapter device in the embodiments of the present application; when the fast charging power required by the charging device connected to the universal serial interface is greater than the maximum power supported by the adapter device in the embodiment of the present application, a common charging policy may be provided for the charging device connected to the universal serial interface, that is, a default output voltage is provided for each charging device, and a common charging current is configured according to the charging requirement of each charging device, which is not described herein.
In a possible embodiment, in the aspect of determining the number of charging devices according to the voltage of the first node, the arbitrary protocol chip is configured to obtain a preset total voltage and the voltage of the first node, and determine the number of charging devices according to a quotient of the preset total voltage and the voltage of the first node.
For ease of understanding, the following is illustrative.
When the universal serial interface corresponding to the adapter device in the embodiment of the application has no charging device access, the information synchronous switches of all protocol chips in the adapter device are disconnected, and the universal serial interface outputs default voltage or does not output voltage.
When a charging device is connected to the universal serial bus interface USBi, the protocol chip ICi controls the information synchronous switch Si of the charging device to be closed, the constant current source Ii of the ICi is turned over by the current mirror, and the current source Ioi flows through the pull-down resistor Rs to generate the voltage Vseli of the first node, at this time, vseli=rs× Ioi, the ICi communicates the output voltage and the output current required by the charging device through the signal line of the USBi, and controls the power output module to output the voltage required by the charging device. It will be appreciated that the charging device may be charged quickly for this time.
When the first charging device is performing fast charging, the second charging device is connected to the usb port at this time, the protocol chip ICj controls the information synchronization switch Sj to be closed, the current source Ioj of ICj, which is turned over by the current mirror, flows through the pull-down resistor Rs to generate the voltage Vselj of the first node, and at this time, the total voltage vsel=vseli+vselj of the first node, and since each protocol chip is the same, vseli=vselj. At this time, the two protocol chips can detect the voltage of Vsel, and can know that several charging devices are currently connected through the voltage of Vsel, for example, the ICi can determine that the number of charging devices connected through Vsel/Vseli is 2, and the icj can determine that the number of charging devices connected through Vsel/Vseli is 2, which is not described herein.
When the ICi detects that another charging device is connected to the USBj, the output voltage of the USBi is immediately closed and the preset duration is waited, after the output voltage of the USBi is reduced to be within a preset voltage threshold, the ICi opens the USBi to charge the charging device, and similarly, ICj synchronously opens the USBj to charge the charging device at the moment, because two charging devices exist at the moment, the total power of the AD-DC power supply is constant, and protocol chips ICi and ICj can detect the current on respective current detection loops through respective CSP pins and CSN pins so as to perform power distribution on respective universal serial interfaces, and flexibly adjust the output voltage, the output current and the output power of the respective universal serial interfaces in real time. It will be appreciated that whether or not the fast charge can be performed on both charging devices may be based on the total power of the AC-DC and the power required by each of the two charging devices in the fast charge mode, and that the fast charge strategy may be performed on both charging devices when the total power is greater than the sum of the powers required by both charging devices in the fast charge mode, and may not be performed on both charging devices when the total power is less than the sum of the powers required by both charging devices in the fast charge mode.
When the third charging device is connected to the USB k, the protocol chip ICk controls the information synchronization switch Sk of itself to be closed, the constant current source Ik of ICk is turned over by the current mirror, and the current source Iok flows through the pull-down resistor Rs to generate the voltage Vselk of the first node, where the total voltage vsel=vseli+vselj+vselk of the first node, at this time, ICi, ICj, ICk detects that the number of charging devices connected to the adapter device is 3, ICi, ICj, ICk will pass through the number of devices currently connected to the adapter device, and the current conditions on the CSP and CSN current detection loops, and adjusts the charging voltage and the charging current of each USB universal serial interface in real time.
When the nth charging device accesses the universal serial interface, the working signal flow of each protocol chip refers to the above description, and it should be noted that, the number of charging devices that the adapter device in the embodiment of the present application can support access at most is determined by the pull-down resistor Rs, the maximum output current Io and the voltage Vsel of the first node.
Therefore, through the adapter device, each protocol chip can determine the number of charging devices which are connected to the universal serial interface at present, when the charging devices are pulled out of the universal serial interface, each protocol chip can detect the reduction of the number of the charging devices connected to the universal serial interface and synchronously adjust the power allocated to the charging devices which are still connected to the universal serial interface, so that each charging device connected to the universal serial interface can be allocated to the current maximum power allowed.
In one possible embodiment, when the charging device is gradually pulled out from a plurality of charging devices, and only one charging device is left to access the universal serial interface finally, the corresponding protocol chip can provide the maximum output voltage, the maximum output current and the maximum output power for the charging device according to the requirement of the charging device.
In one possible embodiment, when the charging device bell is gradually full, the real-time current required by the charging device bell is gradually reduced, the protocol chip can detect that the real-time current is smaller and smaller through the current detection loop, and when the current detection loop is smaller than a preset current threshold value, the protocol chip can adjust the output loop to reduce the output voltage of the universal serial interface so as to protect the charging device.
It can be seen that, through the above-mentioned adapter device, including power output module, n protocol chips, n universal serial interfaces, n is a positive integer greater than 1; the power output module is connected with the n protocol chips, the n protocol chips are connected with the corresponding n universal serial interfaces, and the n protocol chips are connected to a first node; any protocol chip is used for determining the number of the charging devices connected to the universal serial interface according to the voltage of the first node, and controlling the output voltage and the output current of the universal serial interface according to the number of the charging devices and the charging requirement. All protocol chips can be connected through a single pin, information synchronization of the protocol chips in the adapter device can be realized in a hardware improvement mode, complex communication protocols are not required to be set, peripheral devices are few, logic of each protocol chip is identical, a master chip and a slave chip are not required to be set, and cost is reduced while flexible charging strategies are provided for electronic equipment.
An electronic device 500 according to an embodiment of the present application is described below with reference to fig. 5, and the electronic device 500 may include the above-mentioned adapter device, which is not described herein.
The adapter device and the electronic device comprise a power output module, n protocol chips and n universal serial interfaces, wherein n is a positive integer greater than 1; the power output module is connected with the n protocol chips, the n protocol chips are connected with the corresponding n universal serial interfaces, and the n protocol chips are connected to a first node; any protocol chip is used for determining the number of the charging devices connected to the universal serial interface according to the voltage of the first node, and controlling the output voltage and the output current of the universal serial interface according to the number of the charging devices and the charging requirement. All protocol chips can be connected through a single pin, information synchronization of the protocol chips in the adapter device can be realized in a hardware improvement mode, and flexible charging strategies are provided for the electronic device and meanwhile cost is reduced.
It should be noted that, for simplicity of description, the foregoing embodiments of the application are all described as a series of acts, but it should be understood by those skilled in the art that the present application is not limited by the order of acts described, as some steps may be performed in other orders or concurrently in accordance with the present application. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required for the present application.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
In the several embodiments provided by the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, such as the above-described division of units, merely a division of logic functions, and there may be additional manners of dividing in actual implementation, such as multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, or may be in electrical or other forms.
The units described above as separate components may or may not be physically separate, and components shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The foregoing has outlined rather broadly the more detailed description of embodiments of the application, wherein the principles and embodiments of the application are explained in detail using specific examples, the description of the embodiments being merely intended to facilitate an understanding of the application and its core concepts; meanwhile, as those skilled in the art will appreciate, modifications will be made in the specific embodiments and application scope in accordance with the idea of the present application, and the present disclosure should not be construed as limiting the present application.
Claims (10)
1. An adapter device, comprising: the power output module, n protocol chips, n universal serial interfaces, n is a positive integer greater than 1;
the power output module is connected with the n protocol chips, the n protocol chips are connected with the n corresponding universal serial interfaces, and the n protocol chips are connected through a first node;
and any protocol chip is used for determining the number of the charging devices connected to the universal serial interface according to the voltage of the first node and controlling the output voltage and the output current of the universal serial interface according to the number of the charging devices and the charging requirement.
2. The adapter device of claim 1, wherein the arbitrary protocol chip comprises a chip voltage terminal, a first triode, a second triode, a current source terminal, a processor, an information synchronization switch, an information synchronization pin, a first resistor, a second resistor, and an output terminal;
the chip voltage end is respectively connected with the first end of the first triode, the first end of the second triode and one end of the first resistor, the current source end is connected with the second end of the first triode, the third end of the first triode is connected with the third end of the second triode, the second end of the second triode is connected with one end of the processor and one end of the information synchronous switch, the other end of the processor is connected with the other end of the first resistor and one end of the second resistor, the other end of the second resistor is grounded, the other end of the information synchronous switch is connected with the information synchronous pin, and the output end of the information synchronous switch is connected with a corresponding universal serial interface;
each protocol chip is connected to the first node through the information synchronization pin, the first node is also connected with one end of a pull-down resistor, and the other end of the pull-down resistor is grounded;
the arbitrary protocol chip determines the number of charging devices connected to the n universal serial interfaces by detecting the voltage of the first node, and determines the output voltage and the output current of the output terminal according to the number of the charging devices and the charging requirements of the charging devices.
3. The adapter device of claim 2, wherein the any one of the protocol chips further comprises a current sense loop, a first current sense pin, a second current sense pin, a ground pin, and a current sense resistor;
one end of the current detection loop is connected with the first current detection pin, the other end of the current detection loop is connected with the second current detection pin, the first current detection pin is connected with one end of the current detection resistor, one end of the current detection resistor is also connected with the grounding pin, and the other end of the current detection resistor is connected with the second current detection pin and grounded;
and the arbitrary protocol chip detects the real-time current of the universal serial interface through the current detection loop, and determines the output voltage and the output current of the output end through the real-time current and the charging requirement.
4. An adapter device according to claim 2 or 3, characterized in that,
the output end comprises a VBUS pin, a DM pin, a DP pin and a CC pin, wherein the VBUS pin, the DM pin, the DP pin and the CC pin are respectively connected with the universal serial interface.
5. The adapter device of any of claims 1-4 wherein the power output module comprises an AC-DC power supply.
6. The adapter device according to any of claims 1-5, characterized in that,
the arbitrary protocol chip is used for:
and when no charging equipment is connected to the universal serial interface corresponding to any protocol chip, the information synchronous switch of the protocol chip is controlled to be disconnected.
7. The adapter device according to any of claims 1-6, characterized in that,
the arbitrary protocol chip is used for:
when the charging equipment is connected to the universal serial interface corresponding to any protocol chip, the information synchronous switch of the protocol chip is controlled to be closed;
determining the number of the charging devices according to the voltage of the first node, wherein the number of the charging devices comprises 1;
and when the number of the charging devices is 1, controlling the universal serial interfaces corresponding to the protocol chip to output a first output voltage and a first output current according to the charging requirements of the charging devices and the real-time current.
8. The adapter device of claim 7 wherein the adapter device is configured to,
the number of the charging devices comprises x, and x is a positive integer greater than 1; after determining the number of charging devices according to the voltage of the first node, the arbitrary protocol chip is further configured to:
and when the number of the charging devices is x, controlling the universal serial interface corresponding to the protocol chip to output a second output voltage and a second output current according to the charging requirement and the real-time current of each charging device.
9. The adapter device according to claim 7, wherein in the determining the number of the charging devices according to the voltage of the first node, the arbitrary protocol chip is configured to:
acquiring a preset total voltage and the voltage of the first node;
and determining the number of the charging devices according to the quotient of the preset total voltage and the voltage of the first node.
10. An electronic device comprising the adapter device of any of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210572880.4A CN116632953A (en) | 2022-02-11 | 2022-02-11 | Adapter device and related electronic device |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210129909.1A CN114172247B (en) | 2022-02-11 | 2022-02-11 | Adapter device and electronic device |
| CN202210572880.4A CN116632953A (en) | 2022-02-11 | 2022-02-11 | Adapter device and related electronic device |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210129909.1A Division CN114172247B (en) | 2022-02-11 | 2022-02-11 | Adapter device and electronic device |
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| Publication Number | Publication Date |
|---|---|
| CN116632953A true CN116632953A (en) | 2023-08-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210129909.1A Active CN114172247B (en) | 2022-02-11 | 2022-02-11 | Adapter device and electronic device |
| CN202210572880.4A Pending CN116632953A (en) | 2022-02-11 | 2022-02-11 | Adapter device and related electronic device |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202210129909.1A Active CN114172247B (en) | 2022-02-11 | 2022-02-11 | Adapter device and electronic device |
Country Status (2)
| Country | Link |
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| CN (2) | CN114172247B (en) |
| WO (1) | WO2023151569A1 (en) |
Families Citing this family (1)
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| CN114172247B (en) * | 2022-02-11 | 2022-05-17 | 深圳英集芯科技股份有限公司 | Adapter device and electronic device |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9735820B2 (en) * | 2013-03-15 | 2017-08-15 | Microchip Technology Incorporated | Multi-current harmonized paths for low power local interconnect network (LIN) receiver |
| US20180339597A1 (en) * | 2017-05-23 | 2018-11-29 | Martin Kruszelnicki | Charging connector |
| CN212343388U (en) * | 2020-07-10 | 2021-01-12 | 深圳英集芯科技有限公司 | Be used for battery charging outfit interface to ground short-circuit protection circuit |
| CN113629802B (en) * | 2021-07-15 | 2024-04-05 | 深圳天德钰科技股份有限公司 | Power supply device |
| CN115693877A (en) * | 2021-07-23 | 2023-02-03 | 深圳英集芯科技股份有限公司 | Power adapter, charging control method, and related medium and program product |
| CN113629806A (en) * | 2021-08-04 | 2021-11-09 | 闪极科技(深圳)有限公司 | Multi-interface charger with freely-distributed output power |
| CN114172247B (en) * | 2022-02-11 | 2022-05-17 | 深圳英集芯科技股份有限公司 | Adapter device and electronic device |
-
2022
- 2022-02-11 CN CN202210129909.1A patent/CN114172247B/en active Active
- 2022-02-11 CN CN202210572880.4A patent/CN116632953A/en active Pending
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| CN114172247B (en) | 2022-05-17 |
| CN114172247A (en) | 2022-03-11 |
| WO2023151569A1 (en) | 2023-08-17 |
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