CN116632004A - Parallel MOS tube, differential pair, layout method and integrated circuit - Google Patents
Parallel MOS tube, differential pair, layout method and integrated circuit Download PDFInfo
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Abstract
The application discloses a parallel MOS tube, a differential pair, a layout method and an integrated circuit, wherein one parallel MOS tube comprises n linear parallel structures, and each linear parallel structure comprises m MOS tubes arranged along a first direction; the n straight-line parallel structures are arranged along the second direction; the sources of the m MOS tubes are connected through a first metal strip, and the drains of the m MOS tubes are connected through a second metal strip; the first metal strips of the adjacent linear parallel structures are arranged adjacently, or the second metal strips of the adjacent linear parallel structures are arranged adjacently; n and m are integers greater than or equal to 2; the first metal strips of the n straight-line parallel structures are connected with each other, and the second metal strips of the n straight-line parallel structures are connected with each other, so that the n straight-line parallel structures jointly form the parallel MOS tube. The application can make the parallel MOS tube and the related integrated circuit work at higher frequency and increase gain by improving the MOS tube connection structure.
Description
Technical Field
The application relates to the technical field of integrated circuits, in particular to a parallel MOS tube, a differential pair, a layout method and an integrated circuit.
Background
The differential circuit is a circuit having a characteristic of "suppressing a common mode signal and amplifying a differential mode signal". The input end of the circuit is the input of two signals, the difference value of the two signals is the effective input signal of the circuit, and the output of the circuit is the amplification of the difference value of the two input signals. If the interference signal exists, the same interference can be generated on the two input signals, and the effective input of the interference signal is zero through the difference between the two input signals, so that the aim of resisting common-mode interference is fulfilled.
Differential pairs (Differential Pair) are widely used in circuitry for differential signal amplification. As signal frequencies get higher, so too does the performance requirements for differential pairs. It is desirable that the gain of the differential pair be increased while it is desirable that the differential pair support higher frequency transmissions.
In the circuit system, the MOS transistor is a four-port device, namely a gate terminal (g), a source terminal(s), a drain terminal (drain, d) and a substrate (bulk, b). In practical application, the maximum working frequency fmax of the MOS transistor is:the method comprises the steps of carrying out a first treatment on the surface of the Wherein: rgate is the gate resistance, cgg is the gate capacitance; rsource is the source resistor and Css is the source capacitor; rdrain is drain resistance and Cdd is drain capacitance. In the circuitry, it is desirable that fmax be as large as possible, preferably close to fT (the cut-off operating frequency of the MOS transistor), and it is seen that reducing the capacitance between the drain and the source may allow the differential pair to operate at higher frequencies.
Disclosure of Invention
In order to improve the working frequency and gain of the differential pair, the application provides a parallel MOS tube, a differential pair, a layout method and an integrated circuit, and the parallel MOS tube and the related integrated circuit can work at higher frequency and gain by improving the connection structure of the MOS tube.
Specifically, the technical scheme of the application is as follows:
in a first aspect, the present application discloses a parallel MOS transistor for an integrated circuit, characterized in that,
the MOS transistor comprises n linear parallel structures, wherein each linear parallel structure comprises m MOS transistors arranged along a first direction; the n straight-line parallel structures are arranged along the second direction;
the sources of the m MOS tubes are connected through a first metal strip, and the drains of the m MOS tubes are connected through a second metal strip; the first metal strips of the adjacent linear parallel structures are arranged adjacently, or the second metal strips of the adjacent linear parallel structures are arranged adjacently;
n and m are integers greater than or equal to 2; the first metal strips of the n straight-line parallel structures are connected with each other, and the second metal strips of the n straight-line parallel structures are connected with each other, so that the n straight-line parallel structures jointly form the parallel MOS tube.
In some embodiments, the second direction is a stacking direction of the multi-layer chip structure, and the first metal strips and the second metal strips of the n straight parallel structures are respectively connected to each other through vias.
In a second aspect, the application also discloses a differential pair,
the differential pair comprises a first MOS tube and a second MOS tube, wherein the first MOS tube and the second MOS tube are parallel MOS tubes as claimed in claim 1 or 2;
one of a source electrode and a drain electrode of the first MOS tube is connected with one of a source electrode and a drain electrode of the second MOS tube.
In some embodiments, the two parallel MOS transistors are arranged in parallel along a third direction, and the first direction, the second direction, and the third direction are perpendicular to each other.
In some embodiments, the first MOS transistor and the second MOS transistor have the same number of straight parallel structures arranged in parallel one by one.
In some embodiments, the differential pair is an NMOS differential pair, and the first metal strips of the first MOS transistor and the first metal strips of the second MOS transistor are arranged in parallel one by one and are connected to each other;
or the differential pair is a PMOS tube differential pair, and the second metal strips of the first MOS tube and the second metal strips of the second MOS tube are arranged in parallel one by one and are connected with each other.
In a third aspect, the present application also discloses a layout method of an integrated circuit, for forming parallel MOS transistors, which is characterized by comprising the steps of:
arranging m MOS tubes along a first direction to form a linear parallel structure;
arranging n straight-line parallel structures along a second direction to form a parallel array;
connecting sources of m MOS tubes with a linear parallel structure through a first metal strip, and connecting drains through a second metal strip;
the first metal strips of the adjacent linear parallel structures are arranged adjacently, or the second metal strips of the adjacent linear parallel structures are arranged adjacently;
the first metal strips of the n straight-line parallel structures are connected with each other, and the second metal strips of the n straight-line parallel structures are connected with each other, so that the n straight-line parallel structures jointly form a parallel MOS tube;
wherein n and m are integers greater than or equal to 2.
In some embodiments, the second direction is a stacking direction of the multi-layer chip structure, and the first metal strips of the n straight parallel structures are connected by through holes; and the second metal strips of the n straight parallel structures are connected through holes.
In some embodiments, the method further comprises the step of:
arranging two parallel MOS tubes in parallel, wherein the two parallel MOS tubes have the same number and are in a straight parallel structure which is arranged in parallel one by one;
one of the first metal strip and the second metal strip of one parallel MOS tube and one of the first metal strip and the second metal strip of the other parallel MOS tube are arranged in parallel one by one and are connected with each other.
In a fourth aspect, the application also discloses an integrated circuit, which is characterized in that,
the parallel MOS transistor comprises the parallel MOS transistor in any embodiment.
Compared with the prior art, the application has at least one of the following beneficial effects:
1. the structure of the parallel MOS tube is suitable for an integrated circuit, and can improve the power and efficiency of the circuit and the reliability of the circuit.
2. The differential pair structure is provided, the layout structure of the differential pair circuit is improved, two adjacent layers of metal strips with the same properties are designed together, the overall capacitance of the parallel MOS tube structure is reduced, the working frequency of the parallel MOS tube can be effectively improved, and meanwhile, the working frequency of the differential pair is improved. The source metal strips of the subcircuits of each layer are connected in parallel through metal through holes, so that the differential pair gain is improved.
3. The layout of the integrated circuit can be spliced and expanded, a plurality of MOS tubes can be designed in each layer of sub-circuit to be connected in parallel, the capacitance generated by a source electrode end and a drain electrode end can be obviously reduced, and the parallel MOS tubes and differential pairs can work at higher frequency. And the more MOS tubes connected in parallel, the larger the generated operational amplifier gain.
Drawings
The above features, technical features, advantages and implementation of the present application will be further described in the following description of preferred embodiments with reference to the accompanying drawings in a clear and easily understood manner.
FIG. 1 is a schematic layout of a conventional parallel MOS tube structure;
FIG. 2 is a schematic layout of the connection of an improved parallel MOS tube structure provided by the application;
FIG. 3 is a cross-sectional view of a conventional differential pair;
FIG. 4 is a cross-sectional view of a differential pair modified in accordance with the teachings of the present application;
fig. 5 is an equivalent circuit diagram of a differential pair structure provided by the present application;
fig. 6 is a schematic layout of connection of an improved differential pair structure according to the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
For simplicity of the drawing, only the parts relevant to the application are schematically shown in each drawing, and they do not represent the actual structure thereof as a product. Additionally, in order to simplify the drawing for ease of understanding, components having the same structure or function in some of the drawings are shown schematically with only one of them, or only one of them is labeled. Herein, "a" means not only "only this one" but also "more than one" case.
It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
In this context, it should be noted that the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected, unless explicitly stated or limited otherwise; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
In particular implementations, the terminal devices described in embodiments of the present application include, but are not limited to, other portable devices such as mobile phones, laptop computers, home teaching machines, or tablet computers having touch-sensitive surfaces (e.g., touch screen displays and/or touchpads). It should also be appreciated that in some embodiments, the terminal device is not a portable communication device, but rather a desktop computer having a touch-sensitive surface (e.g., a touch screen display and/or a touch pad).
In addition, in the description of the present application, the terms "first," "second," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following description will explain the specific embodiments of the present application with reference to the accompanying drawings. It is evident that the drawings in the following description are only examples of the application, from which other drawings and other embodiments can be obtained by a person skilled in the art without inventive effort.
The embodiment of the parallel MOS tube is used for an integrated circuit.
The MOS transistor comprises n linear parallel structures, wherein each linear parallel structure comprises m MOS transistors arranged along a first direction. The n straight parallel structures are arranged along the second direction.
Specifically, the parallel MOS transistor is generally used to improve the gain of the op-amp. Each layer of straight line parallel structure comprises a first metal strip and a second metal strip, and the first metal strip and the second metal strip are used for connecting the source electrode or the drain electrode of the parallel MOS tube.
Specifically, a schematic layout of a traditional parallel MOS tube structure refers to an attached figure 1 of the specification, taking 16 MOS tubes as an example, and adopting a 4*4 drawing method. S and D in the shaded portion of fig. 1 represent a first metal stripe for source connection and a second metal stripe for drain connection, respectively. A larger capacitance exists between the adjacent first metal strip and the second metal strip, if the capacitance (n > =2) of the metal between n layers is not considered, the capacitance between the metal connected with the source electrode in each layer of the linear parallel structure and the metal connected with the drain electrode in the adjacent layer of the linear parallel structure is assumed to be Cds.
The sources of the m MOS tubes are connected through a first metal strip, and the drains of the m MOS tubes are connected through a second metal strip. The first metal strips of the adjacent linear parallel structures are arranged adjacently, or the second metal strips of the adjacent linear parallel structures are arranged adjacently.
Specifically, the parallel MOS tube structure provided by the application connects the source terminal of each layer of the multi-layer chip structure stack with the source terminal of the adjacent layer. The schematic layout of the optimized parallel MOS tube structure is shown in fig. 2, wherein two adjacent S or two adjacent D can be regarded as being completely connected, and can also be regarded as sharing the same metal strip, so that no capacitor exists.
Comparing fig. 1 and fig. 2, it can be seen that the total capacitance existing between D and S in the conventional parallel MOS transistor structure is 7 cds. The method of drawing the adjacent first metal strips in the straight parallel structure or the adjacent second metal strips in the straight parallel structure is adopted, as shown in fig. 2, the mode of connection of SD DS DS. or DS SD DS SD. is adopted, the capacitance between D and S is reduced, and the total capacitance between D and S is 4×cds and is reduced to 4/7 of the original capacitance.
Generally, when the drawing method of n rows is adopted, compared with the traditional structure, cds of the optimized structure can be reduced to n/(2*n-1) originally, when n approaches infinity, cds of the optimized structure can be reduced to 1/2 of the original Cds, and the capacitance seen by D and S can be obviously reduced.
To sum up, the total capacitance C of the parallel MOS transistor circuit can be expressed as:the method comprises the steps of carrying out a first treatment on the surface of the Wherein n is the n straight-line parallel structures of the parallel MOS tubes.
The capacitor Cds can be split:wherein: css is the source capacitance, cdd is the drain capacitance, < ->And->Is a constant value parameter and is determined according to specific circuit conditions.
The working frequency f of the parallel MOS tube circuit is as follows:
in general, the gate capacitance Cgg is much larger than the source capacitance Css and the drain capacitance Cdd. Therefore, the reduction of the source capacitance Css and the drain capacitance Cdd can affect the increase of the operating frequency f of the circuit, so that the overall parallel MOS transistor circuit operates at a higher frequency.
In another implementation manner of this embodiment, there is another case that the drains of the m MOS transistors are connected through a first metal strip, and the sources are connected through a second metal strip.
In another embodiment of the parallel MOS transistor of the present application, on the basis of the above embodiment of the parallel MOS transistor, the second direction is a stacking direction of a multi-layer chip structure, and the first metal strips of the n straight parallel structures are connected through holes; and the second metal strips of the n straight parallel structures are connected through holes.
Specifically, in the embodiment, the first direction and the second direction are perpendicular to each other. The first direction and the second direction are respectively an X-axis direction and a Y-axis direction by taking a space rectangular coordinate system as a standard, and the array can be formed in the plane direction in the same way, namely the first direction and the second direction are respectively an X-axis direction and a Z-axis direction.
n and m are integers greater than or equal to 2. The first metal strips of the n straight-line parallel structures are connected with each other, and the second metal strips of the n straight-line parallel structures are connected with each other, so that the n straight-line parallel structures jointly form the parallel MOS tube.
Based on the same technical conception, the application also discloses a differential pair, which is characterized by comprising a first MOS tube and a second MOS tube, wherein the first MOS tube and the second MOS tube are both parallel MOS tubes described in the embodiment.
One of a source electrode and a drain electrode of the first MOS tube is connected with one of a source electrode and a drain electrode of the second MOS tube.
The first MOS tubes and the second MOS tubes have the same number and are in a straight line parallel structure which is arranged in parallel one by one.
Specifically, the two parallel MOS tubes which are of the same type and symmetrical in structure are connected to form a differential pair structure. The differential pair structure can constitute a differential amplifier excellent in performance in the simplest manner.
Specifically, a structural cross-section of a conventional differential pair is shown in fig. 3 of the specification. Taking an NMOS tube differential pair circuit as an example, as shown in the figure, the left half part is of a first MOS tube structure, the right half part is of a second MOS tube structure, and after the parallel MOS tubes are respectively connected to the top layer from the bottom layer, the source ends of the parallel MOS tubes are connected by using top layer metal.
Wherein: the broken line part is a resistor connected with the wiring, and M0-M3 are respectively each layer of straight line parallel structure of the multi-layer parallel MOS tube structure. VIA0-VIA2 are through holes connected between two layers of straight parallel structures. In fig. 3, 4 layers are taken as an example. R0 is the wiring resistance of the parallel MOS transistors from M0 to M3, and R1 is the wiring resistance of M3. In the figure, the source ends of the first MOS tube and the second MOS tube are respectively connected from M0 to M3, and then are connected with the source ends between the first MOS tube and the second MOS tube through M3. Circuit structure equivalent resistance rs=r0+r1+r0.
In another implementation manner of this embodiment, the differential pair is an NMOS differential pair, and the first metal strips of the first MOS transistor and the first metal strips of the second MOS transistor are arranged in parallel one by one and are connected to each other.
Or the differential pair is a PMOS tube differential pair, and the second metal strips of the first MOS tube and the second metal strips of the second MOS tube are arranged in parallel one by one and are connected with each other.
Referring to fig. 4 of the specification, in the improved differential pair circuit structure provided by the application, an NMOS differential pair circuit is taken as an example, and a broken line part is a resistor connected with a wiring. M0-M3 are each layer of straight line parallel structure of the multi-layer parallel MOS tube structure. VIA0-VIA2 are through holes connected between two layers of straight parallel structures. The source ends of each layer of structure of the first MOS tube and the second MOS tube are connected together.
Specifically, as shown in fig. 5, an equivalent circuit diagram of the differential pair structure provided by the present application, the source metal strips after being connected in parallel form a total source resistor RS, which can be expressed as:
Rs=RM3//RM2//RM1//RM0
wherein: RM3-RM0 is the equivalent resistance of the metal strip corresponding to each layer of the sub-circuit in the 4-layer parallel structure.
Compared with the equivalent resistance of the circuit structure before improvement, the circuit structure after improvement can effectively reduce the Rs resistance, thereby achieving the purpose of improving the gain.
Specifically, the gain AV of the differential pair circuit is:
wherein: gm is the mobility of the MOS tube; r0 is the equivalent resistance between the source and drain terminals of the sub-circuit; RL is the load resistance of the MOS tube.
It can be seen that the greater the Rs, the lower the overall gain. As Rs decreases, the gain AV of the differential pair circuit increases.
Specifically, if the two parallel MOS transistors are N-channel MOS transistors, and form an NMOS differential pair circuit, source metal strips of each layer of straight parallel structure of the two N-channel MOS transistors are arranged in parallel and connected with each other. When the two parallel MOS tubes are N-channel MOS tubes, the connection mode of the differential pair structure is referred to in the specification of figure 6. The left half of the diagram corresponds to the first MOS transistor in fig. 4, and the right half corresponds to the second MOS transistor in fig. 4. The first MOS tube is connected with the first metal strip of each layer of the second MOS tube, namely the source metal strip S.
In another case, if the two parallel MOS transistors are P-channel MOS transistors to form a PMOS differential pair circuit, the second metal strips of each layer of the straight parallel structure of the two P-channel MOS transistors, that is, the drain metal strips, are arranged in parallel and connected with each other.
The embodiment may also be implemented on the basis of the prior art shown in fig. 1, that is, the first MOS transistor and the second MOS transistor still adopt the embodiment of fig. 1, and the effect of increasing the gain of the differential pair circuit may also be achieved.
In another embodiment of the differential pair provided by the present application, on the basis of any one of the differential pair embodiments, in the differential pair structure, two parallel MOS transistors are arranged in parallel along a first direction, and the first direction and the second direction are perpendicular to each other.
Specifically, every two parallel MOS tubes form a differential pair, and the layout can be expanded between the differential pair and the differential pair through parallel splicing. Wherein the parallel differential pairs are aligned along a first direction. In the embodiment, the first direction and the second direction are the X-axis direction and the Y-axis direction respectively, and in the same manner, it is theoretically possible to form an array in the plane direction, that is, the first direction and the second direction are the X-axis direction and the Z-axis direction respectively.
In another implementation manner of the differential pair embodiment of the present application, in the differential pair structure, two parallel MOS transistors are arranged in parallel along a third direction, and the first direction is perpendicular to the third direction.
Specifically, every two parallel MOS tubes form a differential pair, wherein the sub-MOS tubes in the parallel MOS tubes are arranged along a first direction, and the two parallel MOS tubes in the differential pair are arranged in parallel along a third direction.
Or two parallel MOS tubes in the differential pair are arranged in parallel along the first direction; the sub-MOS tubes in the parallel MOS tubes are all arranged along the third direction. And taking the space rectangular coordinate system as a standard, wherein the first direction, the second direction and the third direction are respectively an X axis, a Y axis and a Z axis in the space rectangular coordinate system. If the parallel arrays are arranged in parallel, they can only be arranged side by side in the first direction.
Based on the same technical conception, the application also discloses a layout method of the integrated circuit, which is used for forming the parallel MOS tube and is characterized by comprising the following steps:
and arranging m MOS tubes along a first direction to form a linear parallel structure.
And arranging the n straight-line parallel structures along a second direction to form a parallel array.
The sources of m MOS tubes with the linear parallel structure are connected through a first metal strip, and the drains are connected through a second metal strip.
The first metal strips of the adjacent straight-line parallel structures are arranged adjacently, or the second metal strips of the adjacent straight-line parallel structures are arranged adjacently.
And the first metal strips of the n straight-line parallel structures are connected with each other, and the second metal strips of the n straight-line parallel structures are connected with each other, so that the n straight-line parallel structures jointly form the parallel MOS tube.
Wherein n and m are integers greater than or equal to 2.
In another embodiment of the method of the present application, based on the above embodiment, two parallel MOS transistors of the same type are arranged in parallel to form a differential pair.
The integrated circuit of the present application may have an n-layer structure (n is greater than or equal to 2), without being limited to the 4-layer parallel structure in the above embodiments and the drawings.
Not limited to the above embodiment and the drawings, each layer of parallel structure includes 4 MOS transistors, and each layer of parallel structure may be formed by m MOS transistors (m is greater than or equal to 2).
The source metal interconnection of the M0-M3 layers described in the above embodiments and drawings is not limited, and each of the source metals of the n-layer structure is interconnected.
The layout method provided by the application further comprises the following steps on the basis of the method embodiment:
arranging two parallel MOS tubes in parallel, wherein the two parallel MOS tubes have the same number and are in a straight parallel structure which is arranged in parallel one by one;
one of the first metal strip and the second metal strip of one parallel MOS tube and one of the first metal strip and the second metal strip of the other parallel MOS tube are arranged in parallel one by one and are connected with each other.
Specifically, a structural cross-section of a conventional differential pair is shown in fig. 3 of the specification. As shown in the figure, the left half part is of a first MOS tube structure, the right half part is of a second MOS tube structure, and after the parallel MOS tubes are respectively connected to the top layer from the bottom layer, the source ends of the MOS tubes are connected by using top layer metal.
Wherein: the broken line part is a connecting wiring, and M0-M3 are respectively each layer of straight line parallel structure of the multi-layer parallel MOS tube structure. In fig. 3, 4 layers are taken as an example. R0 is the wiring resistance of the parallel MOS transistors from M0 to M3, and R1 is the wiring resistance of M3. In the figure, the source ends of the first MOS tube and the second MOS tube are respectively connected from M0 to M3, and then are connected with the source ends between the first MOS tube and the second MOS tube through M3. Circuit structure equivalent resistance rs=r0+r1+r0.
The improved differential pair circuit structure provided by the application is shown in the accompanying figure 4 in the specification: the broken line part is a connecting wire. The source ends of each layer of structure of the first MOS tube and the second MOS tube are connected together, and the drain ends are not connected. And then punching the multilayer structure in parallel.
Specifically, the source metal strips after being connected in parallel form a total source resistance RS, which can be expressed as:
Rs=RM3//RM2//RM1//RM0
wherein: RM3-RM0 is the equivalent resistance of the source electrode metal strip corresponding to each layer of the sub-circuit in the 4-layer parallel structure.
Compared with the equivalent resistance of the circuit structure before improvement, the circuit structure after improvement can effectively reduce the Rs resistance, thereby achieving the purpose of improving the gain.
Specifically, the gain AV of the differential pair circuit is:
wherein: gm is the mobility of the MOS tube; r0 is the equivalent resistance between the source and drain terminals of the sub-circuit; RL is the load resistance of the MOS tube.
It can be seen that the greater the Rs, the lower the overall gain. As Rs decreases, the gain AV of the differential pair circuit increases.
The embodiment may also be implemented on the basis of the prior art shown in fig. 1, that is, the first MOS transistor and the second MOS transistor still adopt the embodiment of fig. 1, and the effect of increasing the gain of the differential pair circuit may also be achieved.
Based on the same technical conception, the application also discloses an integrated circuit, which comprises the parallel MOS tube in any one of the parallel MOS tube embodiments.
An embodiment of the integrated circuit of the present application is as follows: the integrated circuit comprises n layers of sub-circuits, and each layer of sub-circuit is formed by connecting m MOS tubes in parallel; wherein n and m are integers not less than 2.
In the integrated circuit: the source stages of all MOS tubes of each layer are connected with the top metal strip of the layer to form a first metal strip, namely a source stage metal strip; the drain electrodes of all MOS tubes in each layer are connected with the bottom metal strip of the layer to form a second metal strip, namely a drain electrode metal strip;
in the integrated circuit, the drain metal bar of each odd layer of the sub-circuit is connected with the drain metal bar of the sub-circuit of the adjacent next even layer. The source metal strips of each even-numbered layer of the sub-circuit are connected with the source metal strips of the adjacent even-numbered layer of the sub-circuit. And (3) forming: SD DS SD DS..
Or, in the integrated circuit, the drain metal strip of each sub-circuit of the odd layer is connected with the drain metal strip of the sub-circuit of the adjacent upper even layer. The source metal stripe of each odd layer of the sub-circuit is connected to the source metal stripe of the sub-circuit of the next adjacent even layer. And (3) forming: DS SD DS SD..
The parallel MOS tube, the differential pair, the layout method and the integrated circuit have the same technical conception, and the technical details of the two embodiments can be mutually applicable, so that repetition is reduced, and the description is omitted. The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flowchart and/or block of the flowchart illustrations and/or block diagrams, and combinations of flowcharts and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (10)
1. A parallel MOS tube is used for an integrated circuit and is characterized in that,
the MOS transistor comprises n linear parallel structures, wherein each linear parallel structure comprises m MOS transistors arranged along a first direction; the n straight-line parallel structures are arranged along the second direction;
the sources of the m MOS tubes are connected through a first metal strip, and the drains of the m MOS tubes are connected through a second metal strip; the first metal strips of the adjacent linear parallel structures are arranged adjacently, or the second metal strips of the adjacent linear parallel structures are arranged adjacently;
n and m are integers greater than or equal to 2; the first metal strips of the n straight-line parallel structures are connected with each other, and the second metal strips of the n straight-line parallel structures are connected with each other, so that the n straight-line parallel structures jointly form the parallel MOS tube.
2. The parallel MOS transistor of claim 1, wherein,
the second direction is the stacking direction of the multi-layer chip structure, and the first metal strips of the n linear parallel structures are connected through holes; and the second metal strips of the n straight parallel structures are connected through holes.
3. A differential pair is characterized in that,
the differential pair comprises a first MOS tube and a second MOS tube, wherein the first MOS tube and the second MOS tube are parallel MOS tubes as claimed in claim 1 or 2;
one of a source electrode and a drain electrode of the first MOS tube is connected with one of a source electrode and a drain electrode of the second MOS tube.
4. The differential pair of claim 3,
the two parallel MOS tubes are arranged in parallel along a third direction, and the first direction, the second direction and the third direction are perpendicular to each other.
5. The differential pair of claim 3 or 4, wherein,
the first MOS tubes and the second MOS tubes have the same number and are in a straight line parallel structure which is arranged in parallel one by one.
6. The differential pair of claim 5, wherein,
the differential pair is an NMOS tube differential pair, and the first metal strips of the first MOS tube and the first metal strips of the second MOS tube are arranged in parallel one by one and are connected with each other;
or the differential pair is a PMOS tube differential pair, and the second metal strips of the first MOS tube and the second metal strips of the second MOS tube are arranged in parallel one by one and are connected with each other.
7. A method of patterning an integrated circuit for forming parallel MOS transistors, comprising the steps of:
arranging m MOS tubes along a first direction to form a linear parallel structure;
arranging n straight-line parallel structures along a second direction to form a parallel array;
connecting sources of m MOS tubes with a linear parallel structure through a first metal strip, and connecting drains through a second metal strip;
the first metal strips of the adjacent linear parallel structures are arranged adjacently, or the second metal strips of the adjacent linear parallel structures are arranged adjacently;
the first metal strips of the n straight-line parallel structures are connected with each other, and the second metal strips of the n straight-line parallel structures are connected with each other, so that the n straight-line parallel structures jointly form a parallel MOS tube;
wherein n and m are integers greater than or equal to 2.
8. The patterning process of claim 7, wherein,
the second direction is the stacking direction of the multi-layer chip structure, and the first metal strips of the n linear parallel structures are connected through holes; and the second metal strips of the n straight parallel structures are connected through holes.
9. The patterning process of claim 7, further comprising the step of:
arranging two parallel MOS tubes in parallel, wherein the two parallel MOS tubes have the same number and are in a straight parallel structure which is arranged in parallel one by one;
one of the first metal strip and the second metal strip of one parallel MOS tube and one of the first metal strip and the second metal strip of the other parallel MOS tube are arranged in parallel one by one and are connected with each other.
10. An integrated circuit, characterized in that,
comprising a parallel MOS transistor according to any of claims 1 to 2.
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