CN116631975A - Multilayer glass substrate adopting composite bonding material and manufacturing process - Google Patents
Multilayer glass substrate adopting composite bonding material and manufacturing process Download PDFInfo
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- CN116631975A CN116631975A CN202310314714.9A CN202310314714A CN116631975A CN 116631975 A CN116631975 A CN 116631975A CN 202310314714 A CN202310314714 A CN 202310314714A CN 116631975 A CN116631975 A CN 116631975A
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- 239000000758 substrate Substances 0.000 title claims abstract description 96
- 239000011521 glass Substances 0.000 title claims abstract description 95
- 239000000463 material Substances 0.000 title claims abstract description 39
- 239000002131 composite material Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000004020 conductor Substances 0.000 claims abstract description 10
- 230000000149 penetrating effect Effects 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 10
- 238000011049 filling Methods 0.000 claims description 9
- 239000004642 Polyimide Substances 0.000 claims description 8
- 229920001721 polyimide Polymers 0.000 claims description 8
- 239000011256 inorganic filler Substances 0.000 claims description 7
- 229910003475 inorganic filler Inorganic materials 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- XLJMAIOERFSOGZ-UHFFFAOYSA-M cyanate Chemical compound [O-]C#N XLJMAIOERFSOGZ-UHFFFAOYSA-M 0.000 claims description 5
- 239000000835 fiber Substances 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical group O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 claims description 4
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 239000004952 Polyamide Substances 0.000 claims description 2
- 239000001569 carbon dioxide Substances 0.000 claims description 2
- 229910002092 carbon dioxide Inorganic materials 0.000 claims description 2
- 229920002647 polyamide Polymers 0.000 claims description 2
- 238000003825 pressing Methods 0.000 claims 1
- 230000008054 signal transmission Effects 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 58
- 230000000052 comparative effect Effects 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000003365 glass fiber Substances 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 238000000227 grinding Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000005368 silicate glass Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000009477 glass transition Effects 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical group C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- BERDEBHAJNAUOM-UHFFFAOYSA-N copper(I) oxide Inorganic materials [Cu]O[Cu] BERDEBHAJNAUOM-UHFFFAOYSA-N 0.000 description 1
- KRFJLUBVMFXRPN-UHFFFAOYSA-N cuprous oxide Chemical compound [O-2].[Cu+].[Cu+] KRFJLUBVMFXRPN-UHFFFAOYSA-N 0.000 description 1
- 229940112669 cuprous oxide Drugs 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000012784 inorganic fiber Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention discloses a multi-layer glass substrate adopting composite bonding materials and a manufacturing process thereof, wherein the structure of the multi-layer glass substrate comprises at least two layers of glass substrates and bonding layers between the glass substrates; the glass substrate is provided with a through hole penetrating up and down, the bonding layer is provided with an opening, and the through hole and the opening are filled with metal conductive materials and the surface wiring layer to realize up-down interconnection; wherein the bonding layer is formed by curing a non-photosensitive composite bonding material. The composite bonding material has higher matching degree between the performances of thermal expansion coefficient, modulus and the like and the glass substrate, has lower dielectric constant and loss tangent, and can meet the requirements of high-frequency and high-speed signal transmission.
Description
Technical Field
The invention belongs to the technical field of semiconductor packaging, and particularly relates to a multilayer glass substrate adopting a composite bonding material and a manufacturing process thereof.
Background
Conventional semiconductor packages use a leadframe as an IC on-line and a carrier for supporting the IC, which connects the leads on either side or around the leadframe. With the development of semiconductor packaging technology, as the number of pins increases (more than 500 pins), conventional QFP and other packaging forms have limited their development. In this way, in the middle 90 s of the 20 th century, new semiconductor packages represented by BGA and CSP have been developed, and a new carrier necessary for packaging semiconductor chips has been produced, which is a semiconductor package substrate (IC Package Substrate, also referred to as a semiconductor package carrier).
The substrate provides electrical connection, protection, support, heat dissipation and assembly for the chip, and is a core carrier for massive I/O promotion and System In Package (SiP) under advanced technology. High-end substrates are driven by a combination of electrical, thermal, size, functionality, and cycle cost, moving toward thin thickness, high thermal dissipation, fine wiring, high integration, and short manufacturing cycles. Accordingly, advanced substrate materials should possess the following characteristics: ultra Low CTE, low Dk, low Df, high Tg, high Module, etc. The glass material has high resistivity, good insulating property and good signal isolation, can reduce crosstalk between signals, has the unique advantage of transmitting high-frequency signals, and has adjustable Coefficient of Thermal Expansion (CTE), high Young modulus and capability of solving the problem of thermal mismatch to a certain extent.
The packaging application of the conventional glass substrate is that conductive columns penetrating through the thickness direction are formed on the glass substrate, and interconnection of wiring layers on two opposite surfaces of the glass substrate is achieved through the conductive columns, so that the problem of how to achieve three-dimensional integration by adopting the glass substrate, especially stacking interconnection of a multi-layer rewiring structure, and the method is suitable for high-frequency signal transmission is solved.
Disclosure of Invention
The invention provides a multilayer glass substrate adopting a composite bonding material and a manufacturing process thereof, aiming at the defects existing in the prior art.
In order to achieve the above object, the technical scheme of the present invention is as follows:
a multi-layer glass substrate adopting composite bonding materials comprises at least two layers of glass substrates and a bonding layer arranged between the two layers of glass substrates; the surface of the glass substrate is provided with a wiring layer, the glass substrate is provided with a through hole penetrating up and down, the bonding layer is provided with an opening, and the through hole and the opening are filled with metal conductive materials and are connected up and down together with the surface wiring layer; the bonding layer is formed by solidifying a non-photosensitive composite bonding material, the non-photosensitive composite bonding material is composed of 40% -50% of organic components and 50% -60% of inorganic fillers, and the organic components comprise at least one of non-photosensitive polyimide, polyamide fibers and epoxy resin; the inorganic filler comprises at least one of cyanate, glass, silicon and silicon oxide, and is micropowder or fiber.
Alternatively, the thickness of the bonding layer is 10-100 μm, and the diameter of the inorganic filler is 0.1-0.3 μm.
Optionally, df of the bonding layer is less than 0.01, dk is less than 3.3.
Optionally, the glass substrate is quartz glass, such as quartz glass, silicate glass and the like, and the glass type can consider the mechanical parameters of the chip and the PCB substrate and select a glass wafer with similar CTE.
Optionally, the bonding layer has a coefficient of thermal expansion and a modulus matching those of the glass substrate. The non-photosensitive composite bonding material has wider glass transition temperature, thermal expansion coefficient, modulus and other selectable ranges than those of the photosensitive bonding material, and can select the performance matched with the glass substrate according to the requirements.
The manufacturing process of the multi-layer glass substrate adopting the composite bonding material comprises the following steps of:
a) Manufacturing a blind hole with an upward opening on a first glass substrate, filling a metal conductive material in the blind hole, and manufacturing a first wiring layer on the upper surface of the first glass substrate;
b) Forming a bonding layer on the upper surface of the first glass substrate by adopting the non-photosensitive composite bonding material, and forming an opening penetrating through the bonding layer by laser after pre-curing;
c) Bonding a second glass substrate with a through hole penetrating up and down to a bonding layer in a wafer-level bonding mode, and then solidifying the bonding layer;
d) Filling metal conductive materials in the through holes of the second glass substrate and the openings of the bonding layer, and manufacturing a second wiring layer on the upper surface of the second glass substrate;
e) And mechanically thinning the first glass substrate, forming a TGV through hole, and manufacturing a third wiring layer on the lower surface of the first glass substrate.
Optionally, in the step b), the organic component and the inorganic component are mixed according to the proportion to form a non-photosensitive composite bonding material sheet, and the non-photosensitive composite bonding material sheet is attached to the first glass substrate by adopting a roller film or vacuum lamination mode to form a bonding layer.
Optionally, in the step b), the pre-curing temperature is 100 ℃ to 120 ℃; in the step c), the bonding layer is baked and cured at 160-220 ℃.
Optionally, in the step b), the laser is a carbon dioxide laser or an ultraviolet laser, the diameter of the laser spot used is 10-40 μm, the number of single-hole pulses is 2000-10000, and the single-pulse energy is 1 uj-15 uj.
Optionally, the first wiring layer is exposed in the opening, and the diameter of the opening gradually increases from the bottom to the top of the exposed first wiring layer.
Alternatively, by repeating steps b) to d), a structure in which a multilayered glass substrate stack and a multilayered wiring layer are conducted up and down is formed.
The beneficial effects of the invention are as follows:
glass is adopted as a substrate, the high-frequency electronic characteristics are excellent, the CTE is adjustable, and the glass is processed according to the proper glass model found by different chips, so that the reliability of the whole package is improved; the composite bonding material is used as a bonding layer of a multi-layer glass stack, has higher matching degree between the glass transition temperature, the thermal expansion coefficient, the modulus and other performances and a glass substrate, has lower dielectric constant and loss tangent, can meet the requirement of high-frequency high-speed signal transmission, and has good reliability guarantee due to good adhesive strength.
Drawings
Fig. 1 is a schematic structural view of a multi-layered glass substrate using a composite bonding material according to example 1;
fig. 2 is a process flow chart of example 1, showing the structure obtained by each step.
Detailed Description
The invention is further explained below with reference to the drawings and specific embodiments. The drawings of the present invention are merely schematic to facilitate understanding of the present invention, and specific proportions thereof may be adjusted according to design requirements. The definition of the context of the relative elements and the front/back of the figures described herein should be understood by those skilled in the art to refer to the relative positions of the elements and thus all the elements may be reversed to represent the same elements, which are all within the scope of the present disclosure.
Example 1
Referring to fig. 1, the multi-layered glass substrate using the composite bonding material of embodiment 1, taking a two-layered glass substrate structure as an example, includes a first glass substrate 1 and a second glass substrate 2, with a bonding layer 3 provided between the first glass substrate 1 and the second glass substrate 2. The first glass substrate 1 is provided with a through hole 11, the upper surface is provided with a first wiring layer 4, and the lower surface is provided with a third wiring layer 5; the second glass substrate 2 is provided with a through hole 21, and the upper surface is provided with a second wiring layer 6; the bonding layer 3 is provided with an opening 31; the filling of the via 11, the via 21, and the opening 31 with a metal conductive material realizes the up-down interconnection of the first wiring layer 4, the second wiring layer 6, and the third wiring layer 5.
The bonding layer 3 is formed by curing a non-photosensitive composite bonding material, wherein the composition of the composite bonding material comprises 50% of non-photosensitive Polyimide (PI) and 50% of glass fiber, and the non-photosensitive Polyimide (PI) and the glass fiber are mixed to form a sheet. The glass fiber is silicate glass fiber with the diameter of 0.1-0.3 μm. The glass substrate is silicate glass. Glass is used as a substrate, and compared with a silicon substrate, the silicon substrate has adjustable CTE, so that the interconnection yield and reliability are improved; the dielectric constant of the glass is only 1/3 of that of a silicon material, so that the substrate loss and parasitic effect are greatly reduced, and the integrity of a transmission signal can be effectively improved; compared with the silicon substrate packaging process, the TGV does not need to deposit a silicon oxide insulating layer on the inner wall, and the process is simpler.
Referring to fig. 2, the process for manufacturing the above-described multilayered glass substrate is specifically described below.
Step 1, firstly, providing a first glass substrate 1, wherein the thickness of the first glass substrate is 500-700 mu m, preparing blind holes 11 'with corresponding apertures on the first glass substrate 1 by a laser-induced chemical etching method, wherein the depth of the blind holes 11' is 120-180 mu m, and filling metal copper or other metal conductive materials in the holes by means of sputtering, photoetching, electroplating, photoresist removing, etching and the like. A surface metal wiring is formed as a first wiring layer 4 on the upper surface of the first glass substrate 1.
Step 2, providing a sheet of a non-photosensitive composite bonding layer material, attaching the sheet to the first wiring layer 4 of the first glass substrate 1 by a roller film or vacuum lamination mode to form a bonding layer 3, pre-curing the bonding layer for 10-30 min at about 110 ℃, and then forming a semi-closed opening 31 penetrating through the bonding layer 3 by laser, wherein the bottom of the opening 31 is exposed out of the first wiring layer 4. The semi-closed opening 31 can be characterized by a gradually increasing diameter from the bottom to the top of the first wiring layer 2, and a smooth and step-free sidewall. The adopted laser pore forming mode is that UV laser is taken as an example, the diameter of a laser spot is about 20 mu m, the pulse number of a single pore is 5000, the single pulse energy is 8uj, long molecular chains of organic materials are broken by high-energy photons in an ultraviolet region to form smaller particles, and the bonding layer 3 is rapidly removed under the condition of pinching by external force to form micropores.
Step 3, providing a second glass substrate 2 with a through hole 21, wherein the thickness of the second glass substrate 2 is 100-150 μm, and the through hole 21 is formed by a process such as laser modification. The second glass substrate 2 is bonded to the bonding layer 3 by wafer level bonding, and baked and cured at 180 ℃ to bring the first glass substrate 1 and the second glass substrate 2 into a permanently bonded state.
And 4, filling copper or other metal conductive materials in the through holes and the openings 31 of the second glass substrate 2 by adopting a sputtering and electroplating mode. A high-precision circuit pattern is formed as the second wiring layer 6 on the upper surface of the second glass substrate 2.
And 5, thinning the lower surface of the first glass substrate 1 by a mechanical grinding mode (firstly coarse grinding and then fine grinding polishing) until the bottom surface of the blind hole 11' is exposed to form a TGV through hole, and completing the third wiring layer 5 on the lower surface of the first glass substrate 1 by sputtering, photoetching, electroplating and other modes, thereby finally realizing the stacking interconnection of the two layers of glass substrates.
And (3) circulating the steps 2-4 for a plurality of times, so that a plurality of layers of conducting circuits can be formed on the glass substrate, and finally, a finished product is formed.
In addition, the method further comprises the steps of covering the surface of the formed multilayer structure with a protective layer such as a passivation layer and opening the protective layer to connect circuits.
In this embodiment, the dielectric constant of the bonding layer is 3.2@10GHz, the loss tangent is 0.009@10GHz, and the insertion loss result of the double-layer glass substrate adopting the composite bonding material is obtained by designing a 10mm length GCPWtoStripine structure: 0.68dB@60GHz. Compared with the LTCC substrate structure adopting the same stripline design structure, the insertion loss result with the length of 6.14mm is 0.87dB@40GHz, so that the design scheme and thought adopted by the embodiment have obvious advantages.
Example 2
The difference between example 2 and example 1 is that: the composite bonding material comprises 40% of Epoxy resin (Epoxy), 20% of glass fiber and 40% of inorganic fiber cyanate, and the cyanate forms a triazine ring structure through a cyanate polymerization reaction, so that lower dielectric loss and dielectric loss are obtained, and the requirements of high-frequency and high-speed signal transmission can be met.
Comparative example 1
Comparative example 1 differs from example 1 in that the bonding layer thereof employs FR-4 epoxy glass laminated board or pp (pre reg, prePreg or referred to as semi-cured resin, prePreg) which brings about a large dielectric constant and loss tangent, resulting in an increase in loss under high frequency signal transmission. Meanwhile, in the comparative example 1, copper powder conductive paste is used for filling and filling the interconnection through hole, copper powder is easy to oxidize in the high-temperature curing process, and the generated copper oxide and cuprous oxide can cause the increase of resistivity and the decrease of conductivity in the long-term use process of the conductive paste, especially in a wet environment.
Comparative example 2
Comparative example 2 differs from example 1 in that the bonding material is a non-photosensitive Polyimide (PI) with no inorganic filler added.
| Dielectric constant Dk | Loss tangent Df | |
| Example 1 | 3.200 | 0.0090@10GHz |
| Example 2 | 3.084 | 0.0060@10GHz |
| Comparative example 1 | 4.500 | 0.0200@10GHz |
| Comparative example 2 | 3.300 | 0.0339@10GHz |
It is apparent from examples and comparative examples that the present invention can achieve low dielectric constant and low loss tangent, i.e., low dielectric loss and low dielectric loss at the same time, by using the composite bonding material, and can meet the requirements of high frequency and high speed signal transmission.
The above embodiments are only used to further illustrate a multi-layer glass substrate and a manufacturing process using a composite bonding material, but the present invention is not limited to the embodiments, and any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention falls within the scope of the technical solution of the present invention.
Claims (10)
1. A multi-layer glass substrate using a composite bonding material, characterized in that: comprises at least two layers of glass substrates and a bonding layer arranged between the two layers of glass substrates; the surface of the glass substrate is provided with a wiring layer, the glass substrate is provided with a through hole penetrating up and down, the bonding layer is provided with an opening, and the through hole and the opening are filled with metal conductive materials and are connected up and down together with the surface wiring layer; the bonding layer is formed by solidifying a non-photosensitive composite bonding material, the non-photosensitive composite bonding material is composed of 40% -50% of organic components and 50% -60% of inorganic fillers, and the organic components comprise at least one of non-photosensitive polyimide, polyamide fibers and epoxy resin; the inorganic filler comprises at least one of cyanate, glass, silicon and silicon oxide, and is micropowder or fiber.
2. The multi-layered glass substrate using a composite bonding material according to claim 1, wherein: the thickness of the bonding layer is 10-100 mu m, and the diameter of the inorganic filler is 0.1-0.3 mu m.
3. The multi-layered glass substrate using a composite bonding material according to claim 1, wherein: df of the bonding layer is less than 0.01, dk is less than 3.3.
4. The multi-layered glass substrate using a composite bonding material according to claim 1, wherein: the bonding layer has a coefficient of thermal expansion and a modulus matching those of the glass substrate.
5. A process for producing a multi-layered glass substrate using a composite bonding material according to any one of claims 1 to 4, comprising the steps of:
a) Manufacturing a blind hole with an upward opening on a first glass substrate, filling a metal conductive material in the blind hole, and manufacturing a first wiring layer on the upper surface of the first glass substrate;
b) Forming a bonding layer on the upper surface of the first glass substrate by adopting the non-photosensitive composite bonding material, and forming an opening penetrating through the bonding layer by laser after pre-curing;
c) Bonding a second glass substrate with a through hole penetrating up and down to a bonding layer in a wafer-level bonding mode, and then solidifying the bonding layer;
d) Filling metal conductive materials in the through holes of the second glass substrate and the openings of the bonding layer, and manufacturing a second wiring layer on the upper surface of the second glass substrate;
e) And mechanically thinning the first glass substrate, forming a TGV through hole, and manufacturing a third wiring layer on the lower surface of the first glass substrate.
6. The manufacturing process according to claim 5, wherein: in the step b), the organic component and the inorganic component are mixed according to the proportion to form a non-photosensitive composite bonding material sheet, and the non-photosensitive composite bonding material sheet is attached to the first glass substrate in a roller film attaching or vacuum pressing mode to form a bonding layer.
7. The manufacturing process according to claim 5, wherein: in the step b), the pre-curing temperature is 100-120 ℃; in the step c), the bonding layer is baked and cured at 160-220 ℃.
8. The manufacturing process according to claim 5, wherein: in the step b), the laser is a carbon dioxide laser or an ultraviolet laser, the diameter of the laser spot is 10-40 mu m, the number of single-hole pulses is 2000-10000, and the single-pulse energy is 1 uj-15 uj.
9. The manufacturing process according to claim 5, wherein: the first wiring layer is exposed in the opening, and the diameter of the opening gradually increases from the bottom to the top of the exposed first wiring layer.
10. The manufacturing process according to claim 5, wherein: and c) repeating the steps b) to d), forming a structure of multi-layer glass substrate stack and multi-layer wiring layer up-down conduction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310314714.9A CN116631975A (en) | 2023-03-29 | 2023-03-29 | Multilayer glass substrate adopting composite bonding material and manufacturing process |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310314714.9A CN116631975A (en) | 2023-03-29 | 2023-03-29 | Multilayer glass substrate adopting composite bonding material and manufacturing process |
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| CN116631975A true CN116631975A (en) | 2023-08-22 |
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| CN202310314714.9A Pending CN116631975A (en) | 2023-03-29 | 2023-03-29 | Multilayer glass substrate adopting composite bonding material and manufacturing process |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117976550A (en) * | 2024-03-28 | 2024-05-03 | 深圳市矩阵多元科技有限公司 | Substrate manufacturing method and substrate |
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- 2023-03-29 CN CN202310314714.9A patent/CN116631975A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117976550A (en) * | 2024-03-28 | 2024-05-03 | 深圳市矩阵多元科技有限公司 | Substrate manufacturing method and substrate |
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