CN116627651A - Multi-core system load balancing method and device, electronic equipment and storage medium - Google Patents

Multi-core system load balancing method and device, electronic equipment and storage medium Download PDF

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Publication number
CN116627651A
CN116627651A CN202310617117.3A CN202310617117A CN116627651A CN 116627651 A CN116627651 A CN 116627651A CN 202310617117 A CN202310617117 A CN 202310617117A CN 116627651 A CN116627651 A CN 116627651A
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processor
load
interrupt
task
state
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夏溢
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Deep Blue Automotive Technology Co ltd
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Deep Blue Automotive Technology Co ltd
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Priority to CN202310617117.3A priority Critical patent/CN116627651A/en
Publication of CN116627651A publication Critical patent/CN116627651A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5083—Techniques for rebalancing the load in a distributed system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/505—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the load
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

The invention provides a load balancing method, a device, electronic equipment and a storage medium of a multi-core system, wherein the method comprises the steps of detecting the processing state of each processor in the multi-core system, dividing each processor into an idle processor and a high-load processor based on the processing state, wherein the processing state comprises the idle state and the high-load state, moving a target task with the highest priority in a task queue of the high-load processor to a ready task queue of the idle processor for execution, moving the target task back to the task queue of the high-load processor after the execution of the target task is completed, setting the state of the target task to be in a suspension state so as to balance the load state of the high-load processor, and guaranteeing the safety, the reliability and the stability of an automobile software system through the load balancing method of the multi-core system.

Description

Multi-core system load balancing method and device, electronic equipment and storage medium
Technical Field
The invention relates to the technical field of automobile embedded controller software, in particular to a multi-core system load balancing method, a multi-core system load balancing device, electronic equipment and a storage medium.
Background
With the development trend and trend of the automobile industry, such as intellectualization, networking and electric power, the automobile is gradually transited from mechanical driving to software driving electronic products, the trend of the software-defined automobile is more and more obvious, and under the trend of 'new and fourth' of the automobile, the software, chips, calculation power and the like become more and more important, and the situation is expected to surpass the traditional three parts of an engine, a transmission and a chassis, so that the software-defined automobile is overturned by the traditional automobile value chain. At present, in order to meet the requirements of a software-defined automobile, a chip manufacturer continuously promotes multi-core high-performance and high-power chips, so that the code quantity of automobile software is larger and larger, the complexity of the automobile software is multiplied, and how to optimize the load of an embedded software system of the automobile is one of the problems of increasing attention of the automobile software at present.
The processor of the traditional controller is generally a single-core system, the software functions are very single, under the background, the automobile embedded software system is designed into a foreground and background system for time-sharing task scheduling and interrupt service, the key operation with strong time correlation is ensured by interrupt service, so that the information provided for the interrupt service can not be processed until the background task executes the step of processing the information, the design mode of the software system has two defects, firstly, the real-time performance is greatly reduced, the real-time performance depends on the execution time of the whole system software, and secondly, the execution can not be optimized for certain tasks with high load rate, and the execution can only be sequentially waited for completion.
Under the trend of 'new four' of automobiles, the processor of the controller is developed into a multi-core system, the software functions are increasingly complex, the simple foreground and background software systems can not meet the requirements, and a method for balancing interrupt load of the multi-core processor is disclosed in a patent document with a patent publication number of CN 101354664B.
Disclosure of Invention
In view of the above drawbacks of the related art, the present invention provides a method, an apparatus, an electronic device, and a storage medium for load balancing of a multi-core system, so as to solve the above technical problems.
The load balancing method of the multi-core system comprises the steps of detecting the processing state of each processor in the multi-core system, and dividing each processor into an idle processor and a high-load processor based on the processing state, wherein the processing state comprises the idle state and the high-load state; moving the target task with the highest priority in the task queue of the high-load processor to the ready task queue of the idle processor for execution; and after the target task is executed, moving the target task back to a task queue of the high-load processor, and setting the state of the target task to a suspended state so as to balance the load state of the high-load processor.
In an embodiment of the present invention, moving the highest priority target task in the task queue of the load processor to the ready task queue of the current processor includes: and setting the processor belonging to the task control information of the target task as an idle processor, wherein the task control information at least comprises an entry function address of the target task, the processor belonging to the target task and a task state.
In one embodiment of the present invention, detecting a processing state of each processor in a multi-core system, and dividing each processor into an idle processor and a high-load processor based on the processing state includes: and if the idle task exists in the current processor, determining the current processor as the idle processor.
In one embodiment of the present invention, detecting a processing state of each processor in a multi-core system, and dividing each processor into an idle processor and a high-load processor based on the processing state includes: and if the task waiting to be executed in the task queue in the current processor is detected, determining the current processor as a high-load processor.
In an embodiment of the present invention, the method for balancing load of a multi-core system further includes: calculating interrupt execution time of each processor in the multi-core system at intervals of a preset time period, and obtaining interrupt load rate based on the interrupt execution time; and if the interrupt load rate exceeds a preset interrupt interval, reallocating interrupt service based on the interrupt load rate of each processor.
In an embodiment of the present invention, obtaining the interrupt load rate based on the interrupt execution time includes: collecting the execution times of the interrupt service function of the processor in the preset time period; obtaining total interrupt time according to the interrupt service function execution times and the interrupt execution time; and obtaining the interrupt load rate based on the interrupt total time and the preset time period.
In one embodiment of the invention, reallocating interrupt service based on the interrupt load rate of each of the processors comprises: reconfiguring an interrupt vector table of each processor in the multi-core system to redistribute interrupt services, wherein each processor has one interrupt vector table, and the interrupt vector table is used for configuring the interrupt services of the processor.
The embodiment of the invention also provides a load balancing device of the multi-core system, which comprises a detection module, a control module and a load balancing module, wherein the detection module is used for detecting the processing state of each processor in the multi-core system, and dividing each processor into an idle processor and a high-load processor based on the processing state, and the processing state comprises the idle state and the high-load state; the allocation module is used for moving the target task with the highest priority in the task queue of the high-load processor to the ready task queue of the idle processor for execution; and the balancing module is used for moving the target task back to the task queue of the high-load processor after the target task is executed, and setting the state of the target task to be a suspended state so as to balance the load state of the high-load processor.
Embodiments of the present invention also provide an electronic device including one or more processors; and the storage device is used for storing one or more programs, and when the one or more programs are executed by the one or more processors, the electronic equipment realizes the load balancing method of the multi-core system according to any one of the embodiments.
Embodiments of the present invention also provide a computer-readable storage medium having stored thereon a computer program which, when executed by a processor of a computer, causes the computer to perform the method for load balancing a multi-core system according to any of the embodiments above.
The invention has the beneficial effects that: the method comprises the steps of detecting the processing states of all processors in a multi-core system, dividing the processors into idle processors and high-load processors based on the processing states, wherein the processing states comprise the idle states and the high-load states, moving a target task with the highest priority in a task queue of the high-load processor to a ready task queue of the idle processor for execution, moving the target task back to the task queue of the high-load processor after the target task is executed, setting the state of the target task to be in a suspended state so as to balance the load state of the high-load processor, and guaranteeing the safety, the reliability and the stability of the functions of an automobile software system through the multi-core system load balancing method.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. It is evident that the drawings in the following description are only some embodiments of the present invention and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art. In the drawings:
FIG. 1 is a schematic diagram of a multi-core system load balancing system shown in an exemplary embodiment of the invention;
FIG. 2 is a flow chart of a method for load balancing of a multi-core system according to an exemplary embodiment of the invention;
FIG. 3 is a schematic diagram of a task load balancing process flow shown in an exemplary embodiment of the invention;
FIG. 4 is an inter-core task migration diagram illustrating an exemplary embodiment of the present invention;
FIG. 5 is a load occupancy diagram illustrating non-task load balancing in accordance with an exemplary embodiment of the present invention;
FIG. 6 is a load occupancy diagram illustrating task load balancing in accordance with an exemplary embodiment of the present invention;
FIG. 7 is a flow chart illustrating a process for interrupt service load balancing in accordance with an exemplary embodiment of the present invention;
FIG. 8 is an interrupt service configuration reassignment diagram illustrating an exemplary embodiment of the present invention;
FIG. 9 is a load occupancy diagram illustrating non-interrupt service load balancing in accordance with an exemplary embodiment of the present invention;
FIG. 10 is a load occupancy diagram illustrating load balancing for interrupt service in accordance with an exemplary embodiment of the present invention;
FIG. 11 is a block diagram of a multi-core system load balancing apparatus shown in an exemplary embodiment of the invention;
fig. 12 shows a schematic diagram of a computer system suitable for use in implementing an embodiment of the invention.
Detailed Description
Further advantages and effects of the present invention will become readily apparent to those skilled in the art from the disclosure herein, by referring to the accompanying drawings and the preferred embodiments. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be understood that the preferred embodiments are presented by way of illustration only and not by way of limitation.
It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In the following description, numerous details are set forth in order to provide a more thorough explanation of embodiments of the present invention, it will be apparent, however, to one skilled in the art that embodiments of the present invention may be practiced without these specific details, in other embodiments, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the embodiments of the present invention.
Firstly, it should be noted that, in the existing OSEKOS and autoros software system designs, priority tasks are generally statically assigned to each core, and this software system design manner may firstly have a situation that the task number of each core is unevenly assigned, and secondly, even if the task number of each core is uniformly assigned, the running load of each task is inconsistent, which also causes the load of each core to be uneven.
Referring to fig. 1, fig. 1 is a schematic diagram of a load balancing system of a multi-core system according to an exemplary embodiment of the present invention, where the load balancing system of the multi-core system includes a first processor 101, a second processor 102 and a third processor 103, this embodiment is merely an example of a load balancing system of the multi-core system, the system may further include more processors, and the number of the processors does not limit the scope of the present invention.
Detecting the processing states of a first processor 101, a second processor 102 and a third processor 103 in the multi-core system, dividing the first processor 101, the second processor 102 and the third processor 103 into idle processors and high-load processors based on the processing states, wherein the processing states comprise the idle states and the high-load states, determining the current processor as the idle processors if idle tasks exist in the current processor, determining the current processor as the high-load processor if tasks wait for execution in a task queue in the current processor, determining the first processor as the high-load processor in the embodiment, determining the second processor 102 and the third processor 103 as the idle processors, and moving a target task with the highest priority in the task queue of the high-load processor to a ready task queue of the idle processor for execution, wherein the target task is the ready task with the highest priority in the task queue of the high-load processor.
When the target task is completed, the target task is moved back to the task queue of the high-load processor, and the state of the target task is set to be in a suspended state and is run in the high-load processor, so that the load states among the first processor 101, the second processor 102 and the third processor 103 are balanced.
As shown in fig. 2, in an exemplary embodiment, the load balancing method of the multi-core system at least includes steps S210 to S230, which are described in detail as follows:
in step S210, the processing states of the processors in the multi-core system are detected, and the processors are divided into idle processors and high-load processors based on the processing states, where the processing states include an idle state and a high-load state.
In one embodiment of the invention, the current processor is determined to be an idle processor if it is detected that the current processor has an idle task. And if the task in the current processor is detected to wait for execution in the task queue, determining the current processor as a high-load processor.
Step S220, the target task with the highest priority in the task queue of the high-load processor is moved to the ready task queue of the idle processor to be executed.
And determining the ready-state task to be executed with the highest priority in the high-load processor queue to be executed as a target task, and moving the target task to the ready-state task queue of the idle processor for execution.
In one embodiment of the present invention, the processor belonging to the task control information of the target task is set as an idle processor, and the task control information includes at least an entry function address of the target task, the processor belonging to the target task, and a task state.
In step S230, after the execution of the ready task is completed, the ready task is moved back to the task queue of the high-load processor, and the state of the target task is set to the suspended state, so as to balance the load state of the high-load processor.
In one embodiment of the invention, the load balancing method of the multi-core system further comprises the steps of calculating interrupt execution time of each processor in the multi-core system at intervals of a preset time period, and obtaining interrupt load rate based on the interrupt execution time; and if the interrupt load rate exceeds the preset interrupt interval, reallocating interrupt service based on the interrupt load rate of each processor.
In one embodiment of the invention, the number of times of executing the interrupt service function of the processor in a preset time period is collected; obtaining total interrupt time according to the execution times and the interrupt execution time of the interrupt service function; and obtaining the interrupt load rate based on the total interrupt time and the preset time period.
Referring to fig. 3, fig. 3 is a schematic diagram of a task load balancing process shown in an exemplary embodiment of the present invention, in this process, whether a current CPU (central processing unit) is idle is first detected, if the current CPU is in an idle state, the CPU is determined to be an idle processor, balancing processing is triggered, whether other CPUs have ready-state tasks to be executed is detected, if there is a ready-state task to be executed, the CPU is determined to be a high-load processor, a highest-priority ready-state task to be executed in a queue to be executed by the high-load processor is determined to be a target task, and the target task is moved to a ready task queue of the idle processor for execution. After the execution is completed, the target task is moved to the original CPU scheduling queue, namely, the target task is moved back to the high-load processor, and the execution state of the target task is set to be in a suspended state, so that the task load balancing processing is completed.
In one embodiment of the present invention, each core of the multi-core software system is allocated an IDLE (IDLE) task, and typically, the IDLE task is used to perform some tasks such as CPU load rate calculation and resource release. In the invention, the idle task is utilized to carry out load balancing processing, when the idle task arrives, the current CPU is in an idle state, and then the CPU can be inquired whether other CPUs are in a high-load state or not at the moment (at the moment, the task waits to be executed in a task queue). If a certain CPU is in a high-load state, load balancing processing is executed, and inter-core task migration occurs.
Referring to fig. 4, fig. 4 is an inter-Core task migration diagram according to an exemplary embodiment of the present invention, where Core0 is a high-load processor, tasks with multiple priorities in Core0 are being executed, where the highest priority is priority 0, and there are task1 and task5 under priority 0, where task1 is being executed in Core0, but task5 is in a state to be executed, then task5 is determined as a target task, presence of idle processor Core0 is detected, and target task5 is moved to a ready task queue in idle processor Core0 for execution, thereby reducing processing pressure of high-load processor Core 0.
In one embodiment of the present invention, each task has its own TCI (task control information), including the entry function address of the task, its own core, task state, etc., and each core has its own os_cfg_i (system configuration information), including the priority ready task queue, spin lock, etc. Setting the core to which the TCI information belongs as a current idle CPU, the current CPU can move the target task with the highest priority in a task queue in a high load state to a ready task queue of the current CPU for execution, after the task is executed, moving the task back to the high load CPU task queue, setting the state of the task to a suspended state, setting the core to which the task belongs back to the original CPU core, adding the task to the original CPU core suspended queue, and uniformly scheduling by the high load CPU again. At this time, some CPUs are not in a high-load state all the time, and some CPUs are in an idle and unobjectionable state, so that the aim of balancing the load of the whole automobile embedded software system is fulfilled.
Referring to fig. 5 and 6, fig. 5 is a load occupancy diagram illustrating non-task load balancing according to an exemplary embodiment of the present invention, and fig. 6 is a load occupancy diagram illustrating task load balancing according to an exemplary embodiment of the present invention. The load occupancy (loadrate) of CPU0, CPU1, and CPU2 in both cases is illustrated in fig. 5 and 6, respectively. In fig. 5, the CPU0 is a high-load processor, and the task1 and the task2 are both in ready state to execute tasks, but in fig. 5, task load balancing is not performed, so the load occupation (loadrate) of the CPU0 of the high-load processor in fig. 5 is greater than 1, where the load of the CPU0 in the system is higher, but the loads of the CPU1 and the CPU0 are both lower, and where the load occupation of the system is uneven. In fig. 6, task1 and task2 are respectively moved to idle processor CPU1 and idle processor CPU2 for execution, and at this time, the load occupation of high load processor CPU0 is reduced, so that the load occupation (loadrate) of all three processors is less than 1, and the CPU load is balanced.
Referring to fig. 7, fig. 7 is a flowchart illustrating an interrupt service load balancing process according to an exemplary embodiment of the present invention, in this process, 1000ms is preferably set as a preset time period, interrupt service load balancing processing is triggered every 1000ms, interrupt load rates of each processor core are counted, whether interrupt service is redistributed to each CPU is determined according to the interrupt load rate, if the interrupt load rate exceeds a preset interrupt interval, an interrupt policy is executed, if the interrupt load rate does not exceed the preset interrupt interval, the result of the counted load rate is cleared, and the cycle of triggering interrupt service load balancing processing every 1000ms is re-entered.
In one embodiment of the present invention, interrupt balancing is periodically performed at a timing of 1000ms, and the actual execution time of all interrupts of each CPU core is calculated by using an interrupt execution time function provided by the OS, so that the interrupt load rate of each CPU core is counted, and the interrupt load rate can be calculated by how many times the interrupt service function and the interrupt execution time are performed in 1000 ms.
Referring to fig. 8, fig. 8 is an interrupt service configuration reassignment diagram according to an exemplary embodiment of the present invention, when a deviation occurs in interrupt load rate of each core, then interrupt service (irq) on each core is reassigned according to load conditions, each CPU core maintains an INTCTABLE (interrupt control vector table), and then the interrupt vector is reassigned to be expressed for interrupt reassignment purposes. At this time, there will be no CPU in a high load state all the time because the interrupt load is too high for a period of time, and some CPU is in an idle state, as shown in fig. 9, fig. 9 is a load occupation diagram of an exemplary embodiment of the present invention, in which no interrupt service load balancing is performed, because the interrupt priority is higher than the task, the execution duration of the final task will be affected by the interrupt load, resulting in a higher CPU0 core load, a lower CPU1 and CPU2 core load, and finally, the overall software system will also have poor performance, and the load balancing purpose of the overall embedded software system is achieved through the interrupt service configuration redistribution, the final load optimization is shown in fig. 10, and fig. 10 is a load occupation diagram of the interrupt service load balancing performed in an exemplary embodiment of the present invention, in which all the CPU interrupt loads reach the balance.
FIG. 11 is a block diagram of a multi-core system load balancing apparatus according to an exemplary embodiment of the present invention, as shown in FIG. 11, the exemplary multi-core system load balancing apparatus includes: a detection module 1101, an allocation module 1102 and an equalization module 1103.
The detection module 1101 is configured to detect a processing state of each processor in the multi-core system, and divide each processor into an idle processor and a high-load processor based on the processing state, where the processing state includes an idle state and a high-load state;
an allocation module 1102, configured to move a target task with a highest priority in a task queue of a high-load processor to a ready task queue of an idle processor for execution;
and the balancing module 1103 is configured to move the target task back to the task queue of the high-load processor after the target task is executed, and set the state of the target task to a suspended state, so as to balance the load state of the high-load processor.
It should be noted that, the multi-core system load balancing device provided in the foregoing embodiment and the multi-core system load balancing method provided in the foregoing embodiment belong to the same concept, and a specific manner in which each module and unit perform an operation has been described in detail in the method embodiment, which is not described herein again. In practical application, the load balancing device for a multi-core system provided in the above embodiment may distribute the functions to be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above, which is not limited herein.
The embodiment of the invention also provides electronic equipment, which comprises: one or more processors; and the storage device is used for storing one or more programs, and when the one or more programs are executed by the one or more processors, the electronic equipment realizes the multi-core system load balancing method provided in the various embodiments.
Fig. 12 shows a schematic diagram of a computer system suitable for use in implementing an embodiment of the invention. It should be noted that, the computer system 1200 of the electronic device shown in fig. 12 is only an example, and should not impose any limitation on the functions and the application scope of the embodiments of the present invention.
As shown in fig. 12, the computer system 1200 includes a central processing unit (CentralProcessingUnit, CPU) 1201, which can perform various appropriate actions and processes, such as performing the methods described in the above embodiments, according to a program stored in a Read-only memory (ROM) 1202 or a program loaded from a storage section 1208 into a random access memory (RandomAccessMemory, RAM) 1203. In the RAM 1203, various programs and data required for the system operation are also stored. The CPU1201, ROM1202, and RAM 1203 are connected to each other through a bus 1204. An Input/Output (I/O) interface 1205 is also connected to bus 1204.
The following components are connected to the I/O interface 1205: an input section 1206 including a keyboard, a mouse, and the like; an output portion 1207 including a cathode ray tube (CathodeRayTube, CRT), a liquid crystal display (LiquidCrystalDisplay, LCD), and the like, a speaker, and the like; a storage section 1208 including a hard disk or the like; and a communication section 1209 including a network interface card such as a LAN (local area network) card, a modem, or the like. The communication section 1209 performs communication processing via a network such as the internet. The drive 1210 is also connected to the I/O interface 1205 as needed. A removable medium 1211 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is installed as needed on the drive 1210 so that a computer program read out therefrom is installed into the storage section 1208 as needed.
In particular, according to embodiments of the present invention, the processes described above with reference to flowcharts may be implemented as computer software programs. For example, embodiments of the present invention include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising a computer program for performing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via the communication portion 1209, and/or installed from the removable media 1211. When executed by a Central Processing Unit (CPU) 1201, performs the various functions defined in the system of the present invention.
It should be noted that, the computer readable medium shown in the embodiments of the present invention may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable storage medium may be, for example, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (ErasableProgrammableReadOnlyMemory, EPROM), a flash memory, an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the present invention, a computer-readable signal medium may comprise a data signal propagated in baseband or as part of a carrier wave, with a computer-readable computer program embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. A computer program embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the foregoing.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. Where each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The units involved in the embodiments of the present invention may be implemented by software, or may be implemented by hardware, and the described units may also be provided in a processor. Wherein the names of the units do not constitute a limitation of the units themselves in some cases.
Another aspect of the invention also provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor of a computer, causes the computer to perform a method of load balancing a multi-core system as described above. The computer-readable storage medium may be included in the electronic device described in the above embodiment or may exist alone without being incorporated in the electronic device.
Another aspect of the invention also provides a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the multi-core system load balancing method provided in the above embodiments.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. It is therefore intended that all equivalent modifications and changes made by those skilled in the art without departing from the spirit and technical spirit of the present invention shall be covered by the appended claims.

Claims (10)

1. The multi-core system load balancing method is characterized by comprising the following steps of:
detecting processing states of all processors in the multi-core system, and dividing the processors into idle processors and high-load processors based on the processing states, wherein the processing states comprise the idle states and the high-load states;
moving the target task with the highest priority in the task queue of the high-load processor to the ready task queue of the idle processor for execution;
and after the target task is executed, moving the target task back to a task queue of the high-load processor, and setting the state of the target task to a suspended state so as to balance the load state of the high-load processor.
2. The method of claim 1, wherein moving the highest priority target task in the task queue of the load processor into the ready task queue of the current processor comprises:
and setting the processor belonging to the task control information of the target task as an idle processor, wherein the task control information at least comprises an entry function address of the target task, the processor belonging to the target task and a task state.
3. The method of load balancing of a multi-core system of claim 1, wherein detecting a processing state of each processor in the multi-core system, and dividing each processor into an idle processor and a high-load processor based on the processing state comprises:
and if the idle task exists in the current processor, determining the current processor as the idle processor.
4. The method of load balancing of a multi-core system of claim 1, wherein detecting a processing state of each processor in the multi-core system, and dividing each processor into an idle processor and a high-load processor based on the processing state comprises:
and if the task waiting to be executed in the task queue in the current processor is detected, determining the current processor as a high-load processor.
5. The multi-core system load balancing method of claim 1, further comprising:
calculating interrupt execution time of each processor in the multi-core system at intervals of a preset time period, and obtaining interrupt load rate based on the interrupt execution time;
and if the interrupt load rate exceeds a preset interrupt interval, reallocating interrupt service based on the interrupt load rate of each processor.
6. The method of claim 5, wherein deriving an interrupt load rate based on the interrupt execution time comprises:
collecting the execution times of the interrupt service function of the processor in the preset time period;
obtaining total interrupt time according to the interrupt service function execution times and the interrupt execution time;
and obtaining the interrupt load rate based on the interrupt total time and the preset time period.
7. The multi-core system load balancing method of claim 5, wherein reallocating interrupt services based on the interrupt load rate of each of the processors comprises:
reconfiguring an interrupt vector table of each processor in the multi-core system to redistribute interrupt services, wherein each processor has one interrupt vector table, and the interrupt vector table is used for configuring the interrupt services of the processor.
8. The utility model provides a multicore system load balancing device which characterized in that, multicore system load balancing device includes:
the detection module is used for detecting the processing state of each processor in the multi-core system, and dividing each processor into an idle processor and a high-load processor based on the processing state, wherein the processing state comprises the idle state and the high-load state;
the allocation module is used for moving the target task with the highest priority in the task queue of the high-load processor to the ready task queue of the idle processor for execution;
and the balancing module is used for moving the target task back to the task queue of the high-load processor after the target task is executed, and setting the state of the target task to be a suspended state so as to balance the load state of the high-load processor.
9. An electronic device, the electronic device comprising:
one or more processors;
storage means for storing one or more programs that, when executed by the one or more processors, cause the electronic device to implement the multi-core system load balancing method of any of claims 1-7.
10. A computer-readable storage medium, having stored thereon a computer program which, when executed by a processor of a computer, causes the computer to perform the multi-core system load balancing method of any of claims 1 to 7.
CN202310617117.3A 2023-05-29 2023-05-29 Multi-core system load balancing method and device, electronic equipment and storage medium Pending CN116627651A (en)

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