CN116627463A - Chip upgrading method, device, equipment and medium - Google Patents
Chip upgrading method, device, equipment and medium Download PDFInfo
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- CN116627463A CN116627463A CN202310605306.9A CN202310605306A CN116627463A CN 116627463 A CN116627463 A CN 116627463A CN 202310605306 A CN202310605306 A CN 202310605306A CN 116627463 A CN116627463 A CN 116627463A
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Abstract
The application discloses a chip upgrading method, a device, equipment and a medium, which relate to the field of computer servers, and the method is applied to complex programmable logic devices which are respectively connected with a baseboard management controller and a preset external interface in advance, and comprises the following steps: when a target command for opening a target path between the complex programmable logic device and a target update chip, which is sent by a baseboard management controller, is received, opening the target path; the target updating chip is configured on a target board card, and the target board card is one of a plurality of board cards which are connected with the complex programmable logic device in advance; and receiving a target update file sent by a preset debugging tool through the preset external interface, and sending the target update file to the target update chip based on the target path so as to update the target update chip. The application can upgrade and manage the retimer chip of the whole server without disassembling the machine.
Description
Technical Field
The present application relates to the field of computer servers, and in particular, to a method, an apparatus, a device, and a medium for upgrading a chip.
Background
PCIe (i.e., PCI-Express, peripheral component interconnect Express, high-speed serial computer expansion bus standard) Retimer chips mainly solve the problems of uneven signal timing, large loss, poor integrity, etc. when a data center server transmits data at high speed and long distance. With the increasing complexity of server architecture, for servers with complex configuration, such as large rack blade servers, PCIE smart cards and other devices that can reach the chassis port only through multiple board card switching are increasingly required, and these complex configurations are particularly important for field application when the actual application scenario changes the configuration.
In the existing scheme design, PCIE resource allocation corresponding to FW (Firmware) version of the re-timer is fixed, a multi-board device is provided in the server device, and an I2C (i.e., inter-Integrated Circuit, integrated circuit bus) Header is added to each board for use in upgrading the re-timer version by using upgrade-testing tools of the re-timer manufacturer, and several headers are provided for several boards, so that the whole server must be disassembled during upgrading, and the upgrade-testing tools of the re-timer manufacturer are connected to each board for upgrade-testing. In this way, the requirement for the use of the server requiring flexible configuration is high, if a plurality of boards in one configuration contain retimer chips, if each retimer chip needs to be upgraded, tools need to be connected to each board in turn, and correct I2C Header PIN (Personal identification number ) sequence needs to be checked, which may cause other problems such as improper assembly during disassembly and assembly. The development and adjustment time is wasted, and the time and effort are wasted for the occasion of changing the configuration.
From the above, how to avoid the complicated chip upgrading process in the chip upgrading process is a problem to be solved in the field.
Disclosure of Invention
In view of the above, the present application aims to provide a method, an apparatus, a device and a medium for upgrading a chip, which can upgrade and manage a retimer chip of an entire server without disassembling the device. The specific scheme is as follows:
in a first aspect, the present application discloses a chip upgrade method applied to a complex programmable logic device which is connected with a baseboard management controller and a preset external interface in advance, comprising:
when a target command for opening a target path between the complex programmable logic device and a target update chip, which is sent by a baseboard management controller, is received, opening the target path; the target updating chip is configured on a target board card, and the target board card is one of a plurality of board cards which are connected with the complex programmable logic device in advance;
and receiving a target update file sent by a preset debugging tool through the preset external interface, and sending the target update file to the target update chip based on the target path so as to update the target update chip.
Optionally, the complex programmable logic device establishes a first communication link with the baseboard management controller, establishes a second communication link with the preset external interface, and opens the target path when receiving a target command sent by the baseboard management controller for opening the target path between the complex programmable logic device and the target update chip, including:
when a target command which is sent by the baseboard management controller through the first communication link and is used for opening a target channel between the complex programmable logic device and a target updating chip is received, opening the target channel;
correspondingly, the receiving the target update file sent by the preset debugging tool through the preset external interface includes:
and receiving a target update file sent by a preset debugging tool through the preset external interface through the second communication link.
Optionally, the first communication link and the second communication link are both integrated circuit bus links.
Optionally, when receiving a target command sent by the baseboard management controller for opening a target path between the complex programmable logic device and a target update chip, opening the target path includes:
after receiving a chip updating instruction which is sent by a preset debugging tool through the preset external interface and is aimed at a target chip through a third communication link, a target command which is sent and used for opening a target channel between the complex programmable logic device and the target updating chip is received by the baseboard management controller, and then the target channel is opened; the third communication link is a link pre-established between the baseboard management controller and the preset external interface.
Optionally, the third communication link is a link constructed based on a universal asynchronous receiver transmitter.
In a second aspect, the present application discloses a chip upgrade method applied to a baseboard management controller connected with a complex programmable logic device, comprising:
sending a target command for opening a target path between the complex programmable logic device and a target update chip to the complex programmable logic device, so that the complex programmable logic device opens the target path and sends a target update file to the target update core based on the target path after receiving the target update file sent by a preset debugging tool through the preset external interface to update the target update chip;
the complex programmable logic device is connected with a preset external interface in advance, the target updating chip is configured on a target board card, and the target board card is one of a plurality of board cards which are connected with the complex programmable logic device in advance.
Optionally, the sending, to the complex programmable logic device, a target command for opening a target path between the complex programmable logic device and a target update chip includes:
when a chip updating instruction, which is sent by a preset debugging tool through the preset external interface and is aimed at a target chip on a target board, is received through a third communication link, determining a chip address corresponding to the target chip from a first register used for recording board information and a second register used for recording chip address information in the complex programmable logic device based on the chip updating instruction; wherein, the third communication link is a link pre-established between the baseboard management controller and the preset external interface;
a target command is sent to the complex programmable logic device to open a target path between the complex programmable logic device and the target chip address.
In a third aspect, the present application discloses a chip upgrade apparatus, applied to a complex programmable logic device that is connected to a baseboard management controller and a preset external interface in advance, comprising:
the access switching module is used for opening the target access when receiving a target command which is sent by the baseboard management controller and used for opening the target access between the complex programmable logic device and the target updating chip; the target updating chip is configured on a target board card, and the target board card is one of a plurality of board cards which are connected with the complex programmable logic device in advance;
the chip updating module is used for receiving a target updating file sent by a preset debugging tool through the preset external interface, and sending the target updating file to the target updating chip based on the target path so as to update the target updating chip.
In a fourth aspect, the present application discloses an electronic device, comprising:
a memory for storing a computer program;
and the processor is used for executing the computer program to realize the chip upgrading method.
In a fifth aspect, the present application discloses a computer storage medium for storing a computer program; wherein the computer program when executed by a processor implements the steps of the previously disclosed chip upgrade method.
After receiving a target command sent by a baseboard management controller and used for opening a target channel between the complex programmable logic device and a target updating chip, a complex programmable logic device which is respectively connected with the baseboard management controller and a preset external interface in advance opens the target channel; the target updating chip is configured on a target board card, and the target board card is one of a plurality of board cards which are connected with the complex programmable logic device in advance; and then the complex programmable logic device receives a target update file sent by a preset debugging tool through the preset external interface, and sends the target update file to the target update chip based on the target path so as to update the target update chip. In this way, the CPLD is connected with all boards, the BMC can realize channel switching of the CPLD, can realize management of information of all boards and version information of the retimer chip in the server, and can upgrade and manage the retimer chip of the whole server without disassembling the machine.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for upgrading a chip provided by the application;
FIG. 2 is a schematic view of an overall structure according to the present application;
FIG. 3 is a flowchart of a specific chip upgrade method according to the present application;
FIG. 4 is a schematic diagram of a chip upgrade apparatus according to the present application;
fig. 5 is a block diagram of an electronic device according to the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the prior art, when the chip is upgraded, the whole server must be disassembled, and the upgrade adjustment tool of the retimer manufacturer is connected to each board card to upgrade the adjustment. The requirement of the server to be flexibly configured on personnel is high, if a plurality of boards are provided with retimer chips in one configuration, if each retimer chip is required to be updated, tools are required to be connected to each board in sequence, and research and development testing time is wasted. In the application, upgrade management is carried out on the retimer chip of the whole server under the condition of not disassembling the machine.
The embodiment of the application discloses a chip upgrading method which is applied to a complex programmable logic device which is respectively connected with a baseboard management controller and a preset external interface in advance, and is described with reference to fig. 1, and the method comprises the following steps:
step S11: when a target command for opening a target path between the complex programmable logic device and a target update chip, which is sent by a baseboard management controller, is received, opening the target path; the target updating chip is configured on a target board card, and the target board card is one of a plurality of board cards which are connected with the complex programmable logic device in advance.
In this embodiment, the complex programmable logic device (i.e., complex Programmable Logic Device, CPLD) is connected to a plurality of boards and is respectively connected to a baseboard management controller (i.e., (Baseboard Management Controller, BMC) and a preset external interface, each board is configured with a chip, and when the chip needs to be updated, an external preset debugging tool sends a command for updating a target updating chip in the target board through the preset external interface so as to update the target updating chip.
In a specific embodiment, an external preset debugging tool sends an instruction for updating a target updating chip in a target board card to a baseboard management controller through the external interface, the baseboard management controller determines the target updating chip after receiving the instruction, and sends a target command for opening a target channel between the complex programmable logic device and the target updating chip to a complex programmable logic device, and the complex programmable logic device opens a corresponding target channel after receiving the target command, so as to realize the transmission of updated files based on the target channel.
It will be appreciated that in this embodiment, the complex programmable logic device and each of the boards respectively establish a corresponding path, and in a preferred embodiment, each path is an integrated circuit bus path. Specifically, a path between a complex programmable logic device and each chip in each of the boards may be established. That is, the complex programmable logic device establishes a path with each chip on each board. When a certain chip in a certain board card is updated, a corresponding passage is opened in advance, and then the subsequent updating file transmission process is completed.
In specific implementation, the complex programmable logic device specifically performs a process of switching the path. That is, when a plurality of chips in a plurality of boards are required to be upgraded, the access is switched before each upgrade, so that flexible configuration of the server is realized.
Step S12: and receiving a target update file sent by a preset debugging tool through the preset external interface, and sending the target update file to the target update chip based on the target path so as to update the target update chip.
It can be understood that in this embodiment, after a target path between the complex programmable device and the target update chip is opened, a target update file sent by a preset debug tool through a preset external interface is received, and the target update file is sent to the target update chip based on the target path, so as to update the target update chip.
In this embodiment, the establishing of the first communication link between the complex programmable logic device and the baseboard management controller and the establishing of the second communication link between the complex programmable logic device and the preset external interface, and when receiving a target command sent by the baseboard management controller for opening a target path between the complex programmable logic device and the target update chip, opening the target path may include: and when a target command which is sent by the baseboard management controller through the first communication link and is used for opening a target channel between the complex programmable logic device and the target updating chip is received, opening the target channel. Correspondingly, the receiving the target update file sent by the preset debug tool through the preset external interface may include: and receiving a target update file sent by a preset debugging tool through the preset external interface through the second communication link. In addition, the first communication link and the second communication link are both integrated circuit bus links, i.e., I2C links.
It should be noted that in this embodiment, when the second communication link is established, an unused idle pin after the DB9 is connected to the BMC may be connected to the complex programmable logic device, so that the connector resources connected to the panel may be fully utilized without changing any configuration.
In this embodiment, when receiving the target command sent by the baseboard management controller to open the target path between the complex programmable logic device and the target update chip, opening the target path may include: after receiving a chip updating instruction which is sent by a preset debugging tool through the preset external interface and is aimed at a target chip through a third communication link, a target command which is sent and used for opening a target channel between the complex programmable logic device and the target updating chip is received by the baseboard management controller, and then the target channel is opened; the third communication link is a link pre-established between the baseboard management controller and the preset external interface. In addition, the third communication link is a link constructed based on a universal asynchronous receiver Transmitter (i.e., universal Asynchronous Receiver/Transmitter, uart).
That is, in this embodiment, after receiving, through the third communication link, a chip update instruction for the target chip sent by the preset debug tool through the preset external interface, the baseboard management controller sends a target command for opening a target path between the complex programmable logic device and the target update chip to the complex programmable logic device.
Fig. 2 is a schematic diagram of an overall structure provided by the present application, in which an I2C link is established between a baseboard management controller and a complex programmable logic device, an I2C link is established between DB9 and the complex programmable logic device, and a uart link is established between the baseboard management controller and DB9, taking a preset external interface as DB9 and a chip as a retimer chip as an example. In a specific implementation scenario, a preset debugging tool sends a chip updating instruction for updating a target updating chip to a baseboard management controller through a uart link by a DB9 interface, the baseboard management controller sends a target command for opening a target channel between a complex programmable logic device and the target updating chip to the complex programmable logic device based on a first communication link pre-established between the baseboard management controller and the complex programmable logic device, and after the complex programmable logic device opens a corresponding target channel, the complex programmable logic device receives a target updating file transmitted by a second communication link by the DB9 interface and sends the target updating file to the target updating chip based on the target channel so as to update the chip.
In this embodiment, after a complex programmable logic device, which is connected to a baseboard management controller and a preset external interface in advance, receives a target command sent by the baseboard management controller and used for opening a target path between the complex programmable logic device and a target update chip, the target path is opened; the target updating chip is configured on a target board card, and the target board card is one of a plurality of board cards which are connected with the complex programmable logic device in advance; and then the complex programmable logic device receives a target update file sent by a preset debugging tool through the preset external interface, and sends the target update file to the target update chip based on the target path so as to update the target update chip. In this way, the CPLD is connected with all boards, the BMC can realize channel switching of the CPLD, can realize management of information of all boards and version information of the retimer chip in the server, and can upgrade and manage the retimer chip of the whole server without disassembling the machine.
Fig. 3 is a schematic diagram of a specific chip upgrade method according to an embodiment of the present application, which is applied to a baseboard management controller connected to a complex programmable logic device. Referring to fig. 3, the method includes:
step S21: and sending a target command for opening a target channel between the complex programmable logic device and a target updating chip to the complex programmable logic device, so that the complex programmable logic device opens the target channel and sends a target updating file to the target updating core based on the target channel after receiving the target updating file sent by a preset debugging tool through the preset external interface, so as to update the target updating chip.
The complex programmable logic device is connected with a preset external interface in advance, the target updating chip is configured on a target board card, and the target board card is one of a plurality of board cards which are connected with the complex programmable logic device in advance.
In this embodiment, the sending, to the complex programmable logic device, a target command for opening a target path between the complex programmable logic device and a target update chip may include: when a chip updating instruction, which is sent by a preset debugging tool through the preset external interface and is aimed at a target chip on a target board, is received through a third communication link, determining a chip address corresponding to the target chip from a first register used for recording board information and a second register used for recording chip address information in the complex programmable logic device based on the chip updating instruction; a target command is sent to the complex programmable logic device to open a target path between the complex programmable logic device and the target chip address.
It will be appreciated that in this embodiment, the complex programmable logic device (as shown in fig. 2) includes a first register for recording board card information and a second register for recording chip address information, so that each chip can be correctly managed and upgraded. After the BMC receives the chip updating instruction, the chip address information of the target updating chip can be determined from the first register and the second register in the CPLD based on the first communication link, and after a target command is generated based on the chip address information, the target command is sent to the complex programmable logic device.
In the prior art architecture, since the versions of the retimer chips are not uniformly managed, the version management of each retimer chip on the board card is single and is recorded only by processing requirements, and other engineers cannot check the versions. In this regard, the present application (as shown in fig. 2) further configures a third register for recording the version information of the chip in the complex programmable logic device, so as to facilitate checking the version and configuration mode of each chip, and solve the problem of chip version management in the prior art.
In the application, the channel switching function based on the I2C channel upgrading re-timer chip is uniformly realized in the CPLD of the main board, so that the channel switching is arranged at a total control position so as to be convenient for controlling each board card. In other embodiments, the CPLD may be replaced with other switching management devices. The CPLD or the switching management device manages the address information and version information of each board card containing the retimer chip and the retimer chip through one register, and then connects the I2C control path to the outside through the rest pins of the DB9, so that the CPLD or the switching management device can be connected to an external debugging tool only by carrying out cable switching of the connector through the DB9 under the condition of not disassembling the machine, and upgrade management is carried out on the retimer chip, thereby achieving the purpose of flexibly configuring the whole server.
Referring to fig. 4, an embodiment of the present application discloses a chip upgrade apparatus, which is applied to a complex programmable logic device that is connected with a baseboard management controller and a preset external interface in advance, and specifically may include:
the access switching module 11 is configured to open a target access when receiving a target command sent by the baseboard management controller for opening the target access between the complex programmable logic device and the target update chip; the target updating chip is configured on a target board card, and the target board card is one of a plurality of board cards which are connected with the complex programmable logic device in advance;
the chip updating module 12 is configured to receive a target updating file sent by a preset debug tool through the preset external interface, and send the target updating file to the target updating chip based on the target path, so as to update the target updating chip.
After receiving a target command sent by a baseboard management controller and used for opening a target channel between the complex programmable logic device and a target updating chip, a complex programmable logic device which is respectively connected with the baseboard management controller and a preset external interface in advance opens the target channel; the target updating chip is configured on a target board card, and the target board card is one of a plurality of board cards which are connected with the complex programmable logic device in advance; and then the complex programmable logic device receives a target update file sent by a preset debugging tool through the preset external interface, and sends the target update file to the target update chip based on the target path so as to update the target update chip. In this way, the CPLD is connected with all boards, the BMC can realize channel switching of the CPLD, can realize management of information of all boards and version information of the retimer chip in the server, and can upgrade and manage the retimer chip of the whole server without disassembling the machine.
Further, the embodiment of the present application further discloses an electronic device, and fig. 5 is a block diagram of an electronic device 20 according to an exemplary embodiment, where the content of the diagram is not to be considered as any limitation on the scope of use of the present application.
Fig. 5 is a schematic structural diagram of an electronic device 20 according to an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a display screen 24, an input-output interface 25, a communication interface 26, and a communication bus 27. The memory 22 is used for storing a computer program, and the computer program is loaded and executed by the processor 21 to implement relevant steps in the chip upgrade method disclosed in any of the foregoing embodiments. In addition, the electronic device 20 in the present embodiment may be specifically an electronic computer.
In this embodiment, the power supply 23 is configured to provide an operating voltage for each hardware device on the electronic device 20; the communication interface 26 can create a data transmission channel between the electronic device 20 and an external device, and the communication protocol to be followed is any communication protocol applicable to the technical solution of the present application, which is not limited herein in detail; the input/output interface 25 is used for acquiring external input data or outputting external output data, and the specific interface type thereof may be selected according to the specific application requirement, which is not limited herein.
The memory 22 may be a carrier for storing resources, such as a read-only memory, a random access memory, a magnetic disk, or an optical disk, and the resources stored thereon may include an operating system 221, a computer program 222, virtual machine data 223, and the virtual machine data 223 may include various data. The storage means may be a temporary storage or a permanent storage.
The operating system 221 is used for managing and controlling various hardware devices on the electronic device 20 and computer programs 222, which may be Windows Server, netware, unix, linux, etc. The computer program 222 may further include a computer program that can be used to perform other specific tasks in addition to the computer program that can be used to perform the chip upgrade method performed by the electronic device 20 disclosed in any of the previous embodiments.
Further, the present application also discloses a computer readable storage medium, where the computer readable storage medium includes a random access Memory (Random Access Memory, RAM), a Memory, a Read-Only Memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a magnetic disk, or any other form of storage medium known in the art. Wherein the computer program, when executed by the processor, implements the chip upgrade method disclosed previously. For specific steps of the method, reference may be made to the corresponding contents disclosed in the foregoing embodiments, and no further description is given here.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, so that the same or similar parts between the embodiments are referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section. Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The chip upgrading method, device, equipment and storage medium provided by the application are described in detail, and specific examples are applied to illustrate the principle and implementation of the application, and the description of the above examples is only used for helping to understand the method and core idea of the application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.
Claims (10)
1. The chip upgrading method is characterized by being applied to a complex programmable logic device which is respectively connected with a baseboard management controller and a preset external interface in advance, and comprising the following steps:
when a target command for opening a target path between the complex programmable logic device and a target update chip, which is sent by a baseboard management controller, is received, opening the target path; the target updating chip is configured on a target board card, and the target board card is one of a plurality of board cards which are connected with the complex programmable logic device in advance;
and receiving a target update file sent by a preset debugging tool through the preset external interface, and sending the target update file to the target update chip based on the target path so as to update the target update chip.
2. The method of claim 1, wherein the complex programmable logic device establishes a first communication link with the baseboard management controller and establishes a second communication link with the preset external interface, and when a target command sent by the baseboard management controller for opening a target path between the complex programmable logic device and a target update chip is received, opening the target path comprises:
when a target command which is sent by the baseboard management controller through the first communication link and is used for opening a target channel between the complex programmable logic device and a target updating chip is received, opening the target channel;
correspondingly, the receiving the target update file sent by the preset debugging tool through the preset external interface includes:
and receiving a target update file sent by a preset debugging tool through the preset external interface through the second communication link.
3. The chip upgrade method of claim 2 wherein the first communication link and the second communication link are both integrated circuit bus links.
4. A method of upgrading a chip according to any one of claims 1 to 3, wherein when receiving a target command sent by a baseboard management controller for opening a target path between the complex programmable logic device and a target update chip, opening the target path comprises:
after receiving a chip updating instruction which is sent by a preset debugging tool through the preset external interface and is aimed at a target chip through a third communication link, a target command which is sent and used for opening a target channel between the complex programmable logic device and the target updating chip is received by the baseboard management controller, and then the target channel is opened; the third communication link is a link pre-established between the baseboard management controller and the preset external interface.
5. The method of claim 4, wherein the third communication link is a link constructed based on a universal asynchronous receiver transmitter.
6. A method of chip upgrade, applied to a baseboard management controller connected to a complex programmable logic device, comprising:
sending a target command for opening a target path between the complex programmable logic device and a target update chip to the complex programmable logic device, so that the complex programmable logic device opens the target path and sends a target update file to the target update core based on the target path after receiving the target update file sent by a preset debugging tool through the preset external interface to update the target update chip;
the complex programmable logic device is connected with a preset external interface in advance, the target updating chip is configured on a target board card, and the target board card is one of a plurality of board cards which are connected with the complex programmable logic device in advance.
7. The chip upgrade method according to claim 6, wherein the sending the target command to the complex programmable logic device for opening a target path between the complex programmable logic device and a target update chip comprises:
when a chip updating instruction, which is sent by a preset debugging tool through the preset external interface and is aimed at a target chip on a target board, is received through a third communication link, determining a chip address corresponding to the target chip from a first register used for recording board information and a second register used for recording chip address information in the complex programmable logic device based on the chip updating instruction; wherein, the third communication link is a link pre-established between the baseboard management controller and the preset external interface;
a target command is sent to the complex programmable logic device to open a target path between the complex programmable logic device and the target chip address.
8. The chip upgrading device is characterized by being applied to a complex programmable logic device which is respectively connected with a baseboard management controller and a preset external interface in advance, and comprising:
the access switching module is used for opening the target access when receiving a target command which is sent by the baseboard management controller and used for opening the target access between the complex programmable logic device and the target updating chip; the target updating chip is configured on a target board card, and the target board card is one of a plurality of board cards which are connected with the complex programmable logic device in advance;
the chip updating module is used for receiving a target updating file sent by a preset debugging tool through the preset external interface, and sending the target updating file to the target updating chip based on the target path so as to update the target updating chip.
9. An electronic device comprising a processor and a memory; wherein the processor, when executing the computer program stored in the memory, implements the chip upgrade method according to any one of claims 1 to 7.
10. A computer-readable storage medium storing a computer program; wherein the computer program, when executed by a processor, implements the chip upgrade method according to any one of claims 1 to 7.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310605306.9A CN116627463A (en) | 2023-05-26 | 2023-05-26 | Chip upgrading method, device, equipment and medium |
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| CN202310605306.9A CN116627463A (en) | 2023-05-26 | 2023-05-26 | Chip upgrading method, device, equipment and medium |
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