CN116627463A - A chip upgrade method, device, equipment and medium - Google Patents

Abstract

The present application discloses a chip upgrade method, device, equipment and medium, which relate to the field of computer servers. The method is applied to complex programmable logic devices connected to the baseboard management controller and the preset external interface in advance, including: when receiving The target command sent by the baseboard management controller for opening the target path between the complex programmable logic device and the target update chip opens the target path; the target update chip is configured on the target board, so The target board is one of the multiple boards pre-connected with the complex programmable logic device; receiving the target update file sent by the preset debugging tool through the preset external interface, and based on the target path The target update file is sent to the target update chip, so as to update the target update chip. The invention can upgrade and manage the retimer chip of the whole server without dismantling the machine.

Description

A chip upgrade method, device, equipment and medium

technical field

The invention relates to the field of computer servers, in particular to a chip upgrading method, device, equipment and medium.

Background technique

PCIe (that is, PCI-Express, peripheral component interconnect express, high-speed serial computer expansion bus standard) Retimer chips mainly solve the problems of uneven signal timing, large loss, and poor integrity when data center servers transmit data at high speed and long distances. As the server architecture becomes more and more complex, for servers with complex configurations, such as large-scale rack blade servers, multiple boards need to be transferred to devices such as PCIE smart cards at the chassis ports, and there is an increasing demand for reimter. For these complicated configurations, when the configuration will be changed in the actual application scenario, it is especially important for the modification of the field application.

In the existing scheme design, the PCIE resource allocation corresponding to the FW (i.e. Firmware, firmware version) version of the retimer is fixed, and there are multiple board devices in the server device, and an I2C (i.e. Inter-Integrated Circuit (integrated circuit bus) header, which is used to connect to the retimer manufacturer’s upgrade debugging tool when upgrading the retimer version. There are several boards with several headers. When upgrading, the entire server must be disassembled, and the retimer manufacturer’s The upgrade debugging tool is connected to each board to upgrade and debug. This method will require higher personnel requirements for the use of servers that require flexible configuration. If there are multiple boards in a configuration that contain retimer chips, if each retimer chip needs to be upgraded, the tools need to be connected in turn. To each board, it is necessary to check the correct I2C Header PIN (Personal identification number, personal identification number) sequence, which may also cause other problems such as improper assembly during disassembly and installation. It is a waste of research and development and commissioning time, and it is very time-consuming and labor-intensive for the occasion of changing the configuration.

It can be seen from the above that, in the process of chip upgrading, how to avoid the complicated situation of the chip upgrading process is a problem to be solved in this field.

Contents of the invention

In view of this, the purpose of the present invention is to provide a chip upgrade method, device, equipment and medium, which can upgrade and manage the retimer chip of the entire server without dismantling the machine. The specific plan is as follows:

In the first aspect, the present application discloses a method for upgrading a chip, which is applied to complex programmable logic devices that are respectively connected to a baseboard management controller and a preset external interface in advance, including:

When receiving the target command sent by the baseboard management controller for opening the target path between the complex programmable logic device and the target update chip, open the target path; the target update chip is configured on the target board Above, the target board is one of the multiple boards pre-connected with the complex programmable logic device;

receiving a target update file sent by a preset debugging tool through the preset external interface, and sending the target update file to the target update chip based on the target path, so as to update the target update chip.

Optionally, the complex programmable logic device establishes a first communication link with the baseboard management controller, and establishes a second communication link with the preset external interface, and when receiving the baseboard management controller The target command sent for opening the target path between the complex programmable logic device and the target update chip, then opening the target path includes:

Opening the target path when a target command for opening the target path between the complex programmable logic device and the target update chip sent by the baseboard management controller through the first communication link is received;

Correspondingly, the receiving the target update file sent by the preset debugging tool through the preset external interface includes:

The target update file sent by the preset debugging tool through the preset external interface is received through the second communication link.

Optionally, both the first communication link and the second communication link are integrated circuit bus links.

Optionally, when receiving the target command sent by the baseboard management controller for opening the target path between the complex programmable logic device and the target update chip, opening the target path includes:

After the baseboard management controller receives the chip update instruction for the target chip sent by the preset debugging tool through the preset external interface through the third communication link, the instruction sent to open the complex programmable logic device and A target command for updating a target path between chips opens the target path; wherein, the third communication link is a pre-established link between the baseboard management controller and the preset external interface.

Optionally, the third communication link is a link constructed based on a Universal Asynchronous Receiver Transmitter.

In the second aspect, the present application discloses a chip upgrade method, which is applied to a baseboard management controller connected to a complex programmable logic device, including:

Sending a target command for opening a target path between the complex programmable logic device and a target update chip to the complex programmable logic device, so that the complex programmable logic device opens the target path and receives a preset After the target update file is sent by the debugging tool through the preset external interface, based on the target path, the target update file is sent to the target update core to update the target update chip;

Wherein, the complex programmable logic device is pre-connected to a preset external interface, and the target update chip is configured on a target board, and the target board is a plurality of boards that are pre-connected to the complex programmable logic device A piece of the card.

Optionally, the sending a target command for opening a target path between the complex programmable logic device and the target update chip to the complex programmable logic device includes:

When receiving the chip update instruction for the target chip on the target board sent by the preset debugging tool through the preset external interface through the third communication link, then based on the chip update instruction, from the complex programmable logic device The chip address corresponding to the target chip is determined in the first register for recording board information and the second register for recording chip address information; wherein, the third communication link is the baseboard management controller A pre-established link with the preset external interface;

A target command for opening a target path between the complex programmable logic device and the target chip address is sent to the complex programmable logic device.

In a third aspect, the present application discloses a chip upgrade device, which is applied to complex programmable logic devices that are pre-connected to a baseboard management controller and a preset external interface, including:

The path switching module is configured to open the target path when receiving the target command sent by the baseboard management controller for opening the target path between the complex programmable logic device and the target update chip; the target update chip configured on the target board, the target board being one of the multiple boards pre-connected to the complex programmable logic device;

A chip update module, configured to receive the target update file sent by the preset debugging tool through the preset external interface, and send the target update file to the target update chip based on the target path, so as to update the target The chip is updated.

In a fourth aspect, the present application discloses an electronic device, including:

memory for storing computer programs;

A processor, configured to execute the computer program, so as to implement the aforementioned chip upgrade method.

In a fifth aspect, the present application discloses a computer storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the steps of the chip upgrade method disclosed above are implemented.

In this application, the complex programmable logic device connected to the baseboard management controller and the preset external interface in advance respectively receives the target for opening the target channel between the complex programmable logic device and the target update chip sent by the baseboard management controller. After the command, the target path is opened; the target update chip is configured on the target board, and the target board is one of the multiple boards connected with the complex programmable logic device in advance; then complex The programmable logic device receives the target update file sent by the preset debugging tool through the preset external interface, and sends the target update file to the target update chip based on the target path, so as to perform the target update chip on the target update chip renew. In this way, in the present invention, the CPLD is connected with all the boards, and the BMC can switch the channels of the CPLD, and can realize the management of the information of all boards in the server and the version information of the retimer chip, without disassembling the machine. Upgrade and manage the retimer chips of the entire server.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only It is an embodiment of the present invention, and those skilled in the art can also obtain other drawings according to the provided drawings without creative work.

Fig. 1 is a kind of chip upgrading method flow chart that the present application provides;

FIG. 2 is a schematic diagram of an overall structure provided by the present application;

FIG. 3 is a flow chart of a specific chip upgrading method provided by the present application;

FIG. 4 is a schematic structural diagram of a chip upgrading device provided by the present application;

FIG. 5 is a structural diagram of an electronic device provided by the present application.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

In the prior art, when upgrading the chip, the entire server must be disassembled, and the upgrade and commissioning tool of the retimer manufacturer is connected to each board for upgrade and commissioning. This method will require higher personnel requirements for the use of servers that require flexible configuration. If there are multiple boards in a configuration that contain retimer chips, if each retimer chip needs to be upgraded, the tools need to be connected in turn. to each board, wasting R&D and commissioning time. In this application, the retimer chip of the entire server is upgraded and managed without dismantling the machine.

The embodiment of the present invention discloses a method for upgrading a chip, which is applied to a complex programmable logic device connected to a baseboard management controller and a preset external interface in advance, as described in FIG. 1 , the method includes:

Step S11: Open the target path when receiving the target command sent by the baseboard management controller for opening the target path between the complex programmable logic device and the target update chip; the target update chip is configured in On the target board, the target board is one of the multiple boards pre-connected with the complex programmable logic device.

In this embodiment, a complex programmable logic device (Complex Programmable Logic Device, CPLD) is connected to multiple boards, and is connected to a Baseboard Management Controller (Baseboard Management Controller, BMC) and a preset external interface respectively. Each Chips are configured on the boards, and when the chips need to be updated, the external preset debugging tool sends a command for updating the target update chip in the target board through the preset external interface to update the target board. The target update chip is upgraded.In a preferred embodiment, the chip is a retimer chip, and the preset external interface is preferably DB9.

In a specific implementation, the external preset debugging tool first sends an instruction for updating the target update chip in the target board to the baseboard management controller through the external interface, and the baseboard management controller receives the instruction , determine the target update chip, and send to the complex programmable logic device a target command for opening the target path between the complex programmable logic device and the target update chip, and the complex programmable logic device receives the target command , opening the corresponding target path for subsequent transmission of the update file based on the target path.

It can be understood that, in this embodiment, the complex programmable logic device and each of the boards have corresponding paths established respectively, and in a preferred implementation manner, each path is an integrated circuit bus path. Specifically, a path between the complex programmable logic device and each chip in each board can be established. That is, there are paths established between the complex programmable logic device and each chip on each board. When updating a certain chip in a board, first open the corresponding channel in advance, and then complete the subsequent update file transmission process.

During specific implementation, the complex programmable logic device specifically executes a process of switching paths. That is, when multiple chips in multiple boards need to be upgraded, the paths are switched before each upgrade, thereby realizing flexible configuration of the server.

Step S12: Receive the target update file sent by the preset debugging tool through the preset external interface, and send the target update file to the target update chip based on the target path, so as to update the target update chip .

It can be understood that in this embodiment, after the target path between the complex programmable device and the target update chip is opened, the target update file sent by the preset debugging tool through the preset external interface will be received, and based on the The target path sends the target update file to the target update chip, so as to update the target update chip.

In this embodiment, the complex programmable logic device establishes a first communication link with the baseboard management controller, and establishes a second communication link with the preset external interface, and when receiving the baseboard management control If the target command for opening the target path between the complex programmable logic device and the target update chip is sent by the device, opening the target path may include: when receiving If the target command for opening the target path between the complex programmable logic device and the target update chip is sent by the path, the target path is opened. Correspondingly, the receiving the target update file sent by the preset debugging tool through the preset external interface may include: receiving the target update file sent by the preset debugging tool through the preset external interface through the second communication link document. In addition, both the first communication link and the second communication link are integrated circuit bus links, that is, I2C links.

It should be pointed out that, in this embodiment, when establishing the second communication link, the unused free pins after the DB9 is connected to the BMC can be connected to the complex programmable logic device, so that it can be used without changing any configuration. case, make full use of the connector resources connected to the panel.

In this embodiment, when the target command for opening the target path between the complex programmable logic device and the target update chip is received from the baseboard management controller, opening the target path may include: when After receiving the chip update instruction for the target chip sent by the preset debugging tool through the preset external interface by the baseboard management controller through the third communication link, the command sent to open the complex programmable logic device and the target chip The target command for updating the target path between chips opens the target path; wherein, the third communication link is a pre-established link between the baseboard management controller and the preset external interface. In addition, the third communication link is a link constructed based on a Universal Asynchronous Receiver/Transmitter (Universal Asynchronous Receiver/Transmitter, uart).

That is, in this embodiment, after receiving the chip update instruction for the target chip sent by the preset debugging tool through the preset external interface through the third communication link, the baseboard management controller sends the command to the complex programmable logic device. A target command for opening a target path between the complex programmable logic device and a target update chip.

As shown in Figure 2, it is a schematic diagram of the overall structure provided by the present invention. In the figure, the preset external interface is DB9, and the chip is a retimer chip as an example. An I2C link is established between the base board management controller and the complex programmable logic device. , An I2C link is established between the DB9 and the complex programmable logic device, and a uart link is established between the baseboard management controller and the DB9. In the specific implementation scenario, the preset debugging tool sends a chip update command to the baseboard management controller to update the target update chip through the DB9 interface through the uart link. The baseboard management controller is based on the connection between the baseboard management controller and the complex programmable logic device. The pre-established first communication link sends a target command for opening the target path between the complex programmable logic device and the target update chip to the complex programmable logic device, and after the complex programmable logic device opens the corresponding target path, The target update file transmitted by the second communication link is received through the DB9 interface, and the target update file is sent to the target update chip based on the target path to update the chip.

In this embodiment, the complex programmable logic device that is connected to the baseboard management controller and the preset external interface in advance respectively receives the target for opening between the complex programmable logic device and the target update chip sent by the baseboard management controller. After the target command of the path, the target path is opened; the target update chip is configured on the target board, and the target board is one of the multiple boards connected with the complex programmable logic device in advance ; Then the complex programmable logic device receives the target update file sent by the preset debugging tool through the preset external interface, and sends the target update file to the target update chip based on the target path, so as to update the target Update the chip to update. In this way, in the present invention, the CPLD is connected with all the boards, and the BMC can switch the channels of the CPLD, and can realize the management of the information of all boards in the server and the version information of the retimer chip, without disassembling the machine. Upgrade and manage the retimer chips of the entire server.

FIG. 3 is a specific chip upgrade method provided by the embodiment of the present application, which is applied to a baseboard management controller connected to a complex programmable logic device. Referring to shown in Figure 3, the method includes:

Step S21: sending to the complex programmable logic device a target command for opening the target path between the complex programmable logic device and the target update chip, so that the complex programmable logic device opens the target path and After receiving the target update file sent by the default debugging tool through the preset external interface, the target update file is sent to the target update core based on the target path to update the target update chip.

Wherein, the complex programmable logic device is pre-connected to a preset external interface, and the target update chip is configured on a target board, and the target board is a plurality of boards that are pre-connected to the complex programmable logic device A piece of the card.

In this embodiment, sending the target command for opening the target path between the complex programmable logic device and the target update chip to the complex programmable logic device may include: when receiving the target command through the third communication link To the chip update instruction for the target chip on the target board sent by the preset debugging tool through the preset external interface, then based on the chip update instruction, from the complex programmable logic device for recording board information The chip address corresponding to the target chip is determined in the first register of the first register and the second register for recording chip address information; The target command for the target path between addresses.

It can be understood that, in this embodiment, (as shown in FIG. 2 ) the complex programmable logic device includes a first register for recording board information and a second register for recording chip address information, so that the Each chip performs the correct management upgrade. After the BMC receives the chip update instruction, it can determine the chip address information of the target update chip from the first register and the second register in the CPLD based on the first communication link, and after generating the target command based on the chip address information, send to The complex programmable logic device sends the target command.

In the current architecture of the prior art, since the version of the retimer chip is not managed uniformly, the version management of each retimer chip on the board is relatively simple, and only the processing requirements are used for recording, and other engineers cannot check the version. In this regard, (as shown in FIG. 2 ) the present invention also configures a third register for recording chip version information in the complex programmable logic device, so as to facilitate checking and recording the version and configuration mode of each chip, and solve the current problem. There is a chip version management problem in the technology.

In the present invention, the channel switching function based on the I2C channel upgrade retimer chip is uniformly placed in the CPLD of the main board for realization, so that the channel switching is placed in a master control position to facilitate the control of each board. In other implementation manners, the CPLD can be replaced by other switching management devices. This CPLD or switching management device manages each board card containing retimer chip, address information and version information of retimer chip through a register respectively, and then connects the I2C control path to the outside through the remaining pins of DB9, so that Without dismantling the machine, it can be connected to an external debugging tool only through the cable transfer of the connector through DB9, and the retimer chip can be upgraded and managed, so as to achieve the purpose of flexible configuration of the entire server.

Referring to Figure 4, the embodiment of the present application discloses a chip upgrade device, which is applied to complex programmable logic devices connected to the baseboard management controller and the preset external interface in advance, and may specifically include:

The path switching module 11 is configured to open the target path when receiving the target command sent by the baseboard management controller for opening the target path between the complex programmable logic device and the target update chip; the target update The chip is configured on a target board, and the target board is one of a plurality of boards pre-connected to the complex programmable logic device;

The chip update module 12 is configured to receive the target update file sent by the preset debugging tool through the preset external interface, and send the target update file to the target update chip based on the target path, so as to update the target Update the chip to update.

In the present invention, the complex programmable logic device connected to the baseboard management controller and the preset external interface in advance respectively receives the message sent by the baseboard management controller for opening the target path between the complex programmable logic device and the target update chip After the target command, the target path is opened; the target update chip is configured on the target board, and the target board is one of the multiple boards connected with the complex programmable logic device in advance; after that The complex programmable logic device receives the target update file sent by the preset debugging tool through the preset external interface, and sends the target update file to the target update chip based on the target path, so as to update the target chip to update. In this way, in the present invention, the CPLD is connected with all the boards, and the BMC can switch the channels of the CPLD, and can realize the management of the information of all boards in the server and the version information of the retimer chip, without disassembling the machine. Upgrade and manage the retimer chips of the entire server.

Further, the embodiment of this application also discloses an electronic device. FIG. 5 is a structural diagram of an electronic device 20 according to an exemplary embodiment, and the content in the figure should not be regarded as any limitation on the application scope of this application.

FIG. 5 is a schematic structural diagram of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21 , at least one memory 22 , a power supply 23 , a display screen 24 , an input/output interface 25 , a communication interface 26 and a communication bus 27 . Wherein, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement relevant steps in the chip upgrading method disclosed in any of the foregoing embodiments. In addition, the electronic device 20 in this embodiment may specifically be an electronic computer.

In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 26 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows is applicable Any communication protocol in the technical solution of the present application is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the external, and its specific interface type can be selected according to specific application needs, here Not specifically limited.

In addition, the memory 22, as a resource storage carrier, can be a read-only memory, random access memory, magnetic disk or optical disk, etc., and the resources stored thereon can include an operating system 221, a computer program 222, and virtual machine data 223, etc., and the virtual machine data 223 A wide variety of data can be included. The storage method can be short-term storage or permanent storage.

Wherein, the operating system 221 is used to manage and control various hardware devices and computer programs 222 on the electronic device 20 , which may be Windows Server, Netware, Unix, Linux, etc. The computer program 222 may further include a computer program capable of completing other specific tasks in addition to the computer program capable of completing the chip upgrade method performed by the electronic device 20 disclosed in any of the foregoing embodiments.

Further, the present application also discloses a computer-readable storage medium, where the computer-readable storage medium includes random access memory (Random Access Memory, RAM), memory, and read-only memory (Read-OnlyMemory, ROM) , electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, magnetic disk or optical disk or any other form of storage medium known in the technical field. Wherein, when the computer program is executed by the processor, the chip upgrade method disclosed above is realized. Regarding the specific steps of the method, reference may be made to the corresponding content disclosed in the foregoing embodiments, and details are not repeated here.

Each embodiment in this specification is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same or similar parts of each embodiment can be referred to each other. As for the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and for relevant details, please refer to the description of the method part. Professionals can further realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software or a combination of the two. In order to clearly illustrate the possible For interchangeability, in the above description, the composition and steps of each example have been generally described according to their functions. Whether these functions are executed by hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may use different methods to implement the described functions for each specific application, but such implementation should not be regarded as exceeding the scope of the present application.

The steps of the methods or algorithms described in connection with the embodiments disclosed herein may be directly implemented by hardware, software modules executed by a processor, or a combination of both. Software modules can be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other Any other known storage medium.

Finally, it should also be noted that in this text, relational terms such as first and second etc. are only used to distinguish one entity or operation from another, and do not necessarily require or imply that these entities or operations, any such actual relationship or order exists. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

The chip upgrade method, device, equipment, and storage medium provided by the present invention have been introduced in detail above. In this paper, specific examples are used to illustrate the principle and implementation of the present invention. The descriptions of the above embodiments are only used to help understand the present invention The method of the invention and its core idea; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation and scope of application. In summary, the content of this specification should not be understood To limit the present invention.

Claims (10)

1. The chip upgrading method is characterized by being applied to a complex programmable logic device which is respectively connected with a baseboard management controller and a preset external interface in advance, and comprising the following steps:

when a target command for opening a target path between the complex programmable logic device and a target update chip, which is sent by a baseboard management controller, is received, opening the target path; the target updating chip is configured on a target board card, and the target board card is one of a plurality of board cards which are connected with the complex programmable logic device in advance;

and receiving a target update file sent by a preset debugging tool through the preset external interface, and sending the target update file to the target update chip based on the target path so as to update the target update chip.

2. The method of claim 1, wherein the complex programmable logic device establishes a first communication link with the baseboard management controller and establishes a second communication link with the preset external interface, and when a target command sent by the baseboard management controller for opening a target path between the complex programmable logic device and a target update chip is received, opening the target path comprises:

when a target command which is sent by the baseboard management controller through the first communication link and is used for opening a target channel between the complex programmable logic device and a target updating chip is received, opening the target channel;

correspondingly, the receiving the target update file sent by the preset debugging tool through the preset external interface includes:

and receiving a target update file sent by a preset debugging tool through the preset external interface through the second communication link.

3. The chip upgrade method of claim 2 wherein the first communication link and the second communication link are both integrated circuit bus links.

4. A method of upgrading a chip according to any one of claims 1 to 3, wherein when receiving a target command sent by a baseboard management controller for opening a target path between the complex programmable logic device and a target update chip, opening the target path comprises:

after receiving a chip updating instruction which is sent by a preset debugging tool through the preset external interface and is aimed at a target chip through a third communication link, a target command which is sent and used for opening a target channel between the complex programmable logic device and the target updating chip is received by the baseboard management controller, and then the target channel is opened; the third communication link is a link pre-established between the baseboard management controller and the preset external interface.

5. The method of claim 4, wherein the third communication link is a link constructed based on a universal asynchronous receiver transmitter.

6. A method of chip upgrade, applied to a baseboard management controller connected to a complex programmable logic device, comprising:

sending a target command for opening a target path between the complex programmable logic device and a target update chip to the complex programmable logic device, so that the complex programmable logic device opens the target path and sends a target update file to the target update core based on the target path after receiving the target update file sent by a preset debugging tool through the preset external interface to update the target update chip;

the complex programmable logic device is connected with a preset external interface in advance, the target updating chip is configured on a target board card, and the target board card is one of a plurality of board cards which are connected with the complex programmable logic device in advance.

7. The chip upgrade method according to claim 6, wherein the sending the target command to the complex programmable logic device for opening a target path between the complex programmable logic device and a target update chip comprises:

when a chip updating instruction, which is sent by a preset debugging tool through the preset external interface and is aimed at a target chip on a target board, is received through a third communication link, determining a chip address corresponding to the target chip from a first register used for recording board information and a second register used for recording chip address information in the complex programmable logic device based on the chip updating instruction; wherein, the third communication link is a link pre-established between the baseboard management controller and the preset external interface;

a target command is sent to the complex programmable logic device to open a target path between the complex programmable logic device and the target chip address.

8. The chip upgrading device is characterized by being applied to a complex programmable logic device which is respectively connected with a baseboard management controller and a preset external interface in advance, and comprising:

the access switching module is used for opening the target access when receiving a target command which is sent by the baseboard management controller and used for opening the target access between the complex programmable logic device and the target updating chip; the target updating chip is configured on a target board card, and the target board card is one of a plurality of board cards which are connected with the complex programmable logic device in advance;

the chip updating module is used for receiving a target updating file sent by a preset debugging tool through the preset external interface, and sending the target updating file to the target updating chip based on the target path so as to update the target updating chip.

9. An electronic device comprising a processor and a memory; wherein the processor, when executing the computer program stored in the memory, implements the chip upgrade method according to any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program; wherein the computer program, when executed by a processor, implements the chip upgrade method according to any one of claims 1 to 7.