CN116615023A - Semiconductor memory structure - Google Patents

Abstract

The application provides a semiconductor memory structure, which comprises a semiconductor substrate, a bit line on the semiconductor substrate, a dielectric lining on the side wall of the bit line and a capacitor contact on one side of the bit line. The dielectric liner includes: a first nitride liner on the bit line sidewalls, an oxide liner on the first nitride liner sidewalls, and a second nitride liner on the oxide liner sidewalls. The capacitive contact includes: the semiconductor device includes a semiconductor plug disposed on a semiconductor substrate, a metal plug on the semiconductor plug, a metal silicide liner layer including sidewall portions and a bottom portion extending along sidewalls and a bottom portion of the metal plug, respectively, and a nitride layer on the metal silicide liner layer. The sidewall portion is disposed directly above the second nitride liner.

Description

Semiconductor memory structure

Technical Field

The present application relates to a semiconductor memory structure, and more particularly to a contact structure of a dynamic random access memory.

Background

Dynamic random access memory (Dynamic Random Access Memory, DRAM) is widely used in consumer electronics. In order to increase the device density and device performance in dram devices, current dram fabrication technology continues to strive toward device size miniaturization.

However, as device sizes continue to shrink, many challenges are presented. For example, in the semiconductor manufacturing process, a larger capacitance value is generated between bit lines due to a smaller contact area between the semiconductor plug and the metal plug. In addition, when annealing polysilicon, the stress and the growth temperature are different due to the different surrounding materials, so that the silicide layer is easy to generate uneven phenomenon at the corners. Accordingly, there remains a need for improved process techniques for dynamic random access memories that overcome the problems associated with device scaling.

Disclosure of Invention

Embodiments of the present application provide a semiconductor memory structure including a semiconductor substrate, a bit line on the semiconductor substrate, a dielectric liner on a sidewall of the bit line, and a capacitor contact on one side of the bit line. The dielectric liner comprises: a first nitride liner on the bit line sidewalls, an oxide liner on the first nitride liner sidewalls, and a second nitride liner on the oxide liner sidewalls. The capacitive contact includes: a semiconductor plug on a semiconductor substrate, a metal plug on the semiconductor plug, a metal silicide liner comprising extending sidewall portions and bottoms along sidewalls and bottoms of the metal plug, respectively, and a nitride layer on the metal silicide liner. The sidewall portion is disposed directly above the second nitride liner.

Drawings

The features and advantages of the present application will become more apparent from the following detailed description of various embodiments, which is to be read in connection with the accompanying drawings, in which:

fig. 1 is a schematic top view of a semiconductor memory structure according to some embodiments of the application.

Fig. 2-14 are schematic cross-sectional views of a semiconductor memory structure formed at various stages, wherein extensions in the semiconductor material are fully silicided, in accordance with some embodiments of the present application.

Fig. 15-16 are schematic cross-sectional views of a semiconductor memory structure formed at various stages, wherein the extensions in the semiconductor material are not fully silicided, in accordance with other embodiments of the present application.

Fig. 17-18 are schematic cross-sectional views of a semiconductor memory structure formed at various stages according to further embodiments of the present application, wherein the bottom surface of the sidewall portion of the metal silicide liner is lower than the top surface of the bottom portion in the height direction.

Fig. 19-20 are schematic cross-sectional views of a semiconductor memory structure formed at various stages according to still other embodiments of the present application, wherein a bottom surface of a sidewall portion of a metal silicide liner is higher than a top surface of a bottom portion in a height direction.

Detailed Description

Fig. 1 is a schematic top view of a semiconductor memory structure 100 according to some embodiments of the application. In some embodiments, the semiconductor memory structure 100 is part of a Dynamic Random Access Memory (DRAM) array (array). In some embodiments, the semiconductor memory structure 100 includes a semiconductor substrate 102, a word line 106, a bit line contact 108, a bit line 120, a dielectric liner 130, and a capacitor contact 140.

The semiconductor substrate 102 includes an active region 102A and an isolation region 102B surrounding the active region 102A. The dielectric liner 130 includes a pair of nitride liners 131, 133 and an oxide liner 132 sandwiched between the pair of nitride liners 131, 133. The capacitor contact 140 includes a metal plug 148 and an adhesion layer 147 and a nitride layer 144 surrounding the metal plug 148.

In this top-view embodiment, the word line 106 extends along a first direction D1, the bit line 120 extends along a second direction D2, and the active region 102A extends along a third direction D3. In this embodiment, the first direction D1 is perpendicular to the second direction D2, and the third direction D3 (i.e. the extending direction of the active region 102A) forms an angle of about 10 ° to 40 °, for example, 20 °, with the second direction D2, so as to improve the integration of the device.

In this top view embodiment, the capacitive contact 140 extends through the second nitride liner 133 and the oxide liner 132 in the first direction without passing through the first nitride liner 131. In this embodiment, the nitride layer 144 directly contacts the first nitride liner 131, the oxide liner 132, and the second nitride liner 133.

It should be noted that fig. 1 shows only a portion of the elements of a Dynamic Random Access Memory (DRAM) to simplify the drawing. The following is illustrated as a schematic cross-sectional view (a plane formed by the first direction D1 and the height direction Z) along a section line A-A' in fig. 1 to facilitate explanation of the method of forming the semiconductor memory structure.

Fig. 2-14 are schematic cross-sectional views of a semiconductor memory structure 100 at various stages in the formation of the structure, according to some embodiments of the application.

As shown in fig. 2, a semiconductor substrate 102 is provided, wherein the semiconductor substrate 102 includes an active region 102A and an isolation region 102B, and is staggered with each other. In fig. 2, an isolation feature 104 is disposed in an isolation region 102B of a semiconductor substrate 102, which includes an isolation liner 1041 and an isolation fill 1042.

In some embodiments, word lines (not shown) are buried in the active region of the semiconductor substrate. In some embodiments, the word line serves as a gate and includes a gate dielectric layer, a gate liner layer, and a gate electrode (not shown). It should be noted that no word line is present in fig. 2, since word line 106 in fig. 1 extends along the first direction D1 and the split line A-A' does not contact word line 106.

In fig. 2, the bit line contacts 108 are partially buried in the active region 102A of the semiconductor substrate 102 to facilitate subsequent electrical connection with the bit lines 120. In some embodiments, spacers 109 are provided on both sides of the bit line contacts 108 to prevent shorting of the bit line contacts to subsequently formed capacitive contacts.

In some embodiments, the bit line contacts 108 are polysilicon with dopants to reduce the contact resistance with subsequently formed bit lines. The dopant may comprise an n-type or p-type dopant, such as nitrogen, arsenic, phosphorus, antimony ions or boron, aluminum, gallium, indium, boron trifluoride ions (bf3+).

In some embodiments, the spacers 109 are dielectric materials that include a nitride, such as silicon nitride.

With continued reference to fig. 2, a cap layer 110 is formed on the semiconductor substrate 102 to protect the devices in the semiconductor substrate from subsequent processes. In some embodiments, cap layer 110 includes an oxide layer 112 and a nitride layer 114.

In some embodiments, oxide layer 112 comprises a silicon oxide layer formed from Tetraethoxysilane (TEOS). In some embodiments, nitride layer 114 comprises silicon nitride (SiN) or silicon oxynitride (SiON). In some embodiments, the oxide layer 112 and the nitride layer 114 may be sequentially formed by deposition processes as described above.

Next, as shown in fig. 2, forming the bit line 120 on the semiconductor substrate 102 also includes forming the bit line 120 on the bit line contact 108. In some embodiments, bit line 120 on bit line contact 108 includes conductive layers 122 and 123 on bit line contact 108, and dielectric layers 124 and 125 on conductive layers 122 and 123. The bit line 120 on the isolation feature 104 includes a dielectric layer 121 on the cap layer 110, conductive layers 122 and 123 on the dielectric layer 121, and dielectric layers 124 and 125 on the conductive layers 122 and 123. By the uppermost dielectric layers 144 and 145, the underlying film layers (e.g., conductive layers 122 and 123) may be protected from damage during subsequent processing.

In some embodiments, conductive layers 122 and 123 comprise doped polysilicon, metal, or metal nitride, such as tungsten (W), titanium (Ti), titanium nitride (TiN), and the like. In some embodiments, dielectric layers 121, 124, and 125 comprise a nitride, such as silicon nitride, or the like.

Next, as shown in fig. 2, a dielectric liner 130 is formed on both sidewalls and top surface of the bit line 120 and on the cap layer 110 to prevent the bit line 120 from being in direct contact with a subsequently formed capacitor contact to short.

In some embodiments, the dielectric liner 130 on both sidewalls of the bit line 120 includes a first nitride liner 131 and a second nitride liner 133, and an oxide liner 132 disposed therebetween, thereby preventing parasitic capacitance between the bit line 120 and a subsequently formed capacitor contact. In an alternative embodiment, the oxide liner 132 may also be replaced by an air gap (air gap).

In some embodiments, the dielectric liner 130 on the top surface of the bit line 120 and on the cap layer 110 includes only the second nitride liner 133 to protect the underlying film from subsequent processes.

In some embodiments, the first nitride liner 131 and the oxide liner 132 are deposited by a deposition process, the first nitride liner 131 and the oxide liner 132 on the top surface of the bit line 120 and the top surface of the cap layer are removed by an etch back process, and the nitride liner 133 is deposited by a deposition process such that the oxide liner 132 is sandwiched between the first nitride liner 131 and the second nitride liner 133.

Next, fig. 3-13 are cross-sectional views of the bit line 120 at various stages of forming the capacitor contact 140.

As shown in fig. 3, the cap layer 110 and the semiconductor substrate 102 (also including the etched portion of the spacer 109) are recessed along the sidewalls of the dielectric liner 120 by an etch back process to electrically connect the subsequently formed capacitive contact to the active region 102A of the semiconductor substrate 102.

Next, as shown in fig. 4 and 5, a semiconductor material 141 is deposited by a deposition process, and then the semiconductor material 141 is etched by an etch back process such that a top surface of the semiconductor material 141 is lower than a top surface of the bit line 120 and higher than the conductive layer 123 in the bit line 120. In some embodiments, semiconductor material 141 comprises doped polysilicon.

Next, as shown in fig. 6, the second nitride liner 133 and the oxide liner 132 on the semiconductor material 141 are removed by an etching process. In this embodiment, the etchant comprises sicon to etch the second nitride liner 133 and the oxide liner 132 without substantially etching the semiconductor material 141. In addition, the first nitride liner 131 may be used as an etch stop layer and the etching process may be stopped by an etch signal. In this way, the first nitride liner 131 may remain on the entire sidewall of the bit line 120 and protect the bit line 120 from subsequent processes. Here, the removing of the second nitride liner 133 and the oxide liner 132 may include removing a portion of the uppermost dielectric layer 125 in the bit line 120. That is, the height of the bit line 120 may be slightly reduced by the influence of the etching process. In other embodiments, the removal of the second nitride liner 133 and the oxide liner 132 does not include removing a portion of the bit line 120. That is, the height of the bit line 120 may not be affected by the etching process.

Next, as shown in fig. 7 and 8, the semiconductor material 141 is again deposited by a deposition process, and the semiconductor material 141 is again etched by an etch back process such that the top surface of the semiconductor material 141 is below the top surface of the bit line 120 and above the top surfaces of the oxide liner 132 and the second nitride liner 133.

Next, as shown in fig. 9 and 10, a nitride material layer 143 is conformally deposited by a deposition process, and then the nitride material layer 143 on the top surface of the semiconductor material 141 and the top surface of the bit line 120 is etched by an etching process until a portion of the top surface of the semiconductor material 141 is exposed, leaving a nitride layer 144 on both sides of the bit line 120.

In some embodiments, the top surface of the nitride layer 144 is flush with the top surfaces of the first nitride liner 131 and the bit line 120, so that the nitride layer 144 has a finer pattern, which is advantageous for defining the metal silicide liner later. In addition, the sidewalls of the nitride layer 144 directly contact the sidewalls of the first nitride liner 131.

By replacing the upper oxide liner with a nitride layer and semiconductor material, subsequent damage to the oxide liner due to post-clean (post-clean) processes may be prevented.

Next, as shown in fig. 11, the semiconductor material 141 is etched by an etching process with the nitride layer 144 as an etching mask to form a recess 1410 in the semiconductor material 141, and the semiconductor material 141 is divided into an extension portion 141t on a sidewall of the recess 1410 and a body portion 141b under a bottom of the recess. In some embodiments, the top surface of body portion 141b is lower than the top surface of extension portion 141t and higher than the top surface of conductive layer 123 in bit line 120. In some embodiments, at least a portion of the body portion 141b and at least a portion of the extension portion 141t will be subsequently converted to a metal silicide liner.

In fig. 11, the body portion 141b and the extension portion 141t intersect at only one point. That is, the top surface of the body portion 141b is substantially flush with the bottom surface of the extension portion 141 t. In other embodiments, the body portion 141b and the extension portion 141t are connected to each other by a portion of the sidewall. In still other embodiments, the body portion 141b and the extension portion 141 are not connected to each other.

Next, as shown in fig. 12, a portion of the semiconductor material 141 is converted into a metal silicide liner 146 by a silicidation (salicidation) process to reduce the contact resistance with a subsequent metal plug (not shown). Specifically, the extension portion 141t extending along the side surface of the notch 1410 is completely converted into the sidewall portion 146s of the metal silicide liner 146, and the body portion 141b extending along the bottom of the notch 1410 is partially converted into the bottom portion 146b of the metal silicide liner 146. Here, the remaining semiconductor material 141 is referred to as a semiconductor plug 141, and the remaining body portion 141b is referred to as a body portion 141b'.

In some embodiments, the bottom portion 146b assumes an arc shape at the corner C due to the silicidation process, so the sidewall portion 146s does not directly contact the bottom portion 146b. In some embodiments, in the height direction Z, the bottom surface of the sidewall portion 146s is flush with the top surface of the bottom portion 146b. It should be noted that the top surface of the bottom 146b is denoted herein as the top surface of the highest point of the bottom 146b.

In some embodiments, in the height direction Z, the sidewall portions 146s are sandwiched between the nitride layer 144 and the second nitride liner 133. In some embodiments, in the height direction Z, the sidewalls of the nitride layer 144, the sidewalls of the sidewall portions 146s, and the sidewalls of the second nitride liner 133 are aligned with each other. That is, the nitride layer 144, the sidewall 146s, and the second nitride liner 133 are disposed from top to bottom in the height direction Z. That is, the sidewall portion 146s is located directly above the second nitride liner 133. In some embodiments, sidewall portions 146s are disposed on sidewalls of the first nitride liner 131 and bottom portions 146b are disposed on sidewalls of the second nitride liner 133.

In fig. 12, the sidewall 146s is provided directly above the oxide liner 132 in the height direction Z. That is, the bottom surface of the sidewall portion 146s is in direct contact with the top surface of the oxide liner 132 and the top surface of the second nitride liner 133. In fig. 12, in the height direction Z, the side walls of the nitride layer 144, the side walls of the side wall portions 146s, and the side walls of the oxide liner 132 are aligned with each other.

In some embodiments, the silicidation process includes depositing a metal (e.g., cobalt) on the semiconductor material 141 including the extension 141t and the body 141b, annealing the metal, and removing unreacted portions of the metal using a wet etching process to form the metal silicide liner 146. In some embodiments, the metal silicide liner 146 comprises silicon cobalt oxide (CoSi).

Compared with the semiconductor material only provided with the body part, the embodiment of the application further comprises the extension part, so that the semiconductor material at the corner has more uniform stress and growth temperature in the silicidation process due to the contact of the semiconductor material at the corner with the more similar material, thereby improving the uniformity of the metal silicide layer. That is, the bottom 146b of the metal silicide layer 146 in the embodiment of the application is not greatly lowered at the corner C (the bottom 146b forms only a relatively flat arc surface at the corner C), so as to improve the uniformity of the bottom 146b.

According to the embodiment of the application, the contact area between the metal silicide lining and the metal plug formed later can be increased through the side wall part of the metal silicide lining, so that the contact resistance is reduced.

In some embodiments, since the extension portion 141T and the body portion 141b of the semiconductor material 141 are simultaneously converted into the sidewall portion 146s and the bottom portion 146b of the metal silicide liner 146 by the silicidation process, the width W146s of the sidewall portion 146s is substantially equal to the thickness T146 of the bottom portion 146b.

In some embodiments, a width W146s of the sidewall portion 146s of the metal silicide liner 146 is not greater than a sum of a width W132 of the oxide liner 132 and a width W133 of the second nitride liner 133 (w132+w133). In fig. 12, the width W146s of the sidewall 146s of the metal silicide liner 146 is equal to the widths of the oxide liner 132 and the second nitride liner 133. Therefore, the width of the metal plug to be formed later can be maintained, and the offset of the metal plug and the conductive barrier layer later can be prevented.

In some embodiments, the ratio of the width W146s of the sidewall portion 146s of the metal silicide liner 146 to the width W120 of the bit line 120 is between 1% -65%. Between the above ratios, the contact resistance of the capacitive contact can be reduced without offsetting the subsequent metal plug from the conductive barrier. In fig. 12, the above ratio is between 40% and 65%.

Next, as shown in fig. 13, an adhesion layer material is formed along the surface of the metal silicide liner 146 by a deposition process and a planarization process, and a metal material is formed on the adhesion layer material, and then the adhesion layer 147 and the metal plug 148 are formed by removing the excess portion by the planarization process.

In fig. 13, the capacitor contact 140 includes a semiconductor plug (only the body portion 141b' in fig. 13) disposed on the semiconductor substrate 102, a metal silicide liner 146 including sidewall portions 146s and a bottom portion 146b extending along sidewalls and a bottom portion of the metal plug 148, respectively, a nitride layer 144 disposed on the metal silicide liner 146, and an adhesion layer 147 disposed between the metal silicide liner 146 and the metal plug 148.

In some embodiments, the adhesion layer 147 may increase the adhesion between the metal silicide liner 146 and the metal plug 148. In some embodiments, the top surface of adhesion layer 147, the top surface of metal plug 148, is flush with the top surface of nitride layer 144. In some embodiments, since the adhesion layer 147 is formed along the sidewall portion 146s and the bottom portion 146b of the metal silicide liner 146, the adhesion layer 147 substantially assumes a U-shape and surrounds the metal plug 148.

In some embodiments, the adhesion layer 147 extends along the sidewalls of the nitride layer 144 and the sidewalls 146s and bottom 146b of the metal silicide liner 146 and directly contacts the sidewalls 146s and bottom 146b of the nitride layer 144 and the metal silicide liner 146. In some embodiments, the adhesion layer 147 comprises titanium (Ti) or titanium nitride (TiN), or the like.

In some embodiments, the top surface of metal plug 148 is flush with the top surface of nitride layer 144. In some embodiments, a top surface of sidewall portions 146s of metal silicide liner 146 is lower than a top surface of metal plugs 148 in a height direction Z. In some embodiments, the sidewall portion 146s of the metal silicide liner 146 and the nitride layer 144 are disposed between the first nitride liner 131 and the metal plug 148.

In some embodiments, the sidewalls of the upper portion of metal plug 148 are surrounded by nitride layer 144, while the sidewalls of the lower portion of metal plug 148 are surrounded by sidewall portions 146s of metal silicide liner 146.

Compared with the case of only disposing the metal silicide liner layer at the bottom of the metal plug, the embodiment of the application further disposes the metal silicide liner layer 146 at the sidewall of the metal plug 148 to increase the contact area, thereby reducing the resistance of the capacitor contact.

In some embodiments, the bottom surface of metal plug 148 is not lower than the top surface of conductive layer 123 in bit line 120, thereby reducing the capacitance value of bit line 120 and capacitive contact 140.

In some embodiments, the semiconductor substrate 102 under the bit line contact 108 has a doped region (not shown) that can be used as a source, and the semiconductor substrate 102 under the capacitor contact 140 also has a doped region (not shown) that can be used as a drain. In any of the active regions 102A extending along the third direction D3, the capacitor contacts 140, the word line 106, the bit line contacts 108, the word line 106, and the capacitor contacts 140 may be arranged in the order of drain, gate, source, gate, and drain, respectively, in accordance with fig. 1. That is, the active region 102A includes two sets of transistor structures sharing the same source, so that the layout can be used more effectively to save the manufacturing cost.

Referring next to fig. 14, a dielectric layer 152, a conductive barrier layer 154, and a capacitor structure 160 are formed over the capacitor contact 140 and the bit line 120.

In some embodiments, in the first direction D1, both the dielectric layer 152 and the conductive barrier layer 154 are staggered. The conductive barrier layer 154 is located directly above the capacitive contact 140 and spans to the nitride layer 144. In some embodiments, the conductive barrier layer 154 comprises a material that is resistant to penetration by etching solutions, such as tungsten or copper.

In some embodiments, the capacitor structure 160 includes electrode layers 162 and 166 and a dielectric layer 164 sandwiched therebetween. In some embodiments, electrode layer 162 is formed on conductive barrier layer 154 and has a U-shaped cross-sectional profile. In some embodiments, dielectric layer 164 extends along electrode layer 162 and conductive barrier layer 154 and is a continuous film. It should be noted that the capacitor structure of fig. 14 is only an example, and those skilled in the art can apply the capacitor structure different from fig. 11 to the capacitor contact 140.

In some embodiments, the dielectric layer 164 may include silicon nitride (Si 3N 4), aluminum oxide (Al 2O 3), yttrium oxide (Y2O 3), titanium oxide (TiO), hafnium oxide (HfO 2), zirconium dioxide (ZrO 2), or the like. In some embodiments, electrode layers 162 and 166 may include silicon germanium (SiGe), titanium nitride, tungsten nitride, tantalum nitride, or the like, to reduce leakage current.

It should be noted that additional features, such as metal layers and dielectric layers, etc., may be formed after the formation of the capacitor structure 160 to complete the fabrication of a memory device, such as a Dynamic Random Access Memory (DRAM).

In summary, the embodiment of the application can improve the uniformity of the metal silicide lining layer by forming the side wall part and the bottom part of the metal silicide lining layer, and simultaneously reduce the resistance in the capacitor contact, thereby improving the semiconductor performance.

Fig. 15 and 16 are schematic cross-sectional views illustrating various stages in forming a semiconductor memory structure according to other embodiments of the present application.

Referring to fig. 11, as shown in fig. 15, the extension portion 141t extending along the sidewall of the recess 1410 is partially converted into the sidewall portion 146s of the metal silicide liner 146 by a silicidation (silicidation) process, and the body portion 141b extending along the bottom of the recess 1410 is partially converted into the bottom portion 146b of the metal silicide liner 146. Here, the remaining semiconductor material 141 is referred to as a semiconductor plug 141, the remaining body portion 141b is referred to as a body portion 141b ', and the remaining extension portion 141t is referred to as an extension portion 141t'. In some embodiments, body portion 141b 'does not contact extension portion 141t'.

In fig. 15, in the height direction Z, the extension 141t' is provided directly above the oxide liner 132. That is, the bottom surface of the extension 141t' is in direct contact with the top surface of the oxide liner 132.

In fig. 15, in the height direction Z, the sidewalls of the nitride layer 144, the extension 141t', and the oxide liner 132 are aligned with each other. Namely, in the height direction Z, the nitride layer 144, the extension 141t', and the oxide liner 132 are disposed from top to bottom. In other words, in the height direction Z, the extension 141t' is sandwiched between the nitride layer 144 and the oxide liner 132.

In fig. 15, the extension portion 141t 'is disposed on the sidewall of the first nitride liner 131, and the body portion 141b' is disposed on the sidewall of the second nitride liner 133. In the first direction D1, the extension portion 141t' is disposed between the first nitride liner 131 and the sidewall portion 146s of the metal silicide liner 146.

In fig. 15, the width W146s of the sidewall portion 146s of the metal silicide liner 146 is smaller than the sum of the width W132 of the oxide liner 132 and the width W133 of the second nitride liner 133. The width W146s of the sidewall portions 146s of the metal silicide liner 146 is substantially equal to the thickness T146b of the bottom portion 146b. In fig. 15, the ratio of the width W146s of the sidewall 146s of the metal silicide liner 146 to the width W120 of the bit line 120 is between 1% -40% or 5% -30%.

The semiconductor plug 141b 'further includes an extension portion 141t', so that the capacitance of the bit line can be further reduced.

Next, the adhesion layer 147 and the metal plug 148 are formed similarly to the above process, and the semiconductor memory structure as shown in fig. 16 can be obtained.

Fig. 17 and 18 are schematic cross-sectional views illustrating various stages in forming a semiconductor memory structure according to further embodiments of the present application.

Referring to fig. 10, as shown in fig. 17, a recess 1410 is formed in the semiconductor material 141, and the semiconductor material 141 is divided into an extension portion 141t on a sidewall of the recess 1410 and a body portion 141b under a bottom of the recess, and the body portion 141b and a portion of the sidewall of the extension portion 141t are connected to each other, and by a process similar to that described above, a semiconductor memory structure as in fig. 18 can be obtained.

Fig. 18 is similar to fig. 13, except that the bottom surface of the sidewall portion 146s in the metal silicide liner 146 is lower than the top surface of the bottom portion 146b in the height direction Z. Therefore, the stress and the growth temperature of the bottom 146b of the metal silicide liner 146 at the corners due to the different materials can be reduced more effectively, and the uniformity can be improved more.

Fig. 19 and 20 are schematic cross-sectional views of a semiconductor memory structure formed at different stages according to further embodiments of the present application.

Referring to fig. 10, as shown in fig. 19, a recess 1410 is formed in the semiconductor material 141, and the semiconductor material 141 is divided into an extension portion 141t on a side wall of the recess 1410 and a body portion 141b under a bottom of the recess, and the body portion 141b and the side wall of the extension portion 141t are not connected (or the body portion 141b and the extension portion 141t are projected to be not in contact with each other in the height direction Z), and by a process similar to the above, the semiconductor memory structure as in fig. 20 can be obtained.

Fig. 20 is similar to fig. 18, except that the bottom surface of the sidewall portion 146s in the metal silicide liner 146 is higher than the top surface of the bottom portion 146b in the height direction Z. Therefore, the contact area of the metal plug can be increased, and the resistance in the capacitor contact can be reduced.

In summary, the embodiment of the application can reduce the resistance of the capacitor contact and improve the uniformity of the metal silicide lining through the sidewall of the metal silicide lining disposed on both sides of the metal plug. In addition, the capacitance of the bit line can be further reduced by the extension of the semiconductor plug disposed on the sidewall portion of the metal silicide liner.

Claims (10)

1. A semiconductor memory structure, comprising:

a semiconductor substrate;

a bit line disposed on the semiconductor substrate;

a dielectric liner disposed on sidewalls of the bit lines, wherein the dielectric liner comprises:

a first nitride liner disposed on sidewalls of the bit lines;

an oxide liner disposed on sidewalls of the first nitride liner; and

a second nitride liner disposed on sidewalls of the oxide liner; and

a capacitive contact disposed on one side of the bit line, wherein the capacitive contact comprises:

a semiconductor plug disposed on the semiconductor substrate;

a metal plug arranged on the semiconductor plug;

a metal silicide liner layer comprising a sidewall portion and a bottom portion extending along the sidewall and bottom portions of the metal plug, respectively, wherein the sidewall portion is disposed directly above the second nitride liner layer; and

and the nitride layer is arranged on the metal silicide lining layer.

2. The semiconductor memory structure of claim 1, wherein the sidewall portion does not directly contact the bottom portion.

3. The semiconductor memory structure according to claim 1, wherein the sidewall portion is disposed between the first nitride liner and the metal plug.

4. The semiconductor memory structure according to claim 1, wherein the sidewall portion is sandwiched between the nitride layer and the second nitride liner in a height direction.

5. The semiconductor memory structure of claim 1, wherein sidewalls of the nitride layer, sidewalls of the sidewall portion, and sidewalls of the second nitride liner are aligned with one another.

6. The semiconductor memory structure of claim 1, wherein the sidewall portion directly contacts the oxide liner.

7. The semiconductor memory structure of claim 1, wherein the semiconductor plug comprises a body portion disposed under the bottom portion and an extension portion disposed on a sidewall of the sidewall portion, wherein the body portion does not contact the extension portion.

8. The semiconductor memory structure according to claim 7, wherein the extension is sandwiched between the nitride layer and the oxide liner in a height direction.

9. The semiconductor memory structure according to claim 7, wherein the extension portion is disposed between the first nitride liner layer and the sidewall portion.

10. The semiconductor memory structure of claim 1, wherein in a top view, the nitride layer directly contacts the first nitride liner, the oxide liner, and the second nitride liner.