CN115084034A

CN115084034A - Semiconductor memory structure and forming method thereof

Info

Publication number: CN115084034A
Application number: CN202110280438.XA
Authority: CN
Inventors: 杨峻昇; 陈兴豪
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2021-03-16
Filing date: 2021-03-16
Publication date: 2022-09-20

Abstract

A semiconductor memory structure and a forming method thereof comprise providing a semiconductor substrate, wherein a pair of word lines are embedded in an active region of the semiconductor substrate, and the word lines extend along a first direction; forming a hard mask layer on the semiconductor substrate; forming a contact opening through the hard mask layer and a portion of the semiconductor substrate corresponding to the pair of word lines; forming a pair of spacers on sidewalls of the contact opening; filling a conductive material in the contact opening to form a contact; forming a bit line directly over the contact and the pair of spacers, wherein the bit line extends along a second direction, wherein the first direction is perpendicular to the second direction; and forming a dielectric liner on sidewalls of the bit lines.

Description

Semiconductor memory structure and forming method thereof

Technical Field

The present application relates generally to semiconductor memory structures and methods of forming the same, and more particularly to dynamic random access memories.

Background

Dynamic Random Access Memory (DRAM) devices are widely used in consumer electronics. In order to increase the device density in dram devices and improve the overall performance thereof, the current technology of dram devices is continuously striving towards the miniaturization of device dimensions.

However, as device dimensions continue to shrink, many challenges ensue. For example, in a semiconductor manufacturing process, nitride is generally disposed beside a contact in order to prevent a short circuit between a bit line contact and a subsequent capacitor contact, but the upper bit line structure may be damaged by an etchant such as phosphoric acid during the nitride patterning process. Therefore, there is still a need for an improved method for manufacturing a dram device to overcome the problems caused by the reduction of device size.

Disclosure of Invention

The embodiment of the invention provides a method for forming a semiconductor memory structure. The method includes providing a semiconductor substrate, wherein a pair of word lines are embedded in an active region of the semiconductor substrate, wherein the pair of word lines extend along a first direction; forming a hard mask layer on the semiconductor substrate; forming a contact opening through the hard mask layer and a portion of the semiconductor substrate corresponding to the pair of word lines; forming a pair of spacers on sidewalls of the contact opening; filling a conductive material in the contact opening to form a contact; forming a bit line directly above the contact and the pair of spacers, wherein the bit line extends along a second direction, wherein the first direction is perpendicular to the second direction; and forming a dielectric liner on sidewalls of the bit line.

The embodiment of the invention provides a semiconductor memory structure, which comprises a semiconductor substrate, a first memory layer, a second memory layer and a first control layer, wherein the semiconductor substrate is provided with an active region; a pair of word lines embedded in an active region of a semiconductor substrate, wherein the pair of word lines extend along a first direction; a cap layer disposed on the semiconductor substrate; a contact passing through the cap layer and partially disposed in the semiconductor substrate; a pair of spacers disposed on sidewalls of the contacts and corresponding to the pair of word lines; a bit line extending along a second direction, wherein the first direction is perpendicular to the second direction, and wherein the bit line is disposed directly above the contact and the pair of spacers on a cross section of the first direction; and a dielectric liner layer disposed on the sidewalls of the bit lines.

Drawings

In order to make the features and advantages of the present invention comprehensible, various embodiments accompanied with figures are described in detail as follows:

FIG. 1 is a schematic top view of a semiconductor memory structure according to some embodiments of the present invention;

FIGS. 2A-7A, 2B-7B are schematic cross-sectional views of a semiconductor memory structure formed at various stages according to some embodiments of the present invention;

FIG. 8 is a schematic top view of a semiconductor memory structure, according to some embodiments of the present invention;

FIGS. 9A-20A, 9B-20B are cross-sectional views of a semiconductor memory structure formed at various stages according to some embodiments of the present invention.

[ description of symbols ]

100: semiconductor memory structure

102: semiconductor substrate

102A: active region

102B: isolation region

104: isolation component

1041: isolation liner

1042: isolation filler

106: word line

1061: gate dielectric layer

1062: gate liner

1063: grid electrode

108: protective layer

110: hard mask layer

110': cover layer

112,114,116: dielectric layer

120: contact opening

131: spacer material layer

132: spacer material

133: conductive material

134: contact element

136: spacer

140: bit line stack layer

141,142: conductive layer

143,144,145: dielectric layer

140': bit line

141',142': conductive pattern

143,144,145: dielectric pattern

150: dielectric liner

151: nitride material liner

152: nitride liner

153: oxide material liner

154: oxide liner

156: nitride liner

160: opening(s)

170: capacitor contact

171: conductive material

172: conductive layer

174: silicide layer

175: conductive material

176: conductive layer

WC: width of

WS: width of

Detailed Description

The present application is described more fully hereinafter with reference to the accompanying drawings of embodiments of the invention. However, the present application may be implemented in various different embodiments and should not be limited to the embodiments described herein. The thickness of layers and regions in the figures may be exaggerated for clarity and the same or similar reference numbers indicate the same or similar elements throughout the figures.

Fig. 1 is a schematic top view of a semiconductor memory structure 100, according to some embodiments of the invention. In some embodiments, the semiconductor memory structure 100 is part of a Dynamic Random Access Memory (DRAM) array (array). In some embodiments, semiconductor memory structure 100 includes a semiconductor substrate 102, a word line 106, contacts 134, spacers 136, bit lines 140', and capacitive contacts 170. The semiconductor substrate 102 includes an active region 102A and an isolation region 102B. In this embodiment, the word line 106 extends along the first direction D1, the bit line 140' extends along the second direction D2, and the active region 102A extends along the third direction D3. In this embodiment, the first direction D1 is perpendicular to the second direction D2, and the third direction D3 (i.e., the extending direction of the active region 102A) forms an angle of about 10-40 DEG, such as 20 DEG, with the second direction D2, so as to improve the integration of the device.

It should be noted that fig. 1 only shows some elements of a Dynamic Random Access Memory (DRAM) to simplify the drawing. The following figures are schematic cross-sectional views along the line a-a 'and the line B-B' of fig. 1, so as to illustrate the formation method of the semiconductor memory structure.

Fig. 2A-7A and 2B-7B are schematic cross-sectional views illustrating different stages in forming the semiconductor memory structure 100, according to some embodiments of the present invention. The cross-sectional views of fig. 2A-7A and 2B-7B are taken along the cross-sectional line a-a '(the first direction D1) and the cross-sectional line B-B' (the second direction D2) of fig. 1, and may be referred to as the cross-sectional view of the first direction and the cross-sectional view of the second direction, respectively.

It should be noted that in the cross-sectional views along the sectional line a-a 'and the sectional line B-B', the horizontal directions are the first direction D1 and the second direction D2 in fig. 1, respectively, and the vertical directions are both indicated as the Z direction.

As shown in fig. 2A and 2B, a semiconductor substrate 102 is provided. In some embodiments, the semiconductor substrate 102 may be an elemental semiconductor substrate, such as a silicon substrate, or a germanium substrate; or a compound semiconductor substrate such as a silicon carbide substrate, or a gallium arsenide substrate. In some embodiments, the semiconductor substrate 102 may be a semiconductor-on-insulator (SOI) substrate.

In some embodiments, the semiconductor substrate 102 includes an active region 102A and an isolation region 102B surrounding the active region 102A. In some embodiments, an isolation feature 104 is disposed in the isolation region 102B of the semiconductor substrate 102, which includes an isolation liner 1041 and an isolation fill 1042. For simplicity, the active region 102A and the isolation region 102B will not be labeled in the subsequent cross-sectional views.

In some embodiments, the isolation liner 1041 and the isolation fill 1042 may comprise a nitride or an oxide, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and/or combinations thereof. The formation of the isolation liner 1041 and the isolation filler 1042 may include a patterning process (e.g., a photolithography process and an etching process), a deposition process (e.g., Chemical Vapor Deposition (CVD)), a planarization process (e.g., Chemical Mechanical Polishing (CMP)).

As shown in fig. 2A, a pair of word lines 106 and a passivation layer 108 thereon are buried in the active region 102B of the semiconductor substrate 102. In some embodiments, the pair of word lines 106 are disposed between the isolation features 104 and do not contact the isolation features 104. It should be noted that the word line 106 is not present in FIG. 2A because the word line extends along the first direction D1 and the cross-sectional line A-A' does not contact the word line 106.

In some embodiments, the word line 106 functions as a gate and includes a gate dielectric layer 1061, a gate liner 1062, and a gate electrode 1063.

In some embodiments, a trench (not shown) is formed by a patterning process, and a gate dielectric layer 1061 is formed in the trench. In some embodiments, the gate dielectric layer 1061 is formed of silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material. In some embodiments, the formation of the gate dielectric layer 1061 includes an oxidation process or a deposition process. The oxidation process comprises thermal oxidation. Deposition processes include Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or the like.

In some embodiments, a gate liner 1062 is formed on the gate dielectric layer 1061. In some embodiments, the gate liner 1062 is formed of tungsten nitride (WN), titanium nitride (TiN), or tantalum nitride (TaN). In some embodiments, the gate liner 1062 may be formed using the deposition process described above, and thus, will not be described in detail herein.

In some embodiments, a gate electrode 1063 is formed on the gate liner 1062. In some embodiments, the gate electrode 1063 is formed of a conductive material, such as doped polysilicon, a metal, or a metal nitride. In some embodiments, the gate electrode 1063 may be formed by the deposition process described above, and thus, will not be described herein.

In some embodiments, after depositing the materials for the gate dielectric layer 1061, the gate liner 1062, and the gate electrode 1063, the gate liner 1062 and the gate electrode 1063 are etched back so that the gate dielectric layer 1061, the gate liner 1062, and the gate electrode 1063 become the word line 106. The etch back is performed such that the word line 106 is lower than the top surface of the semiconductor substrate 102, so as to form a protection layer 108 on the word line 106.

In some embodiments, a protective layer 108 is formed on the top surfaces of the gate dielectric layer 1061, the gate liner 1062, and the gate electrode 1063. In some embodiments, the protection layer 108 comprises silicon nitride, which may be used as a gate dielectric layer to control the channel. In some embodiments, the formation of the protection layer 108 includes depositing nitride on the word line 106 by a deposition process, and removing the nitride on the semiconductor substrate 102 by an etch-back process, wherein the top surface of the nitride is flush with the top surface of the semiconductor substrate 102. The deposition process is similar to that described above and therefore will not be described in detail here.

Next, as shown in FIG. 2A and FIG. 2B, a hard mask layer 110 is formed on the semiconductor substrate 102 and the passivation layer 108. In some embodiments, the hard mask layer 110 includes a first oxide layer 112, a nitride layer 114, and a second oxide layer 116.

In some embodiments, the first oxide layer 112 and the second oxide layer 116 include a silicon oxide layer formed from Tetraethoxysilane (TEOS). In some embodiments, the nitride layer 114 comprises silicon nitride (SiN) or silicon oxynitride (SiON).

In some embodiments, the first oxide layer 112, the nitride layer 114, and the second oxide layer 116 may be sequentially formed by a deposition process as described above.

It should be noted that in this embodiment, the second oxide layer 116 has a thicker thickness than the first oxide layer 112 to prevent subsequent processes from affecting or damaging the nitride layer 114 located therebetween.

Next, as shown in FIGS. 3A and 3B, a contact opening 120 is formed between the isolation features 104, wherein the contact opening 120 penetrates through the hard mask layer 110 and a portion of the semiconductor substrate 120. In fig. 3B, the contact openings 120 correspond to a pair of word lines 106 and pass through a portion of the protection layer 108, but do not contact the word lines 106, to avoid leakage in case of increasing the threshold voltage.

In some embodiments, one side of the contact opening 120 is located between two edges of one word line, and the other side of the contact opening 120 is also located between two edges of another word line. When the side of the contact opening 120 extends beyond the word line 106 and toward the isolation feature 104, it is easy to cause a leakage current caused by the contact between the subsequently formed contact and the active region 102A. When the side of the contact opening 120 is located between the word lines 106 and does not contact the word lines 106, the contact area of the contact to be formed later is too small, which results in a larger contact resistance.

In some embodiments, the formation of the contact openings 120 includes patterning processes, such as photolithography and etching processes. The etching process may comprise a dry etching process, such as Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), inductively coupled plasma etching (inductively coupled plasma etching), suitable etching processes, or combinations thereof.

Next, as shown in fig. 4A and 4B, a spacer material layer 131 is formed on the contact opening 120 and the hard mask layer 110. In some embodiments, the layer of spacer material comprises a dielectric material comprising a nitride or an oxide. In some embodiments, the spacer material layer 131 may be formed by a deposition process or the like as described above.

In one embodiment, Atomic Layer Deposition (ALD) is used to conformally deposit silicon nitride as a spacer material layer, which is dense and not easily etched by the following etchant.

Next, as shown in fig. 5A and 5B, the spacer material layer 131 on the bottom of the contact opening 120 and the hard mask layer 110 is removed, and the remaining spacer material layer 131 on the sidewalls of the contact opening 120 serves as a pair of spacers 132. In some embodiments, the removal of the spacer material layer 131 includes an anisotropic etch process, including, for example, using a dry etch process as described above.

Next, as shown in fig. 6A and 6B, a conductive material 133 is formed on the bottom of the contact opening 120, the spacer 132 and the hard mask layer 110. In some embodiments, the conductive material 133 comprises doped polysilicon, metal, or metal nitride. In some embodiments, the formation of the conductive material 133 includes using the aforementioned deposition process, and thus is not described herein.

In one embodiment, the conductive material 133 is polysilicon with dopants to reduce contact resistance with subsequently formed bit lines. The dopant may comprise an n-type or p-type dopant, such as nitrogen, arsenic, phosphorus, antimony ions or boron, aluminum, gallium, indium, boron trifluoride ions (BF) ³⁺ )。

Next, as shown in fig. 7A and 7B, a portion of the hard mask layer 110, the conductive material 133 and the spacers 132 are removed, the remaining hard mask layer 110 is used as the cap layer 110', the remaining conductive material 133 is used as the contact 134, and the remaining spacers 132 are used as the spacers 136. Specifically, the second oxide layer 116, the conductive material 133, and the spacers 132 on the nitride layer 114 are removed, so that the remaining nitride layer 114, the conductive material 133, and the spacers 132 are coplanar. In fig. 7A and 7B, cap layer 110', spacers 136 are flush with the top surface of contact 134. In some embodiments, the removing comprises performing Chemical Mechanical Polishing (CMP).

Since the contact opening 120 formed in fig. 3A (cross-sectional view along the first direction D1) is located in the active region 102A between the isolation features 104, the spacer 136 in fig. 7A is also located in the active region 102A between the isolation features 104 and does not cross over to the isolation region 102B. Furthermore, in fig. 7A, the contact 134 is laterally spaced from the active region 102A in the semiconductor substrate 102 by a pair of spacers 136 to avoid leakage current.

Since one side of the contact opening 120 formed in fig. 3B (the cross-sectional view along the second direction D2) is located between the edges of one word line 106, the spacer 136 in fig. 7B is also located between the edges of one word line 106 and does not extend beyond the edges of the word line 106. Furthermore, in fig. 7B, the spacer 136 is disposed directly above the wordline 106 and the spacer 136 corresponds to the wordline 106. Specifically, along the vertical direction Z, the spacers 136 are separated from the wordlines 106 by the protective layer 108.

In some embodiments, the ratio of the width WC of the contact 134 to the width WS of the spacer 136 is approximately between 2-10. When the above ratio is less than 2, the contact area of the contact 134 is too small due to the spacer 136 being too thick, which easily causes an increase in contact resistance. When the ratio is greater than 10, the contact 134 is too close to a capacitor contact (not shown) formed subsequently due to the thin spacer 136, which is likely to cause short circuit.

At this point, returning to fig. 1, the contact 134 and the spacer 136 surrounding the contact 134 may be created by the processes described above. That is, the spacer 136 is disposed on the entire sidewall of the contact. Since the spacer material layer 131 is formed on the contact openings 120 in the first direction D1 and the second direction D2 simultaneously in fig. 4A and 4B, the thickness of the spacers 136 in the first direction D1 and the second direction D2 are the same in this embodiment.

Next, reference may be made to FIG. 8. Fig. 8 is a schematic top view of the semiconductor memory structure 100, according to some embodiments of the invention. Referring to fig. 1, fig. 8 illustrates the relative positions of the dielectric liner 150, the contact 134, the spacer 136, and the capacitor contact 170 after the subsequent formation of the dielectric liner 150. It should be noted that fig. 8 shows only a portion of the elements of a Dynamic Random Access Memory (DRAM) to simplify the drawing. The following is a schematic cross-sectional view along the line a-a 'and the line B-B' in fig. 8, so as to illustrate the formation method of the semiconductor memory structure.

Fig. 9A-20A and 9B-20B are cross-sectional views of the semiconductor memory structure 100 formed at various stages in accordance with some embodiments of the present invention, as shown in fig. 2A-7A and 2B-7B. The cross-sectional views of fig. 9A-20A and 9B-20B are taken along the cross-sectional line a-a '(the first direction D1) and the cross-sectional line B-B' (the second direction D2) of fig. 1, and may be referred to as the cross-sectional view of the first direction and the cross-sectional view of the second direction, respectively.

Referring to fig. 7A and 7B, as shown in fig. 9A and 9B, a bit line stack layer 140 is formed on the cap layer 110'. In some embodiments, the bit line stack layer 140 includes

conductive layers

141 and 142 and dielectric layers 143,144, and 145. In some embodiments,

conductive layers

141 and 142 comprise doped polysilicon, metal, or metal nitride, such as tungsten (W), titanium (Ti), and titanium nitride (TiN). In some embodiments, dielectric layers 143,144, and 145 comprise a nitride or an oxide, such as silicon nitride or silicon oxide.

In one specific embodiment, the uppermost dielectric layer 145 is silicon oxide, and the other

dielectric layers

143 and 144 are silicon nitride, to prevent damage to underlying layers (e.g., conductive layers 141 and 142).

In some embodiments, the formation of the bitline stack layer 140 includes a deposition process as described above, and thus is not described herein.

Next, as shown in fig. 10A and 10B, the bit line stack layer 140 is patterned by a patterning process to form a bit line 140'. Specifically, the

conductive layers

141 and 142 and the dielectric layers 143,144, and 145 in the bit line stack layer 140 are etched to form

conductive patterns

141 ' and 142 ' and

dielectric patterns

143 ', 144 ', and 145 '.

Next, in conjunction with fig. 11A-14A and 11B-14B, a dielectric liner 150 (shown in fig. 14A) is formed on the cap layer 110 ' and the bit line 140 ' to isolate the bit line 140 ' from the subsequently formed capacitor contact.

First, in fig. 11A-12A and 11B-12B, a nitride liner 151 is conformally deposited on the sidewalls and top surfaces of the cap layer 110 'and the bit line 140' using a deposition process, followed by conformally depositing an oxide liner 153 on the nitride liner 151 using a deposition process.

Next, in fig. 13A, the nitride material liner 151 and the oxide material liner 153 are etched back, so that the remaining nitride material liner 151 and the oxide material liner 153 can be used as the nitride liner 152 and the oxide liner 154, respectively. In this embodiment, the top surfaces of the nitride liner 152 and the oxide liner 154 are flush with the top surface of the word line 140'. In FIG. 13B, the nitride material liner 151 and the oxide material liner 153 are removed, leaving only the bit lines 140'.

Thereafter, in fig. 14A and 14B, a nitride liner 156 is conformally deposited over the nitride liner 152, the oxide liner 154, and the word line 140 using a deposition process.

Note that in fig. 14A, nitride liner 152, oxide liner 154, and nitride liner 156 are inside-out centered on bit line 140'. By sandwiching the oxide liner 154 between the two

nitride liners

152 and 154, parasitic capacitance between the bit line 140' and a subsequently formed capacitive contact (not shown) is prevented. In an alternative embodiment, the oxide liner 154 may also be replaced by an air gap (air gap).

In some embodiments, since the bit line 140' and the contact opening 120 use inverted mask patterns, the widths of the two are substantially the same. That is, the sidewalls of spacers 136 are substantially flush with the sidewalls of bit lines 140'. Thus, in fig. 14A and 14B, the spacers 136 are seen to be located on the inner side of the dielectric liner 150 along the first direction.

In some embodiments,

nitride liners

152 and 156 comprise silicon nitride and oxide liner 154 comprises silicon oxide. In some embodiments, the deposition process is similar to that described previously and thus is not described in detail herein.

In an exemplary embodiment, in order to form a spacer for separating a contact from a capacitor contact, after forming the contact and a bit line, both sides of the contact are additionally recessed and a trench is formed, so that both sides of the contact are exposed due to the trench; forming an oxide layer using an oxidation process; forming a nitride on the oxide layer; the dielectric liner is formed after phosphoric acid is used to remove excess nitride and the remaining nitride is used as a spacer. However, the above method may affect the profile of the two sides of the contact due to the exposure of the two sides of the contact, and an additional oxidation process is used, thereby increasing the cost and complexity of the process. Moreover, when phosphoric acid is used to remove the excess spacers, the bit lines (e.g., tungsten) are easily damaged, thereby reducing the yield of the semiconductor memory structure.

In contrast, the present embodiment can form the dielectric liner 150 directly after forming the contact 134 and the bit line 140', which not only eliminates the additional step of etching the two sides of the contact, but also does not expose the sidewall of the contact 134, thereby eliminating the step of oxidation process, simplifying the process steps and saving the cost. Furthermore, since the spacers are formed before the contacts are formed in the embodiment, it is not necessary to additionally use phosphoric acid to remove excess nitride in order to form the spacers after the contacts are formed, and thus the

conductive patterns

141 ' or 142 ' in the bit line 140 ' can be prevented from being damaged.

Next, with reference to fig. 15A-20A and 15B-20B, capacitor contacts 170 are formed on the semiconductor substrate 102 and on both sides of the bit lines 140' to facilitate the formation of a subsequent capacitor (not shown). In some embodiments, the capacitive contact 170 includes

conductive layers

172 and 176, and a silicide layer 174 between the

conductive layers

172 and 176.

It should be noted that there are no significant structural changes in the cross-sections of fig. 15B-20B, and therefore the focus is on the cross-sectional structures of fig. 15A-20A described later herein.

In fig. 15A, the cap layer 110' and the semiconductor substrate 102 are recessed along the sidewalls of the dielectric liner 150 using an etch-back process to form an opening 160. The photolithography and etching processes used in this embodiment are similar to those described above and thus are not described in detail herein.

In fig. 16A, a conductive material 171 is formed in the opening 160 and on the semiconductor substrate 102. In some embodiments, the conductive material 171 comprises doped polysilicon, metal, or metal nitride.

In fig. 17A, conductive material 171 is etched back to form conductive layer 172. In fig. 18A, a silicide layer 174 is formed over the conductive layer 172. In some embodiments, the silicide layer 174 comprises silicon cobalt silicide (CoSi) to reduce contact resistance. The formation of the silicide layer 174 may include depositing a metal (e.g., cobalt) on the conductive layer 172, performing an annealing process on the metal, and removing an unreacted portion of the metal by a wet etching process to form the silicide layer 174.

In fig. 19A, a conductive material 175 is formed over the silicide layer 174. In some embodiments, the conductive material 175 comprises doped polysilicon, metal, or metal nitride. In fig. 20A, conductive material 175 is etched back to form conductive layer 176.

In some embodiments, centered on contact 134, extending outward are spacer 136, cap layer 110', and capacitor contact 170, respectively. That is, the contact 134 is laterally spaced from the cap layer 110' and the capacitor contact 170 by the spacer 136 to more effectively avoid leakage current.

In some embodiments, the semiconductor substrate 102 under the contact 134 has a doped region (not shown) therein, which can serve as a source, and the semiconductor substrate 102 under the capacitor contact 170 also has a doped region (not shown) therein, which can serve as a drain. In any active region 102A extending along the third direction D3, the capacitor contact 170, the word line 106, the contact 134, the word line 106, and the capacitor contact 170 are arranged in sequence to serve as a drain, a gate, a source, a gate, and a drain, respectively, in conjunction with fig. 8. That is, two sets of transistor structures in the active region 102A share the same source, which can save the manufacturing cost by more efficient layout.

It should be appreciated that additional components, such as capacitors, metal layers, etc., may still be formed after the formation of the capacitive contact 170 to complete the fabrication of a memory element, such as a Dynamic Random Access Memory (DRAM).

In summary, in the embodiments of the invention, through the formation sequence of the spacer, the contact and the bit line, the damage of the bit line caused by etching the spacer with phosphoric acid in the formation sequence of the contact, the bit line and the spacer can be avoided, and the step of additionally etching the opening can be omitted. In addition, the embodiment can effectively isolate the contact from the capacitor contact through the spacer. Therefore, the reliability and the manufacturing yield of the semiconductor memory device are improved.

Although the present invention has been described with reference to the above embodiments, it is not intended to limit the invention. Those skilled in the art to which the invention pertains will readily appreciate that numerous modifications and adaptations can be made without departing from the scope of the invention as set forth in the claims below.

Claims

1. A method for forming a semiconductor memory structure, comprising:

providing a semiconductor substrate, wherein a pair of word lines are embedded in an active region of the semiconductor substrate, and the pair of word lines extend along a first direction;

forming a hard mask layer on the semiconductor substrate;

forming a contact opening through the hard mask layer and a portion of the semiconductor substrate corresponding to the pair of word lines;

forming a pair of spacers on sidewalls of the contact opening;

filling a conductive material in the contact opening to form a contact element;

forming a bitline directly over the contact and the pair of spacers, wherein the bitline extends along a second direction, wherein the first direction is perpendicular to the second direction; and

a dielectric liner is formed on the sidewalls of the bit lines.

2. The method of claim 1, wherein sidewalls of the contact are not exposed after the step of forming the bit line and before the step of forming the dielectric liner.

3. A semiconductor memory structure, comprising:

a semiconductor substrate having an active region;

a pair of word lines embedded in the active region of the semiconductor substrate, wherein the pair of word lines extend along a first direction;

a cap layer disposed on the semiconductor substrate;

a contact passing through the cap layer and partially disposed in the semiconductor substrate;

a pair of spacers disposed on sidewalls of the contacts and corresponding to the pair of word lines;

a bit line extending along a second direction, wherein the first direction is perpendicular to the second direction, wherein the bit line is disposed directly above the contact and the pair of spacers in a cross-section of the first direction; and

a dielectric liner layer disposed on the sidewalls of the bit lines.

4. The semiconductor memory structure of claim 3, wherein the pair of spacers do not exceed edges of the word line in a cross section along the second direction.

5. The semiconductor memory structure according to claim 3, wherein the pair of spacers are disposed directly above the pair of word lines in a cross section along the second direction.

6. The semiconductor memory structure of claim 3, wherein the semiconductor substrate further comprises an isolation region surrounding the active region, and wherein the pair of spacers are located in the active region between the isolation regions and do not cross over to the isolation region in a cross section along the first direction.

7. The semiconductor memory structure of claim 3, wherein the pair of spacers are located inside the dielectric liner layer in the first direction on a cross section along the first direction.

8. The semiconductor memory structure of claim 3, wherein the pair of spacers are disposed on an entire sidewall of the contact.

9. The semiconductor memory structure of claim 3, wherein the dielectric liner comprises a pair of nitride liners and an oxide liner, wherein the oxide liner is sandwiched between the pair of nitride liners.

10. The semiconductor memory structure of claim 3, further comprising:

a capacitor contact disposed on the sidewall of the dielectric liner and on the cap layer, wherein the contact is laterally spaced from the cap layer and the capacitor contact by the pair of spacers.