CN116614746A - Audio driving circuit, method, chip and audio playing device - Google Patents

Abstract

The application discloses an audio driving circuit, an audio driving method, a chip and audio playing equipment, wherein the audio driving circuit comprises a processor, a calibration module and a driving module; the processor is connected between the driving module and the calibration module and is used for extracting offset voltage deviation in a mute section of the audio output by the driving module and sending the offset voltage deviation to the calibration module; the calibration module is connected between the processor and the driving module and is used for accessing initial audio, calibrating the initial audio by adopting the offset voltage deviation to obtain a calibration signal, and transmitting the calibration signal to the driving module; and the input end of the driving module is connected with the calibration module and is used for performing audio driving by adopting the calibration signal and outputting the driven audio. The application can eliminate noise such as pop sound of the mute section in the initial audio and improve the hearing experience in the mute environment.

Description

Audio driving circuit, method, chip and audio playing device

Technical Field

The application relates to the technical field of circuits, in particular to an audio driving circuit, an audio driving method, a chip and audio playing equipment.

Background

The audio driving circuit is an important component of audio playing equipment such as headphones and/or sound equipment, and has a determining function on the audio quality played by the audio playing equipment. Taking a basic audio driving architecture of the mono channel shown in fig. 1a as an example, the audio driving circuit may include a digital-to-analog converter (DAC shown in fig. 1 a) and a driving module (PA shown in fig. 1 a), where the digital signal data stream generates an analog output signal through the digital-to-analog converter, and then sends the analog output signal to an input INP/INN of the audio driving module to generate an output OUTP/OUTN, and the output drives an external speaker, so that the speaker plays the corresponding audio. Ideally, when the audio digital-to-analog converter and the driving circuit are turned on, the output voltages of the output ports OUTP/OUTN are the same, as shown in (1) ideal case in fig. 1 b; however, as shown in the actual situation of (2) in fig. 1b, in the actual situation, due to the gaussian random deviation existing in the corresponding circuit in the chip, the dc offset Vos will be generated in the digital-to-analog converter and the driving circuit, when the digital-to-analog converter and the driving circuit are turned on, the output voltages of OUTP and OUTN are not equal, and as in the actual situation of (2) in fig. 1b, there is a certain dc offset voltage Δv. Therefore, at the moment of turning on the audio digital-to-analog converter and the driving circuit, the dc offset voltage Δv acts on the speaker, resulting in noise (e.g., pop sound) during audio playing.

Although the conventional scheme adopts the related art to calibrate the input initial audio signal, the calibration effect is limited and the calibration process is complex.

Disclosure of Invention

In view of the above, the present application provides an audio driving circuit, method, chip and audio playing device, so as to solve the problems of limited calibration effect and complex calibration process in the audio signal calibration scheme of the conventional scheme.

The application provides an audio driving circuit which comprises a processor, a calibration module and a driving module, wherein the calibration module is used for calibrating the processor;

the processor is connected between the driving module and the calibration module and is used for extracting offset voltage deviation in a mute section of the audio output by the driving module and sending the offset voltage deviation to the calibration module;

the calibration module is connected between the processor and the driving module and is used for accessing initial audio, calibrating the initial audio by adopting the offset voltage deviation to obtain a calibration signal, and transmitting the calibration signal to the driving module;

and the input end of the driving module is connected with the calibration module and is used for performing audio driving by adopting the calibration signal and outputting the driven audio.

Optionally, the audio driving circuit further comprises an analog-to-digital converter, a first switch assembly and a second switch assembly;

The input end of the analog-to-digital converter is connected with the output end of the driving module through the first switch component and the second switch component respectively, the output end of the analog-to-digital converter is connected with the input end of the processor, and the analog-to-digital converter is used for acquiring a first acquisition signal when the first switch component is conducted, sending the first acquisition signal to the processor, acquiring a second acquisition signal when the second switch component is conducted, and sending the second acquisition signal to the processor; the first acquisition signal is used for superposing positive offset voltage deviation on the basis of a common-mode voltage, and the second acquisition signal is used for superposing negative offset voltage deviation on the basis of the common-mode voltage;

the processor is used for determining the offset voltage deviation according to the first acquisition signal and the second acquisition signal.

Optionally, the processor is configured to extract a dc component of the first collected signal to obtain a first dc signal, extract a dc component of the second collected signal to obtain a second dc signal, and determine the offset voltage deviation according to the first dc signal and the second dc signal.

Optionally, the first direct current signal includes: data1 = VCM + Vos, the second direct current signal comprising: data2 = VCM-Vos; the offset voltage deviation includes: vos= (data 1-data 2)/2; wherein, data1 represents a first direct current signal, data2 represents a second direct current signal, VCM represents a common mode voltage, and Vos represents offset voltage deviation.

Optionally, the driving module includes a first audio end for outputting a positive output signal and a second audio end for outputting a negative output signal; the first switch assembly comprises a first sub-switch and a second sub-switch, and the second switch assembly comprises a third sub-switch and a fourth sub-switch;

the first input end of the analog-to-digital converter is connected with the second audio end through the first sub-switch, is connected with the first audio end through the third sub-switch, and the second input end of the analog-to-digital converter is connected with the second audio end through the fourth sub-switch, and is connected with the first audio end through the second sub-switch.

Optionally, the audio driving circuit further comprises a digital-to-analog converter; the calibration module comprises a first adder and a second adder;

the input end of the digital-to-analog converter is connected with the initial audio frequency, the first output end of the digital-to-analog converter is connected with the first input end of the first adder, and the second output end of the digital-to-analog converter is connected with the first input end of the second adder; the second input end of the first adder is connected with the output end of the processor, and the output end of the first adder is connected with the first input end of the driving module; and a second input end of the second adder is connected with an output end of the processor, and an output end of the second adder is connected with a second input end of the driving module.

Optionally, the driving module comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a first amplifier and a second amplifier;

the grid electrode of the first MOS tube is connected with one input end of the first adder, the source electrode of the first MOS tube is respectively connected with one output end of the first adder, the source electrode of the second MOS tube and the drain electrode of the third MOS tube, and the drain electrode of the first MOS tube is respectively connected with the other output end of the first adder, the drain electrode of the fourth MOS tube and the first input end of the first amplifier; the grid electrode of the second MOS tube is connected with one input end of the second adder, the source electrode of the second MOS tube is connected with one output end of the second adder, and the drain electrode of the second MOS tube is respectively connected with the other output end of the second adder, the drain electrode of the fifth MOS tube and the second input end of the first amplifier; the grid electrode of the third MOS tube is connected with an internal reference voltage, and the source electrode of the third MOS tube is connected with an external power supply end; the grid electrode of the fourth MOS tube is connected with the grid electrode of the fifth MOS tube, and the source electrode of the fourth MOS tube is grounded; the source electrode of the fifth MOS tube is grounded; the first output end of the first amplifier is connected with the first input end of the second amplifier, and the second output end of the first amplifier is connected with the second input end of the second amplifier; the first output end of the second amplifier is the first audio end, and the second output end is the second audio end.

Optionally, each adder includes a plurality of logic control units connected in parallel, each logic control unit includes two logic control ends, and each logic control end is respectively used for accessing the coding signal sent by the processor to control the channel of each MOS tube in the driving module, and calibrate the initial audio.

Optionally, the logic control unit includes a plurality of MOS tube groups connected in parallel; each MOS tube group is respectively connected with two high-order control bits and one low-order control bit corresponding to the coding signals.

Optionally, the MOS tube group includes a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, and a ninth MOS tube;

the grid electrode of the sixth MOS tube is connected with a high-order control bit, the source electrode of the sixth MOS tube is connected with an output end of the corresponding adder, and the drain electrode of the sixth MOS tube is connected with the source electrode of the seventh MOS tube; the grid electrode of the seventh MOS tube is connected with a low-order control bit, and the drain electrode of the seventh MOS tube is respectively connected with the source electrode of the eighth MOS tube and the drain electrode of the ninth MOS tube; the grid electrode of the eighth MOS tube is connected with the offset voltage deviation, and the drain electrode of the eighth MOS tube is connected with the other output end of the corresponding adder; and the grid electrode of the ninth MOS tube is connected with another high-order control bit, and the source electrode of the ninth MOS tube is connected with one output end of the corresponding adder.

The application also provides an audio driving method, which comprises the following steps:

extracting offset voltage deviation in a mute section of the output audio;

calibrating the initial audio frequency by adopting the offset voltage deviation to obtain a calibration signal;

and adopting the calibration signal to carry out audio driving.

Optionally, extracting offset voltage deviation in the mute section of the output audio includes:

sequentially extracting a first acquisition signal and a second acquisition signal from a mute section of the output audio; the first acquisition signal is used for superposing positive offset voltage deviation on the basis of a common-mode voltage, and the second acquisition signal is used for superposing negative offset voltage deviation on the basis of the common-mode voltage;

and determining the offset voltage deviation according to the first acquisition signal and the second acquisition signal.

Optionally, the determining the offset voltage deviation according to the first acquisition signal and the second acquisition signal includes:

extracting a direct current component of the first acquisition signal to obtain a first direct current signal;

extracting a direct current component of the second acquisition signal to obtain a second direct current signal;

and determining the offset voltage deviation according to the first direct current signal and the second direct current signal.

The application also provides an audio driving chip which comprises any one of the audio driving circuits.

The application also provides audio playing equipment, which comprises any one of the audio driving chips.

Optionally, the audio playing device further comprises a playing component; the first input end of the playing component is connected with the first audio end, and the second input end of the playing component is connected with the second audio end.

According to the audio driving circuit, the method, the chip and the audio playing equipment, the processor can extract offset voltage deviation in the mute section of the output audio, the offset voltage deviation is sent to the calibration module, the calibration module calibrates the mute section in the initial audio by adopting the offset voltage deviation, and the obtained calibration signal is sent to the driving module, so that the driving module performs audio driving by adopting the calibration signal, noise such as pop sound of the mute section in the initial audio can be eliminated, and hearing experience under a mute environment is improved; the process of calibrating the initial audio mute section by adopting offset voltage deviation can be overlapped in the corresponding analog circuit, so that the calibration process can be simplified, and the calibration efficiency can be improved; the whole audio driving process does not need to sample VCM (common mode voltage), so that the corresponding circuit structure can be simplified, and the power consumption is reduced. The driving module performs audio driving through a plurality of simple devices such as MOS tubes and amplifiers, and has the advantages of simple structure, high reliability and good driving effect. The calibration module carries out logic control on the MOS tube of the driving module through a plurality of logic control units connected in parallel so as to realize addition and/or subtraction operation, and on the basis of simplifying the circuit structure, the corresponding operation process can be simplified, and the power consumption generated in the operation process is reduced. Therefore, the audio driving circuit can conveniently improve the audio driving effect, and simplify the structure and the driving process of the audio driving circuit, so that the corresponding power consumption is reduced, and the playing quality of the corresponding audio playing equipment is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1a is a schematic diagram of an audio driver chip according to a conventional scheme;

FIGS. 1b, 1c and 1d are schematic diagrams illustrating an analysis of an audio driving process according to a conventional scheme;

FIG. 1e is a schematic diagram of another audio driver chip according to a conventional scheme;

FIG. 2 is a schematic diagram of an audio driving circuit according to an embodiment of the application;

FIG. 3 is a schematic diagram of an audio driving circuit according to another embodiment of the present application;

FIG. 4 is a schematic diagram of an audio driving circuit according to another embodiment of the present application;

FIG. 5 is a schematic diagram illustrating an audio driving circuit according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a driving module according to an embodiment of the application;

FIG. 7 is a schematic diagram of an adder according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a logic control unit according to an embodiment of the present application;

Fig. 9 is a schematic view of a MOS tube group structure according to an embodiment of the present application;

fig. 10 is a schematic diagram of an audio playing device according to an embodiment of the present application.

Detailed Description

The inventor researches an initial audio signal calibration scheme and finds that the related Gaussian random deviation existing in a circuit in a reduction chip is reduced, as shown in (1) in fig. 1c, so that the influence of the Gaussian random deviation is reduced; the direct reduction of gaussian random bias requires a large area and power consumption, and it is difficult to reduce the offset voltage to be achieved due to the irregularity of the chip layout. As shown in fig. 1c (2), the voltage difference is slowly built up, and most of the signal energy of the voltage difference does not fall in the range of 20 to 20khz and is not in the audible range of human ears due to the slow build-up, so that abnormal sounds cannot be heard; however, this approach may result in a long turn-on time of the audio digital-to-analog converter and the driving circuit, which is disadvantageous for use scenarios requiring a fast response.

The other solution is to use self-zeroing (auto zero) technology or chopper (chop) technology to realize very low offset voltage, as shown in fig. 1d, dynamically store the offset voltage of the circuit at the output end of the operational amplifier by self-zeroing technology, and superimpose the stored information on the output signal to complete conversion; the chopper technology dynamically exchanges an input port of the operational amplifier to shift the offset voltage to high frequency and change the offset voltage into a high-frequency signal; both of these techniques generate a certain high frequency energy at the output, require a certain filter circuit, and require an additional clock signal, increasing the complexity of the circuit.

Still other solutions employ calibration techniques, such as the digital domain calibration technique shown in fig. 1 e. In the chip where the audio driving circuit is located, a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC) are typically combined together to implement the recording and playback functions of the audio system, and this solution uses the analog-to-digital converter on the system. In the calibration state, the digital input signal is 0, firstly, an analog signal (vcm+vos) output by the driving circuit is input to the analog-to-digital converter to be converted into a digital signal, the digital signal data 1=vcm+vos is obtained through the data processing module, then the input of the analog-to-digital converter is cut into a common mode signal VCM of the digital-to-analog converter to be converted into a digital signal, the direct signal data 2=vcm is obtained through the data processing module, and the two digital signal data are subtracted to obtain data dcal=vos of offset voltage and stored in the chip. In a normal use state, the digital signal is superimposed with the stored offset voltage signal dcal to offset the offset voltage in the path, so that the offset voltage output by the driving circuit is 0. The offset voltage signal in this way carries out addition, subtraction, multiplication and division operation on the digital signal, and calibration is completed in the digital domain.

The inventors analyzed various solutions and further found that: 1. when the digital signal input in the initial audio signal is 0, i.e. no playing signal is generated, a certain offset voltage signal is superimposed on the playing signal, so that a certain voltage is arranged on the output of a digital-to-analog converter (DAC), a certain amount of noise of the digital-to-analog converter can reach the output end of a driving circuit through a driving module (PA), a certain noise is arranged on the output, and the hearing experience is deteriorated in a mute environment; 2. in order to solve the problem at the 1 st point, the digital signal superposition offset voltage signal needs a certain fade-in fade-out in the starting and closing process, otherwise, a certain pop sound exists in the starting and closing process, the process causes the increase of software cost, and the quick response effect cannot be achieved; 3. because the analog-to-digital conversion needs to be performed on the VCM (common mode voltage) in the calibration process, the VCM needs to be sampled, so that the VCM needs to have driving capability, the requirement of the VCM becomes high, and the power consumption is increased.

Based on the technical problems, in the audio driving circuit, the method, the chip and the audio playing equipment provided by the application, the processor can extract offset voltage deviation in a mute section of output audio, the offset voltage deviation is sent to the calibration module, the calibration module calibrates initial audio by adopting the offset voltage deviation, and the obtained calibration signal is sent to the driving module, so that the driving module performs audio driving by adopting the calibration signal, noise such as pop sound of the mute section in the initial audio can be eliminated, and listening experience under a mute environment is improved; the process of calibrating the initial audio frequency by adopting offset voltage deviation can be overlapped in the corresponding analog circuit, so that the calibration process can be simplified, and the calibration efficiency can be improved; the whole audio driving process does not need to sample the VCM, so that the corresponding audio driving circuit structure can be simplified, and the power consumption generated in the audio driving process is reduced.

The following description of the embodiments of the present application will be made in detail and with reference to the accompanying drawings, wherein it is apparent that the embodiments described are only some, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application. The various embodiments described below and their technical features can be combined with each other without conflict.

A first aspect of the present application provides an audio driver circuit, as shown with reference to fig. 2, comprising a processor 110, a calibration module 200 and a driver module 300; specifically, the first input end of the calibration module 200 is connected to the initial audio, the output end is connected to the input end of the driving module 300, the second input end is connected to the output end of the processor 110, and the input end of the processor 110 is connected to the output end of the driving module 300; the output terminal of the driving module 300 outputs audio, which may also be referred to as an audio output terminal of a corresponding audio driving circuit.

The processor 110 is connected between the driving module 300 and the calibration module 200, and is configured to extract offset voltage deviation in a mute section of the audio output by the driving module 300, and send the offset voltage deviation to the calibration module 200;

The calibration module 200 is connected between the processor 110 and the driving module 300, and is configured to access an initial audio, calibrate the initial audio by using the offset voltage deviation, obtain a calibration signal, and send the calibration signal to the driving module 300;

the input end of the driving module 300 is connected to the calibration module 200, and is configured to perform audio driving by using the calibration signal, and output the audio after driving.

Specifically, the calibration module 200 calibrates the mute segment in the initial audio by using offset voltage deviation to obtain a calibration signal of the mute segment, and sends the calibration signal to the driving module 300, so that the driving module 300 drives the corresponding mute segment by using the calibration signal, and noise such as pop sound of the mute segment is eliminated.

The processor 110 may include logic circuitry capable of signal extraction and/or correlation to extract offset voltage deviations during the silence segments of the output audio. The calibration module 200 may include at least one adder to add or subtract offset voltage deviations from an initial audio frequency to calibrate the initial audio frequency. Optionally, the calibration module 200 may also include logic circuitry capable of implementing corresponding addition and/or subtraction functions to implement the corresponding addition or subtraction functions in the form of logic control.

In the above audio driving circuit, the processor 110 may extract offset voltage deviation in a mute segment of the output audio, send the offset voltage deviation to the calibration module 200, calibrate the initial audio by using the offset voltage deviation, and send the obtained calibration signal to the driving module 300, so that the driving module 300 performs audio driving by using the calibration signal, which can eliminate noise such as pop sound of the mute segment in the initial audio, and improve hearing experience in a mute environment; the process of calibrating the initial audio frequency by adopting offset voltage deviation can be overlapped in the corresponding analog circuit, so that the calibration process can be simplified, and the calibration efficiency can be improved; the whole audio driving process does not need to sample VCM (common mode voltage), so that the corresponding circuit structure can be simplified, and the power consumption is reduced.

In one embodiment, referring to fig. 3, the audio driving circuit further includes an analog-to-digital converter 121, a first switching component (S11 and S12 shown in fig. 3), and a second switching component (S21 and S22 shown in fig. 3); the input end of the analog-to-digital converter 121 is respectively connected to the output end of the driving module 300 through the first switch component and the second switch component, and the output end is connected to the input end of the processor, so as to obtain a first acquisition signal when the first switch component is turned on, send the first acquisition signal to the processor 110, obtain a second acquisition signal when the second switch component is turned on, and send the second acquisition signal to the processor 110; the processor 110 is configured to determine the offset voltage deviation according to the first acquisition signal and the second acquisition signal. The first acquisition signal is used for superposing positive offset voltage deviation on the basis of a common-mode voltage, and the second acquisition signal is used for superposing negative offset voltage deviation on the basis of the common-mode voltage. If the sign of the offset voltage deviation is positive, the positive offset voltage deviation is equal to the offset voltage deviation, the negative offset voltage is equal to the opposite number of the offset voltage deviation, the absolute values of the positive offset voltage deviation and the negative offset voltage deviation are equal, and the sign is opposite, so that the common mode voltage in the first acquisition signal can be eliminated by subtracting the first acquisition signal, and the offset voltage deviation is twice obtained, and the processor 110 can quickly and accurately determine the offset voltage deviation according to the first acquisition signal and the second acquisition signal.

In this embodiment, the processor 110 can determine the offset voltage deviation according to the first acquisition signal and the second acquisition signal through simple addition and subtraction, and has a relatively simple calculation process. The first acquisition signal and the second acquisition signal are digital signals obtained by conversion by the analog-to-digital converter 121, that is, the analog-to-digital converter 121 converts each acquired signal into a corresponding digital signal (such as the first acquisition signal and the second acquisition signal) and then sends the corresponding digital signal to the processor 110 for calculation processing, so that the process of determining offset voltage deviation by the subsequent processor 110 for the first acquisition signal and the second acquisition signal represented in the form of digital signals can be further simplified.

Alternatively, the first switch component and the second switch component may be respectively connected to the processor 110, so that the processor 110 controls the on-off of the first switch component and the second switch component according to specific signal acquisition requirements.

The first switch assembly and the second switch assembly are used for respectively controlling the on-off of the signal acquisition channels corresponding to the output ends of the driving module 300. The inventor has found that, in each signal acquisition path corresponding to the output of the driving module 300, the common-mode voltage VCM is often fixed, and other components (such as offset voltage deviation) in the output audio may be inverted by exchanging the input paths and/or performing time-sharing acquisition, etc. Based on this finding, the present embodiment can acquire the first acquisition signal vcm+v ' when the first switching element is turned on, and acquire the second acquisition signal VCM-V ' when the second switching element is turned on, where V ' is other components than the common mode voltage VCM in the signals acquired by the respective signal acquisition paths. After each path of acquisition signals acquired when the first switch component and the second switch component are respectively connected are obtained, the first acquisition signal and the second acquisition signal are subjected to addition and subtraction and the like simple operation, so that the common-mode voltage VCM in the whole acquisition signal can be eliminated, and other components are obtained.

Specifically, the processor 110 is configured to extract a dc component of the first collected signal to obtain a first dc signal, extract a dc component of the second collected signal to obtain a second dc signal, so that the extracted first dc signal and second dc signal only include a common-mode voltage VCM and an offset voltage deviation Vos, and determine the offset voltage deviation according to the first dc signal and the second dc signal, so that the offset voltage deviation can be obtained by performing simple addition and subtraction operation on the first dc signal and the second dc signal, a determining process of the offset voltage deviation can be simplified, and a circuit structure for obtaining the offset voltage deviation is simplified.

Optionally, the processor 110 may perform denoising processing such as low-pass filtering on the first collected signal, extract the first dc signal based on the denoised first collected signal, perform denoising processing such as low-pass filtering on the second collected signal, and extract the second dc signal based on the denoised second collected signal, so as to ensure validity of the obtained first dc signal and second dc signal.

Optionally, the first direct current signal includes: data1 = VCM + Vos, the second direct current signal comprising: data2 = VCM-Vos; the offset voltage deviation includes: vos= (data 1-data 2)/2; wherein, data1 represents a first direct current signal, data2 represents a second direct current signal, VCM represents a common mode voltage, and Vos represents offset voltage deviation.

Specifically, as shown in fig. 3, the driving module 300 includes a first audio terminal for outputting a positive output signal OUTP and a second audio terminal for outputting a negative output signal OUTN; the first switch assembly comprises a first sub switch S11 and a second sub switch S12, and the second switch assembly comprises a third sub switch S21 and a fourth sub switch S22; the first input end of the analog-to-digital converter 121 is connected to the second audio end through the first sub-switch S11, is connected to the first audio end through the third sub-switch S21, and the second input end is connected to the first audio end through the second sub-switch S12, and is connected to the second audio end through the fourth sub-switch S22. As shown in fig. 3, when the first switch component and the second switch component are switched, that is, the first sub-switch S11 and the second sub-switch S12 are turned on, and the first sub-switch S21 and the fourth sub-switch S22 are switched, the analog-to-digital converter 121 switches the input path, that is, the first signal acquisition path turned on by the first switch component is switched to the second signal acquisition path, so that the fast switching between the first signal acquisition path and the second signal acquisition path can be realized by a simple switch structure. In the first acquisition signal corresponding to the first signal acquisition path and the second acquisition signal corresponding to the second signal acquisition path, the common-mode voltage VCM is kept unchanged, and the offset voltage deviation Vos is inverted, even if the first acquisition signal corresponding to the first signal acquisition path includes a positive offset voltage deviation, the second acquisition signal corresponding to the second signal acquisition path includes a negative offset voltage deviation, so that the processor 110 can efficiently obtain the offset voltage deviation Vos by adopting simple add-subtract arithmetic logic.

In one embodiment, referring to fig. 4, the audio driving circuit further includes a digital-to-analog converter 123; the calibration module 200 includes a first adder 210 and a second adder 220; the input end of the digital-to-analog converter 123 is connected to the initial audio frequency, the first output end is connected to the first input end of the first adder 210, and the second output end is connected to the first input end of the second adder 220; a second input end of the first adder 210 is connected to an output end of the processor 110, and an output end is connected to a first input end of the driving module 300; a second input end of the second adder 220 is connected to an output end of the processor 110, and an output end is connected to a second input end of the driving module 300. After the digital-to-analog converter 123 converts the initial audio frequency into the analog signal, the first output end is used for outputting the positive audio information INP, the second output end is used for outputting the negative audio information INN, so that the first adder 210 can perform an addition and/or subtraction operation on the positive audio information INP to calibrate the positive audio information INP to obtain a first calibration signal, and the second adder 220 can perform an addition and/or subtraction operation on the negative audio information INN to calibrate the negative audio information INN to obtain a second calibration signal, where the first calibration signal and the second calibration signal form the calibration signal output by the calibration module 200.

Specifically, the initial audio may be a digital signal, the mute section is a low-level (e.g., the level is 0) section audio in the corresponding digital signal, and when the processor 110 obtains the offset voltage deviation, the digital-to-analog converter 123 may be controlled to stop working, that is, the digital-to-analog converter is not performed on the initial audio, the low-level section audio in the digital signal obtains the first acquisition signal and the second acquisition signal, the offset voltage deviation is determined, and the offset voltage deviation is pre-stored. After obtaining the offset voltage deviation, the processor 110 may turn off the analog-to-digital converter 121, turn on the digital-to-analog converter 123, and also may simultaneously start the first adder 210 and the second adder 220, respectively send the pre-stored offset voltage deviation to the first adder 210 and the second adder 220, so that the digital-to-analog converter 123 converts the initial audio into corresponding analog audio signals, sends positive audio information INP corresponding to the analog audio signals to the first adder 210, sends negative audio information INN to the second adder 220, and the first adder 210 performs an addition and/or subtraction operation on the received positive audio information INP according to the offset voltage deviation, and the second adder 220 performs an addition and/or subtraction operation on the received negative audio information INN according to the offset voltage deviation, so as to calibrate the positive audio information INP and the negative audio information INN respectively, so that the driving module performs a more accurate driving operation. By analogy, the processor 110 may turn off the digital-to-analog converter 123 and turn on the analog-to-digital converter 121 during a mute section (a low level section corresponding to the digital signal) of the initial audio frequency to obtain the first acquisition signal and the second acquisition signal, so as to determine an offset voltage deviation, and pre-store the offset voltage deviation; after obtaining the offset voltage deviation, the analog-to-digital converter 121 is turned off, the digital-to-analog converter 123 is turned on, so that the digital-to-analog converter 123 converts the initial audio into a corresponding analog audio signal, the positive audio information INP corresponding to the analog audio signal is sent to the first adder 210, the negative audio information INN is sent to the second adder 220, and the first adder 210 and the second adder 220 perform addition and/or subtraction operations on the received audio information according to the offset voltage deviation, respectively, so as to calibrate the corresponding audio signals.

Alternatively, the operation of the audio driving circuit may be as shown in fig. 5, including:

s151, the processor judges whether offset voltage deviation is obtained, if yes, step S161 is executed, and if no, step S152 is executed;

s152, turning off the digital-to-analog converter and turning on the analog-to-digital converter at a low level segment in the digital signal;

s153, turning on the first switch assembly, turning off the second switch assembly, and acquiring a first acquisition signal by the analog-to-digital converter;

s154, the processor acquires a first direct current signal in the first acquisition signal;

s155, turning on a second switch assembly, turning off a first switch assembly, and acquiring a second acquisition signal by an analog-to-digital converter;

s156, the processor acquires a second direct current signal in the second acquisition signal;

s157, the processor performs subtraction operation on the first direct current signal and the second direct current signal to obtain an operation result;

s158, the processor judges the sign bit of the operation result, marks the operation result according to the sign bit, and stores the accurate offset voltage deviation; for example, when the operation result is greater than 0, the sign bit is marked as 0, otherwise, the sign bit is marked as 1, so that the pass sign is the positive sign of the identification operation result;

s161, closing the analog-digital converter, starting the digital-analog converter, reading offset voltage deviation in a low level section of the digital signal by the adder, and calibrating a corresponding audio signal;

S162, inputting a high level segment of the digital signal to enable the corresponding audio playing device to play sound.

Optionally, if the processor includes a plurality of storage bits for storing offset voltage deviations, after step S158, the operation of the audio driving circuit may further include:

s159, feeding back the storage bits after the previous calibration to the adder, and repeating the steps S151 to S158 until each storage bit of the processor stores the latest offset voltage deviation, namely, each storage bit is calibrated.

In one example, referring to fig. 6, the driving module 300 includes a first MOS transistor MP1, a second MOS transistor MP2, a third MOS transistor MP3, a fourth MOS transistor MN1, a fifth MOS transistor MN2, a first amplifier 311, and a second amplifier 312; referring to fig. 7, it is shown: the first adder 210 may include a first logic control terminal and a second logic control terminal, and the second adder 220 may include a third logic control terminal and a fourth logic control terminal. Further, the first adder 210 may further include two output terminals (one of which may be characterized by S and the other of which may be characterized by D) and at least one input terminal (e.g., IN); the second adder 220 may also include two outputs (one of which may be characterized by S and the other of which may be characterized by D) and at least one input (e.g., IN).

The gate of the first MOS transistor MP1 is connected to one input end of the first adder 210, so as to access the forward audio information INP output by the digital-to-analog converter 123, the source is respectively connected to the first output end S of the first adder 210 (one output end of the first adder 210), the source of the second MOS transistor MP2, and the drain of the third MOS transistor MP3, and the drain is respectively connected to the second output end D of the first adder 210 (the other output end of the first adder 210), the drain of the fourth MOS transistor MN1, and the first input end of the first amplifier 311; the gate of the second MOS transistor MP2 is connected to one input end of the second adder 220 to access negative audio information INN of the DAC, the source is connected to a first output end S of the second adder 220 (one input end of the second adder 220), the drain is respectively connected to a second output end D of the second adder 220 (the other input end of the second adder 220), the drain of the fifth MOS transistor MN2 and the second input end of the first amplifier 311; the grid electrode of the third MOS tube MP3 is connected with an internal reference voltage VB, and the source electrode is connected with an external power supply end VDDH; the grid electrode of the fourth MOS tube MN1 is connected with the grid electrode of the fifth MOS tube MN2, and the source electrode is grounded; the source electrode of the fifth MOS tube MN2 is grounded; a first output end of the first amplifier 311 is connected to a first input end of the second amplifier 312, and a second output end of the first amplifier 311 is connected to a second input end of the second amplifier 312; the first output terminal of the second amplifier 312 is the first audio terminal, outputs a positive output signal OUTP, and the second output terminal is the second audio terminal, outputs a negative output signal OUTN.

Optionally, as shown in fig. 6, the gate of the fourth MOS transistor MN1 and the gate of the fifth MOS transistor MN2 are further connected to a common mode feedback level, and the corresponding common mode feedback level is a direct current level. The first amplifier 311 and the second amplifier 312 may further include a power terminal and a ground terminal, the power terminals of the two are respectively connected to the external power terminal VDDH, and the ground terminals are grounded. Optionally, the types of each MOS may be selected according to specific requirements, and the corresponding connection relationship may be adaptively adjusted, so that the device has advantages of high reliability and/or small size on the basis of implementing the corresponding driving function, for example, the first MOS transistor MP1, the second MOS transistor MP2, and the third MOS transistor MP3 may be PMOS transistors, so as to simplify the circuit structure; the fourth MOS transistor MN1 and the fifth MOS transistor MN2 may be NMOS transistors, so as to reduce the occupied area and the like. The driving module 300 shown in fig. 6 includes a three-stage op (operational amplifier ), the input stage (first stage) includes a first MOS transistor MP1, a second MOS transistor MP2, a third MOS transistor MP3, a fourth MOS transistor MN1 and a fifth MOS transistor MN2, the input stage is connected to two adders (such as the first adder and the second adder), each adder is controlled by 8 bits of data, the highest bit indicates the enable of the adder, the low 7 bits <6:0> indicates the data size, and each time one bit is turned on, it is equivalent to connecting a small MOS transistor in parallel to the input MOS transistor (such as the first MOS transistor MP1 or the second MOS transistor MP 2) to change the size of the corresponding MOS transistor, which may be equivalent to adding a signal to the input port INP/INN, and performing the addition and/or subtraction operations equivalently. The second stage and the third stage each include an amplifier to amplify a corresponding output signal.

The driving module 300 provided by the example performs audio driving through a plurality of MOS tubes and amplifiers, and has high reliability and good driving effect.

In one example, referring to fig. 7, each adder (such as the first adder 210 and the second adder 220) includes a plurality of logic control units connected in parallel, where the first logic control unit is outlined by a dashed line in fig. 7, each logic control unit includes two logic control ends, and each logic control end is respectively configured to receive the encoded signal sent by the processor 110, and control the channel of each MOS transistor in the driving module according to the corresponding encoded signal, so as to calibrate the initial audio. Specifically, each adder includes one logic control terminal CTTLH and another logic control terminal CTTLL, where one logic control terminal CTTLH may include a 9-bit signal, as shown in fig. 7, and the logic control terminal CTTLH may include a plurality of high-order control bits, such as CTTLH <1:0>, CTTLH <2:1>, and … … CTTLH <8:7>; fig. 7 shows eight logic control units, one logic control terminal CTTLH of the adder includes high-order control bits CTTLH <1:0> of the first logic control unit, high-order control bits CTTLH <2:1>, … … of the second logic control unit, and eighth logic control terminal CTTLH <8:7>. The other logic control end CTTLL of the adder may include a 16-bit signal, and the logic control end CTTLL may be CTTLL <15:0> corresponding to each logic control unit in fig. 7. Optionally, one logic control end CTTLH and the other logic control end CTTLL of the adder control channels of each MOS transistor in the driving module 300 to calibrate the initial audio. Optionally, as shown in fig. 7, the logic control end includes a plurality of control bits to control on-off of the corresponding MOS transistor. The control bits include at least one low-order control bit (e.g., CTTLL <15:0> in FIG. 7, etc., CTTLL <0> in FIG. 8, etc.) and at least one high-order control bit (e.g., CTTLH <1:0> in FIG. 7, etc., CTTLH <1> in FIG. 8, etc.). The control bits have a corresponding relation with ports provided by related MOS tubes in the logic control unit, for example, the control bits can be in one-to-one correspondence with the ports, etc.

Specifically, referring to fig. 8, the logic control unit includes a plurality of MOS tube groups connected in parallel; each MOS tube group is respectively connected with two high-order control bits and one low-order control bit corresponding to the coding signal, that is, the processor 110 performs coding to generate two high-order control bits and one low-order control bit, so as to control the on-off of the corresponding MOS tube group, realize the parallel on-off of the corresponding MOS tube (such as the eighth MOS tube MP 8) and the input MOS tube (such as the first MOS tube MP1 or the second MOS tube MP 2), and realize the corresponding addition and/or subtraction operation. In fig. 8, a first MOS tube set is shown by a dashed line, where each MOS tube set is connected to two encoded high-level control bits, for example, a gate of a sixth MOS tube MP6 of the first MOS tube set is connected to one high-level control bit CTTLH <1>, a gate of a ninth MOS tube MP9 is connected to another high-level control bit CTTLH <0>, and a gate of a seventh MOS tube MP7 of the first MOS tube set is connected to one low-level control bit CTTLL <0>, so as to control parallel connection and disconnection between an eighth MOS tube MP8 and an input MOS tube (for example, the first MOS tube MP1 or the second MOS tube MP 2). Optionally, in the logic control unit, the number of groups of MOS tube groups is equal to the total number of bits of the low-order control bits, so that each low-order control bit can respectively correspond to one group of MOS tube groups, and specifically can correspond to the gate of the seventh MOS tube MP7 in the corresponding group of MOS tube groups. One set of MOS tube sets may correspond to two high-level control bits, as shown in FIG. 8, the gate of the sixth MOS tube MP6 of the first MOS tube set corresponds to one high-level control bit CTTLH <1>, the gate of the ninth MOS tube MP9 corresponds to the other high-level control bit CTTLH <0>, and so on. Here, fig. 8 is a schematic diagram showing a specific structure of each logic control unit shown in fig. 7, and the high-order control bits of one logic control unit in fig. 7 may include two high-order control bits shown in fig. 8, where CTTLH <1:0> in fig. 7 includes CTTLH <1> and CTTLH <0> in fig. 8. The lower control bits CTTLL <15:0> in FIG. 7 include 16-bit signals, and as shown in FIG. 8, CTTLL <15:0> includes CTTLL <0>, CTTLL <1>, … …, CTTLL <15>.

Optionally, referring to fig. 9, the MOS tube group includes a sixth MOS tube MP6, a seventh MOS tube MP7, an eighth MOS tube MP8, and a ninth MOS tube MP9; the grid electrode of the sixth MOS tube MP6 is connected with a high-order control bit, the source electrode is connected with an output end S of the corresponding adder, and the drain electrode is connected with the source electrode of the seventh MOS tube MP 7; the grid electrode of the seventh MOS tube MP7 is connected with a low-order control bit, and the drain electrode is respectively connected with the source electrode of the eighth MOS tube MP8 and the drain electrode of the ninth MOS tube MP9; the gate of the eighth MOS transistor MP8 is connected to the input signal IN, that is, an output signal (such as positive audio information INP or negative audio information INN) of one end of the DAC, and the drain is connected to the other output end D of the corresponding adder; and the grid electrode of the ninth MOS tube MP9 is connected with another high-order control bit, and the source electrode is connected with an output end S. The sixth MOS transistor MP6, the seventh MOS transistor MP7, and the ninth MOS transistor MP9 together control connection or disconnection between the output end S of the eighth MOS transistor MP8 and the source end of the input MOS transistor (e.g., the first MOS transistor MP1 or the second MOS transistor MP 2) so as to complete connection or disconnection of the parallel operation and complete addition and subtraction operation.

As shown in fig. 8, in each MOS tube group, the sixth MOS tube MP6, the seventh MOS tube MP7, and the ninth MOS tube MP9 together control connection or disconnection between the output end S of the eighth MOS tube MP8 and the source end of the input MOS tube (e.g., the first MOS tube MP1 or the second MOS tube MP 2) so as to complete connection or disconnection of the parallel operation, and complete addition/subtraction operation.

Specifically, the logic for each adder to implement the corresponding add and/or subtract operation includes: the adder receives a first control logic signal and a second control logic signal from the processor, wherein the first control logic signal and the second control logic signal are all coding signals; the first control logic signal and the second control logic signal are connected to a control logic unit in the adder to control the eighth MOS tube MP8 of the corresponding MOS tube group to be started, so that the first MOS tube MP1 and the second MOS tube MP2 on the driving circuit are equivalent to the parallel connection of the corresponding MOS tubes, the superposition of a signal is equivalent to the equivalent completion of corresponding addition and/or subtraction operation.

According to the audio driving circuit, the processor 110 can extract offset voltage deviation in a mute section of output audio, the offset voltage deviation is sent to the calibration module 200, the calibration module 200 calibrates the mute section in initial audio by adopting the offset voltage deviation, and the obtained calibration signal is sent to the driving module 300, so that the driving module 300 adopts the calibration signal to carry out audio driving, noise such as pop sound of the mute section in the initial audio can be eliminated, and hearing experience in a mute environment is improved; the process of calibrating the initial audio mute section by adopting offset voltage deviation can be overlapped in the corresponding analog circuit, so that the calibration process can be simplified, and the calibration efficiency can be improved; the whole audio driving process does not need to sample VCM (common mode voltage), so that the corresponding circuit structure can be simplified, and the power consumption is reduced. The driving module 300 performs audio driving through a plurality of simple devices such as MOS tubes and amplifiers, and has the advantages of simple structure, high reliability and good driving effect. The calibration module 200 performs logic control on the MOS transistors of the driving module 300 through a plurality of logic control units connected in parallel to implement addition and/or subtraction operation, and on the basis of simplifying the circuit structure, the corresponding operation process can be simplified, and the power consumption generated in the operation process can be reduced. Therefore, the audio driving circuit can conveniently improve the audio driving effect, and simplify the structure and the driving process of the audio driving circuit, so that the corresponding power consumption is reduced, and the playing quality of the corresponding audio playing equipment is improved.

The present application provides, in a first aspect, an audio driving method characterized by comprising:

extracting offset voltage deviation in a mute section of the output audio;

calibrating the initial audio frequency by adopting the offset voltage deviation to obtain a calibration signal;

and adopting the calibration signal to carry out audio driving.

In one embodiment, the extracting offset voltage deviation in the mute section of the output audio includes:

sequentially extracting a first acquisition signal and a second acquisition signal from a mute section of the output audio; the first acquisition signal is used for superposing positive offset voltage deviation on the basis of a common-mode voltage, and the second acquisition signal is used for superposing negative offset voltage deviation on the basis of the common-mode voltage;

and determining the offset voltage deviation according to the first acquisition signal and the second acquisition signal.

Specifically, the determining the offset voltage deviation from the first acquisition signal and the second acquisition signal includes:

extracting a direct current component of the first acquisition signal to obtain a first direct current signal;

extracting a direct current component of the second acquisition signal to obtain a second direct current signal;

and determining the offset voltage deviation according to the first direct current signal and the second direct current signal.

The audio driving method can be implemented by adopting the audio driving circuit provided by any one of the embodiments, and has all the beneficial effects of the audio driving circuit provided by any one of the embodiments, which are not described herein.

The present application provides in a third aspect an audio driver chip comprising an audio driver circuit as provided in any one of the embodiments above.

The audio driving chip performs audio driving by adopting the audio driving circuit provided by any one of the embodiments, has a good driving effect, and has low power consumption in the audio driving process.

A fourth aspect of the present application provides an audio playing device, including an audio driving chip according to any one of the foregoing embodiments.

In one embodiment, the audio playback device further comprises a playback component; the first input end of the playing component is connected with the first audio end so as to receive the positive output signal output by the driving module, and the second input end of the playing component is connected with the second audio end so as to receive the negative output signal output by the driving module, so that the playing component can play corresponding audio.

The playing component may include a speaker and/or a speaker. Specifically, as shown in fig. 10, the above-mentioned audio playing device may be referred to as an audio playing device, where the speaker 510 includes a first input terminal and a second input terminal, and the first input terminal of the speaker 510 is connected to the first audio terminal of the audio driving chip, and the second input terminal is connected to the second audio terminal of the audio driving chip.

According to the audio playing device, the audio driving chip described in any one of the embodiments is adopted to perform audio driving, in initial audio, pop sound and other noise of a mute section are effectively eliminated, a higher playing effect is achieved, the structure and the driving process of the audio driving chip are simplified, the reliability of corresponding audio driving is improved, and power consumption is reduced, so that the reliability of the audio playing device can be improved, and the power consumption of the audio playing device is reduced.

Although the application has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based upon a reading and understanding of this specification and the annexed drawings. The present application includes all such modifications and alterations and is limited only by the scope of the following claims. In particular regard to the various functions performed by the above described components, the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the specification.

That is, the foregoing embodiments of the present application are merely examples, and are not intended to limit the scope of the present application, and all equivalent structures or equivalent processes using the descriptions of the present application and the accompanying drawings, such as the combination of technical features of the embodiments, or direct or indirect application in other related technical fields, are included in the scope of the present application.

In addition, the present application may be identified by the same or different reference numerals for structural elements having the same or similar characteristics. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

The previous description is provided to enable any person skilled in the art to make or use the present application. In the above description, various details are set forth for purposes of explanation. It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes have not been shown in detail to avoid unnecessarily obscuring the description of the application. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

Claims (16)

1. An audio driving circuit is characterized by comprising a processor, a calibration module and a driving module;

the processor is connected between the driving module and the calibration module and is used for extracting offset voltage deviation in a mute section of the audio output by the driving module and sending the offset voltage deviation to the calibration module;

the calibration module is connected between the processor and the driving module and is used for accessing initial audio, calibrating the initial audio by adopting the offset voltage deviation to obtain a calibration signal, and transmitting the calibration signal to the driving module;

and the input end of the driving module is connected with the calibration module and is used for performing audio driving by adopting the calibration signal and outputting the driven audio.

2. The audio driver circuit of claim 1, further comprising an analog-to-digital converter, a first switch assembly, and a second switch assembly;

the input end of the analog-to-digital converter is connected with the output end of the driving module through the first switch component and the second switch component respectively, the output end of the analog-to-digital converter is connected with the input end of the processor, and the analog-to-digital converter is used for acquiring a first acquisition signal when the first switch component is conducted, sending the first acquisition signal to the processor, acquiring a second acquisition signal when the second switch component is conducted, and sending the second acquisition signal to the processor; the first acquisition signal is used for superposing positive offset voltage deviation on the basis of a common-mode voltage, and the second acquisition signal is used for superposing negative offset voltage deviation on the basis of the common-mode voltage;

The processor is used for determining the offset voltage deviation according to the first acquisition signal and the second acquisition signal.

3. The audio driver circuit of claim 2, wherein the processor is configured to extract a dc component of the first collected signal to obtain a first dc signal, extract a dc component of the second collected signal to obtain a second dc signal, and determine the offset voltage deviation based on the first dc signal and the second dc signal.

4. The audio driver circuit of claim 3, wherein the first dc signal comprises: data1 = VCM + Vos, the second direct current signal comprising: data2 = VCM-Vos; the offset voltage deviation includes: vos= (data 1-data 2)/2; wherein, data1 represents a first direct current signal, data2 represents a second direct current signal, VCM represents a common mode voltage, and Vos represents offset voltage deviation.

5. The audio driver circuit of claim 2, wherein the driver module includes a first audio terminal for outputting a positive output signal and a second audio terminal for outputting a negative output signal; the first switch assembly comprises a first sub-switch and a second sub-switch, and the second switch assembly comprises a third sub-switch and a fourth sub-switch;

The first input end of the analog-to-digital converter is connected with the second audio end through the first sub-switch, is connected with the first audio end through the third sub-switch, and the second input end of the analog-to-digital converter is connected with the second audio end through the fourth sub-switch, and is connected with the first audio end through the second sub-switch.

6. The audio driver circuit of claim 2, further comprising a digital-to-analog converter; the calibration module comprises a first adder and a second adder;

the input end of the digital-to-analog converter is connected with the initial audio frequency, the first output end of the digital-to-analog converter is connected with the first input end of the first adder, and the second output end of the digital-to-analog converter is connected with the first input end of the second adder; the second input end of the first adder is connected with the output end of the processor, and the output end of the first adder is connected with the first input end of the driving module; and a second input end of the second adder is connected with an output end of the processor, and an output end of the second adder is connected with a second input end of the driving module.

7. The audio driver circuit of claim 6, wherein the driver module comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a first amplifier, and a second amplifier;

The grid electrode of the first MOS tube is connected with one input end of the first adder, the source electrode of the first MOS tube is respectively connected with one output end of the first adder, the source electrode of the second MOS tube and the drain electrode of the third MOS tube, and the drain electrode of the first MOS tube is respectively connected with the other output end of the first adder, the drain electrode of the fourth MOS tube and the first input end of the first amplifier; the grid electrode of the second MOS tube is connected with one input end of the second adder, the source electrode of the second MOS tube is connected with one output end of the second adder, and the drain electrode of the second MOS tube is respectively connected with the other output end of the second adder, the drain electrode of the fifth MOS tube and the second input end of the first amplifier; the grid electrode of the third MOS tube is connected with an internal reference voltage, and the source electrode of the third MOS tube is connected with an external power supply end; the grid electrode of the fourth MOS tube is connected with the grid electrode of the fifth MOS tube, and the source electrode of the fourth MOS tube is grounded; the source electrode of the fifth MOS tube is grounded; the first output end of the first amplifier is connected with the first input end of the second amplifier, and the second output end of the first amplifier is connected with the second input end of the second amplifier; the first output end of the second amplifier is the first audio end, and the second output end is the second audio end.

8. The audio driver circuit of claim 7, wherein each adder includes a plurality of logic control units connected in parallel, each logic control unit includes two logic control terminals, each logic control terminal is respectively used for accessing a coding signal sent by a processor to control a channel of each MOS transistor in the driver module, and calibrate the initial audio.

9. The audio driving circuit according to claim 8, wherein the logic control unit includes a plurality of MOS tube groups connected in parallel; each MOS tube group is respectively connected with two high-order control bits and one low-order control bit corresponding to the coding signals.

10. The audio driving circuit according to claim 9, wherein the MOS tube group includes a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, and a ninth MOS tube;

the grid electrode of the sixth MOS tube is connected with a high-order control bit, the source electrode of the sixth MOS tube is connected with an output end of the corresponding adder, and the drain electrode of the sixth MOS tube is connected with the source electrode of the seventh MOS tube; the grid electrode of the seventh MOS tube is connected with a low-order control bit, and the drain electrode of the seventh MOS tube is respectively connected with the source electrode of the eighth MOS tube and the drain electrode of the ninth MOS tube; the grid electrode of the eighth MOS tube is connected with the offset voltage deviation, and the drain electrode of the eighth MOS tube is connected with the other output end of the corresponding adder; and the grid electrode of the ninth MOS tube is connected with another high-order control bit, and the source electrode of the ninth MOS tube is connected with one output end of the corresponding adder.

11. An audio driving method, comprising:

extracting offset voltage deviation in a mute section of the output audio;

calibrating the initial audio frequency by adopting the offset voltage deviation to obtain a calibration signal;

and adopting the calibration signal to carry out audio driving.

12. The audio driving method according to claim 11, wherein extracting offset voltage deviation in a mute section of the output audio comprises:

sequentially extracting a first acquisition signal and a second acquisition signal from a mute section of the output audio; the first acquisition signal is used for superposing positive offset voltage deviation on the basis of a common-mode voltage, and the second acquisition signal is used for superposing negative offset voltage deviation on the basis of the common-mode voltage;

and determining the offset voltage deviation according to the first acquisition signal and the second acquisition signal.

13. The audio driving method of claim 12, wherein the determining the offset voltage deviation from the first and second acquisition signals comprises:

extracting a direct current component of the first acquisition signal to obtain a first direct current signal;

extracting a direct current component of the second acquisition signal to obtain a second direct current signal;

And determining the offset voltage deviation according to the first direct current signal and the second direct current signal.

14. An audio driver chip comprising an audio driver circuit as claimed in any one of claims 1 to 10.

15. An audio playback device comprising the audio driver chip of claim 14.

16. The audio playback device of claim 15, wherein the audio playback device further comprises a playback component; the first input end of the playing component is connected with the first audio end, and the second input end of the playing component is connected with the second audio end.