CN116601889A - Hybrid scanning apparatus and method for radio electronic device - Google Patents
Hybrid scanning apparatus and method for radio electronic device Download PDFInfo
- Publication number
- CN116601889A CN116601889A CN202180068115.2A CN202180068115A CN116601889A CN 116601889 A CN116601889 A CN 116601889A CN 202180068115 A CN202180068115 A CN 202180068115A CN 116601889 A CN116601889 A CN 116601889A
- Authority
- CN
- China
- Prior art keywords
- machine
- test
- interface
- monitored
- edge connector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B17/00—Monitoring; Testing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/46—Monitoring; Testing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Abstract
Hybrid scanning device for a radio electronic equipment, comprising an electronic computer, at least one control device, at least one response vector memory, at least one test vector memory, at least one edge connector of an object to be monitored, at least one test interface of the object to be monitored, at least one standard interface of the object to be monitored, at least one device for controlling the standard and test interfaces of the object to be monitored, at least one interface of the edge connector of the object to be monitored, at least one device for performing a functional check of the object to be monitored, at least one unit for establishing a model period and for synchronization, at least one standard debug interface and at least one peripheral controller, characterized in that it is configured to be connected to the object to be monitored via the edge connector interface and via the standard and test interfaces of the object to be monitored, wherein the means for controlling the standard and test interfaces are configured to select discrete model periods in the range of 10 picoseconds to 24 hours. In a hybrid scan of a monitored object, first the structure, function and basic circuit of the monitored object or a physical sample of the monitored object is analyzed, then a model of the monitored object is built, which model comprises individual functional clusters, edge connector outputs and programmable element outputs, then a set of test sequences is determined for each cluster according to the functional model of the cluster in question, then test stimuli are delivered through the edge connector and the programmable element outputs, and the condition of the edge connector outputs and the condition of the programmable element outputs are scanned, finally a conclusion is made as to whether the monitored object is working properly.
Description
This group of inventions is due to the automatic control and diagnostic tools of the Radio Electronic Equipment (REEs) of complex machines comprising replaceable functional units; more specifically, this is due to the apparatus and method of controlling the operability of the REEs and diagnosing their faults.
The invention can be used to diagnose conditions of varying complexity of technical systems (e.g. REEs) based on programmable logic integrated circuits or microprocessors, so that their operating algorithms are complex due to the high information capacity of the programmable elements or are partly hidden from the user.
In order to control the operability of the REEs and diagnose their faults, there are various types of technical devices and methods based on the application of digital computing tools, digital metrology instruments, programmable test input sources and implementing automated methods to control the operability of the REEs and diagnose their faults [3].
The REE control and fault diagnosis automation complex exists, and comprises a synchronization unit, a test generation unit, a matching unit and a control computer; the latter is connected with the output and input of the matching unit through the input and output thereof; the matching unit is arranged on an idle slot of a system bus of the control computer; a switchboard is also available, the output group and the input group of which are respectively the output group and the input group for connection to the automatic control and diagnostic complex of the machine; a first output of the test generation unit is connected to a first input of the switchboard; the first output of the synchronization unit is connected to the synchronization input of the test generation unit; the complex is unique in that it further comprises a logic analyzer, a feature analyzer, a digital oscilloscope unit, a programmable power supply unit, a programmable special shape signal generator unit and a local data exchange bus (which connects the matching unit with the test generating unit, the logic analyzer, the feature analyzer, the digital oscilloscope unit, a synchronization unit, a programmable power supply unit, a programmable special shape signal generator unit and a distribution board; the second, third, fourth and fifth outputs of the synchronization unit are connected with the synchronization outputs of the signature analyzer, the digital oscilloscope unit, the logic analyzer and the programmable power supply unit, respectively, the first output of the programmable power supply unit is connected to the second input of the switchboard, the third input of the switchboard is connected to the output of the programmable special shape signal generator unit, the output of the switchboard is connected to the first input of the logic analyzer, the second input of the logic analyzer and the inputs of the signature analyzer and the digital oscilloscope unit are the respective inputs for connection to the automatic control and diagnosis complex of the machine, the outputs of the test generation unit and the programmable power supply unit are the respective outputs for connection to the automatic control and diagnosis complex of the machine, and the information output of the control computer is the output of the complex, furthermore, the switchboard comprises an input group and an output group for connecting the complex to the machine, respectively, an additional input connected with the test generation unit, the programmable power supply unit, the output of the programmable special shape signal generator unit, and it further comprises a separate output connected with the input of the logic analyzer, for transmission of signals from the measurement analyzer to the input of the machine in response to the control mode when the input of the complex is placed into the control of the machine, the switchboard is used to connect the inputs of the measuring units directly to the outputs of the units one by one, to generate the appropriate stimulus according to the instructions from the control computer, or to connect the machine appropriately to the outputs of the stimulus source and to the inputs of the logic analyzer when the complex is in control and diagnostic mode; the control computer of the complex is used for storing a database and software for complex operation, retrieving control software (including reference test) from the database according to the type of the machine, arranging the operation of each component in the complex according to a specified program, recording the test into a buffer memory of a test generating unit, controlling the output of test signals from the test generating unit, controlling the setting of parameters of special shape signals for controlling analog and analog digital circuits, controlling the output of test signals, measuring the parameters of response signals and comparing the response signals with reference signals according to the program, recording the comparison result in each step, analyzing the comparison result of the reference signals and the response signals in each step, generating a positive control result message, transmitting a message describing the fault and fault diagnosis requirement of the machine, outputting instructions according to the diagnostic program for connecting probes of a feature analyzer, a logic analyzer and a digital oscilloscope to relevant intermediate points of a circuit, analyzing the parameters of signals obtained by the feature analyzer, the logic analyzer and the digital oscilloscope so as to identify faults and transmitting detailed descriptions to analyze other parts in the circuit of the machine, controlling the measuring unit (the digital oscilloscope, the logic analyzer and the feature analyzer and the digital oscilloscope) in the digital oscilloscope are connected to the programmable power generating unit by the special shape generating unit; the logic analyzer is provided with a set of "logic 0" and "logic 1" comparators at its outputs and should be used to connect its input circuits to the switchboard output and to the output of the machine through the switchboard, receive a response signal from the output of the machine to the input circuits through the switchboard (where the level of the response signal may be "logic 0" or "logic 1"), identify the response output signal from the machine as either 0 or 1, record these values into the relevant bits in the output registers of the logic analyzer, generate a response code for the input test applied to the machine, and provide operation synchronized with the test generation unit controlled by the synchronization unit. [2]
Drawbacks of this complex in operation include its limited scope of application, the inability to generate tests if the operational algorithms of the product are controlled by programmable components of the product (e.g., FPGA or microprocessor), and thus, the algorithms may be complex or hidden such that it is not possible to find input signal combinations that stimulate the development of the structure and operational algorithms of the generation unit. Programmable elements of a product, such as an FPGA or microprocessor, have a large number of outputs and access to many outputs can be complex; these factors limit the control through internal points using a feature analyzer, logic analyzer, and digital oscilloscope.
A method of generating a diagnostic test exists which is based on the generation of a combination of input test signals (with a specific combination of signal parameters, and a specific application sequence of the input signals corresponding to the application of the input signals during normal operation of an actual product of the appropriate type to be diagnosed), and also on the identification of the parameters of the output signal combination of each input test signal combination, the salient features of which method are as follows: based on the description of the internal components of the related type of product, an equivalent connection reference model should be established; a predefined reference model of a component of a related type of product should be inserted into the gap of the equivalent connection reference model; the appropriate combination of input signals and its sequence corresponding to the actual normal operation of the product to be diagnosed should be applied to the input of the reference model of the resulting product to be diagnosed; for each input signal combination applied, parameters of the response signal combination at the reference model output of the product to be diagnosed and in characteristic intermediate points between the reference models of the product components should be identified; recording parameters of the response signals received from the reference model output and the reference model intermediate points of the product to be diagnosed and parameters of the appropriate input test signals into a database by using a computer; for each condition of the reference model of the product to be diagnosed, the procedure comprising the application of the input test signal and the identification of the parameters of the equivalent output signal should be repeated; the resulting set of input test signals and associated standard equivalent output signals should be used to diagnose the condition of the actual product and to diagnose the failure of the product components. [1]
Drawbacks of this approach include its limited scope of application, the inability to generate tests if the operational algorithms of the product are controlled by programmable components of the product (such as an FPGA or microprocessor), and thus, the algorithms may be complex or hidden so that it is not possible to find the input signal combinations and their order corresponding to the actual normal operation of the product to be diagnosed.
The application technical result of the invention is as follows: allowing a test to be generated for the product so that the operation algorithm of the test is controlled by programmable components such as an FPGA or a microprocessor; allowing the generation of tests using a limited set of functional check tests according to the claimed method for various types of products in various application areas with similar structures; the test development time is shortened; improving diagnostic quality; shortening the diagnosis time of the product.
The technical result is achieved due to the following factors: the hybrid scanning device comprises a computer, at least one control unit, at least one response vector memory, at least one test vector memory, at least one machine edge connector, at least one machine test interface, at least one machine standard interface and machine test interface control unit, at least one machine edge connector interface, at least one machine function verification unit, at least one analog time interval generation and synchronization unit, at least one standard debug interface, at least one peripheral controller, and the remarkable characteristics thereof are as follows: the device has a setting for connecting it to the machine via a machine edge connector interface, a machine standard interface or a machine test interface, the standard interface and the test interface control unit having a setting for setting the discrete analog time interval to be in the range of 10 picoseconds to 24 hours. In the hybrid scanning process of the machine, the structure, function or circuit diagram or physical sample of the machine should be analyzed first; then, building a machine model comprising a functional cluster, an edge connector output and a programmable element output; then, a set of test patterns should be identified for each cluster based on the functional model of each cluster; then, the test input should be applied through the edge connector and output of the programmable element, and the condition of the edge connector output and the condition of the programmable element output should be scanned; finally, a conclusion should be drawn to confirm whether the machine is operating correctly.
Drawings
The concept of the invention is illustrated by the accompanying drawings:
FIG. 1 is a functional diagram of the claimed REE hybrid scanning device;
FIG. 2 is a diagram of a combined unit of the REE hybrid scanning device;
FIG. 3 is a flow chart of the claimed REE hybrid scanning method;
FIG. 4 is an overall block diagram of a machine;
fig. 5 is a time interval layout for application and analysis of test inputs.
The following elements of the combined information input device are shown in the drawings:
1-a computer;
2-a control unit;
3-a response vector memory;
4-test vector memory;
5-machine edge connector;
6-machine;
7-a machine test interface;
8-machine standard interface;
9-a standard interface and test interface control unit;
10-machine edge connector interface;
11-a machine function verification unit;
12-an analog time interval generation and synchronization unit;
13-a standard debug interface for programming the output of the programmable elements of the machine;
14-analyzing a structural, functional or circuit diagram or a physical sample of the machine;
15-building a machine model including functional clusters, edge connector outputs, and programmable element outputs;
16-identifying a set of test patterns for each cluster based on the functional model of each cluster;
17-applying test inputs through the outputs of the edge connector and the programmable element, including a scan of the condition of the edge connector output and the condition of the programmable element output;
18-conclude, confirm whether the machine is operating correctly;
19-programmable element Jn;
20-programmable element J1;
21-a set of peripheral controllers Pm;
22-a set of peripheral controllers P1;
23-machine edge connector S1;
24-machine edge connector Sl;
25-linkage L1;
26-linked Li;
27-a set of functional clusters C1;
28-a set of functional clusters Ck.
Detailed Description
The REE hybrid scanning device comprises a computer (1), at least one control unit (2), at least one response vector memory (3), at least one test vector memory (4), at least one edge connector (5, 23, 24), a machine (6), at least one machine test interface (7), at least one machine standard interface (8), at least one standard interface and test interface control unit (9), at least one machine edge connector interface (10), at least one machine function verification unit (11), an analog time interval generation and synchronization unit (12), at least one standard debug interface (13), at least one peripheral controller (21, 22).
Hybrid scanning method, wherein first the structure, function or circuit diagram of the machine (6) or the physical sample (14) is to be analyzed; then, a model (15) of the machine (6) is built, comprising the functional clusters, the edge connector outputs and the programmable element outputs; then, a set of test patterns (16) should be identified for each cluster based on the functional model of each cluster; then, a test input should be applied through the outputs of the edge connector and the programmable element, including a scan (17) of the condition of the edge connector output and the condition of the programmable element output; finally, a conclusion should be made to confirm whether the machine (6) is operating correctly (18). For these purposes, the discrete analog time interval is a function of the completion time of the transient in the machine (6) due to the application of the test input, which is used to analyze the response of the machine (6), and other time intervals are used to access the elements of the machine (6) through the standard interface (8) and the test interface (7) of the machine (6).
The claimed REE hybrid scanning device operates as follows: the control computer (1) generates an instruction stream for the control unit (2) using a test program; the control unit decodes the instruction stream, executes the instructions, and provides data exchange between the computer (1) and the memory, the test vector memory (4) and the response vector memory (3); an edge connector interface (10) for applying test vectors from the memory (4) to the machine, and machine responses sent from the machine through the edge connector interface (10) for recording into the response vector memory (3); a standard interface and test interface control unit (9) receives instructions and data from the control unit (2) and uses the built-in test interface (7) and standard interface (8) of the machine to analyze the output condition and programming of the programmable elements of the machine; the control unit (2) maps a set of test vectors onto its internal memory to apply these vectors to the machine (6) through the output of the programmable element of the machine, and also maps a set of corresponding vectors into its internal memory from the machine element connected to the programmable element output; the control unit uses the machine edge connector (5) and the standard interface (8) and the test interface (7) to standardize access to the elements of the machine (6).
The combining unit (fig. 2) of the REE hybrid scanning apparatus includes: a machine function verification unit (11) for testing the functional elements, units and clusters of the product; a group of standard debug interfaces (13) for programming outputs of programmable elements of a machine, wherein the group breaks down the structure of the machine by programming the outputs of the programmable elements and providing access to those outputs; an analog time interval generation and synchronization unit (12) providing a synchronous operation of the machine function verification unit (11) and a standard debug interface (13) for programming the output of the programmable element of the machine in an alternating pattern by setting a function verification time interval and a time for programming the output of the programmable element and for structural decomposition of the machine (6). The product testing process is controlled by a control computer (1) according to a specified program.
The REE hybrid scanning device operates as follows: the control computer (1) generates an instruction stream using a test program and arranges data exchange between the machine function verification unit (11), a standard debug interface (13) for programming the output of the programmable elements of the machine and the program; a standard debug interface (13) for programming the output of the programmable elements of the machine breaks down the machine structure (6) into functional elements, units and clusters by controlling the machine test interface (7) and the standard interface (8); the simulation time interval generation and synchronization unit provides operation of the machine function verification unit (11) and the standard debug interface (13) for programming the output of the programmable elements of the machine in an alternating pattern and sets a predetermined simulation time interval; these intervals (completion time control of transients in the machine (6) caused by application of test inputs) are used to analyze the response of the machine (6), access the elements of the machine (6) through the standard interface (8) and the test interface (7), and to verify the functioning of the functional elements, units and clusters of the machine through the outputs of the edge connector (5) of the machine and the programmable elements of the machine, where access to these outputs is provided by the standard debug interface (13) used to program the outputs of the programmable elements of the machine. Thus, it is arranged to subdivide the machine (6) structure into functional elements, units and clusters, and access to these functional elements, units and clusters and edge connectors (5), in order to provide an easy functional test method applicability at a functional level for functional verification of a machine described as a model of the set of functional elements, units and clusters.
The claimed REE hybrid scanning method operates as follows: -analysing a structural, functional or circuit diagram or a physical sample (14) of the machine; -building a machine model comprising functional clusters, edge connector outputs and programmable element outputs (15); identifying a set of test patterns (16) for each cluster based on the functional model of each cluster; applying test inputs through the outputs of the edge connector and the programmable element, including a scan (17) of the condition of the edge connector output and the condition of the programmable element output; it is concluded that the machine is operating correctly (18). The algorithm of this method is shown in fig. 3.
Example 1
The block diagram of the machine (fig. 4) is a general structure of a radio electronic device for information processing, analysis and conversion, comprising programmable elements J1 … … Jn (such as FPGA, microprocessor or programmable controller), a set of peripheral controllers P1 … … Pm (for working with typical (standard) interfaces of ethernet, RS232, USB etc.), a set of clusters of functions C1 … … Ck (where these clusters are combinations of elements providing certain specific data processing functions (such as ROM or RAM, DAC or ADC, bus interfaces, status control and other functions).
The difficulty or impossibility of testing such a structure is due to the complex operation algorithms of the programmable elements of its programmable elements J1 … … Jn due to the high information capacity. However, the individual clusters C1 … … Ck and the links between them may have simple, sometimes standardized, operating algorithms and with digital oscilloscopes for these purposes, standard methods using logic analysis, feature analysis, transient process and state visualization analysis, respectively, are applicable to standardized methods of test arrangement at their functional level. Fig. 2 shows a set of hardware as such a test of the machine function verification unit (11). Thus, to test clusters and links, access through the edge connector and the output of the programmable element may be used.
During the test procedure, the programmable elements are switched to a test mode to make the outputs of these elements and the edge connectors of the device accessible. For an FPGA or microprocessor, the JTAG specification or other debug interface (if available) can be used, if possible, by reprogramming its transients to test mode; for peripheral controllers, an appropriate interface must be used. Fig. 2 shows a set of hardware for controlling the output of a programmable element as a standard debug interface for programming the output of the programmable element of the machine.
For arranging the operation of the hybrid scanning device, an auxiliary unit, an analog time interval generation and synchronization unit (12) is added, which provides the operation of the machine function verification unit (11) and a standard debug interface (13) for programming the output of the programmable elements of the machine in an alternating pattern. For these purposes, a "wait for synchronization event" and a "step ready" signal are added to each element in a set of hardware for the machine function verification unit (11) (the "step ready" signal is generated after one step of applying a test input to the link between clusters); the "wait for sync event" and the "loop ready" signal are added to a set of tools for controlling the outputs of the programmable elements (when all outputs of the programmable elements in the control unit are reprogrammed, the "loop ready" signal is generated). The "step ready" signal terminates the wait state of a standard debug interface (13) for programming the output of the programmable elements of the machine, and the "loop ready" signal terminates the wait state of the machine function verification unit (11). Around the time interval of the "cycle ready" signal, discrete analog time intervals are generated within ±dt for machine response analysis.
To test a product, a set of test vectors is used; these vectors are transferred to the output of the cluster in a functional test step Tf0 … … Tfi (fig. 5). In each step, a cycle Cp00 … … Cpni is generated; they are used to apply and analyze signals from the output of the programmable element. Around time step Tf0 … Tfi, in the range of Tfi-dt … … Tfi+dt, the operation of the cluster is analyzed for correctness, describing the status of the cluster and transient. Thus, a deterministic timing metric is achieved; within the scope of these metrics, correctness analysis is performed for the operation of clusters and the output of links, edge connectors and programmable elements between clusters.
The combination of the output signals from the clusters, the ability to control the output conditions of the programmable elements, and the ability to transmit signals over the communication lines and edge connectors indicate the operability of the product.
Thus, due to the claimed apparatus, functional test methods may be used to prepare diagnostic tests, which may then be used to diagnose overall machine status (pass/fail) and machine faults (including the precise location of the fault).
The claimed apparatus makes it possible to use a program of REE product testing based on a generic functional model of clusters and standardized (in this approach) access to these clusters by programmable elements of the machine.
The claimed test development method provides a functional test method to prepare for the suitability of a diagnostic test, which can then be used to diagnose overall machine status (pass/fail) and machine faults (including the exact location of the fault);
diagnostic tests are developed based on a generic functional model of clusters through standardized (in this approach) access to these clusters by programmable elements of the machine. Furthermore, the nature of the implementation of the method and the effectiveness of the method are largely independent of the structure and operation algorithms of the overall apparatus.
Information sources:
1.Russian Federation Patent RU2261471,Diagnostic Tests Development Method,G06F11/22(2000.01),G05B 23/00(2000.01).
2.Russian Federation Patent RU2257604,Automated Control and Diagnostics Complex(Embodiments)G06F 11/22(2000.01),G05B 23/00(2000.01).
3.Reliability and Effectiveness in Engineering.Reference Book(10volumes).Volume 9.Technical Diagnostics.Editedby V.V.Klyuyev,Moscow:Engineering,1987,p.177-178.
Claims (2)
1. a hybrid scanning device for a radio electronic device, comprising: a computer, at least one control unit, at least one response vector memory, at least one test vector memory, at least one machine edge connector, at least one machine test interface, at least one machine standard interface and machine test interface control unit, at least one machine edge connector interface, at least one machine function verification unit, at least one simulation time interval generation and synchronization unit, at least one standard debug interface, at least one peripheral controller, characterized substantially as follows: the device has a setting for connecting it to the machine via the machine edge connector interface, the machine standard interface or the machine test interface, the standard interface and test interface control unit having a setting for setting a discrete analog time interval in the range of 10 picoseconds to 24 hours.
2. A hybrid scanning method of a radio electronic device, characterized in that the structure, the function or the circuit diagram or the physical sample of the machine should be analyzed first; then, a model of the machine should be built, including functional clusters, edge connector outputs, and programmable element outputs; then, a set of test patterns should be identified for each cluster based on the functional model of each cluster; then, the test inputs should be applied through the outputs of the edge connector and the programmable element, including a scan of the condition of the edge connector output and the condition of the programmable element output; finally, a conclusion should be drawn to confirm whether the machine is operating correctly.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| BY20200250 | 2020-09-03 | ||
| BYA20200250 | 2020-09-03 | ||
| PCT/BY2021/000013 WO2022047567A1 (en) | 2020-09-03 | 2021-07-30 | Hybrid scanning device and method for radioelectronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116601889A true CN116601889A (en) | 2023-08-15 |
Family
ID=80492464
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202180068115.2A Pending CN116601889A (en) | 2020-09-03 | 2021-07-30 | Hybrid scanning apparatus and method for radio electronic device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN116601889A (en) |
| WO (1) | WO2022047567A1 (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2324967C1 (en) * | 2006-10-16 | 2008-05-20 | Федеральное государственное унитарное предприятие "Научно-производственное предприятие "Сигнал" | Soft hardware stand for diagnostics of digital and microprocessor units |
| RU2363975C2 (en) * | 2007-03-23 | 2009-08-10 | Открытое Акционерное Общество "Дольта" | Portable programmable-diagnostics complex |
| RU2504828C1 (en) * | 2012-07-23 | 2014-01-20 | Открытое акционерное общество "Головной центр сервисного обслуживания и ремонта Концерна ПВО "Алмаз-Антей" "Гранит" | System of automatic operability control and fault diagnostics of electronics |
| RU2727334C1 (en) * | 2019-05-07 | 2020-07-21 | Российская Федерация, от имени которой выступает Государственная корпорация по атомной энергии "Росатом" (Госкорпорация "Росатом") | Automated control system for electrical values of electronic equipment |
-
2021
- 2021-07-30 WO PCT/BY2021/000013 patent/WO2022047567A1/en active Application Filing
- 2021-07-30 CN CN202180068115.2A patent/CN116601889A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| WO2022047567A1 (en) | 2022-03-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4709366A (en) | Computer assisted fault isolation in circuit board testing | |
| US5515384A (en) | Method and system of fault diagnosis of application specific electronic circuits | |
| US6487700B1 (en) | Semiconductor device simulating apparatus and semiconductor test program debugging apparatus using it | |
| CA1065062A (en) | Non-logic printed wiring board test system | |
| CN102169846B (en) | Method for writing multi-dimensional variable password in parallel in process of testing integrated circuit wafer | |
| US7047174B2 (en) | Method for producing test patterns for testing an integrated circuit | |
| RU2324967C1 (en) | Soft hardware stand for diagnostics of digital and microprocessor units | |
| GB2186094A (en) | Self diagnostic cyclic analysis testing for lsi/vlsi | |
| WO2022017589A1 (en) | An automated test equipment, a process and a computer program for testing one or more devices under test, wherein different test activities make use of subsets of the device under test resources | |
| US4551837A (en) | High speed operational recurring signature evaluator for digital equipment tester | |
| EP1701173B1 (en) | Error detection in compressed data | |
| CN108319516B (en) | Test system and test method | |
| US20030079165A1 (en) | Effective use of parallel scan for identically instantiated sequential blocks | |
| US20160169954A1 (en) | Method and system for performing electrical tests on complex devices | |
| CN116601889A (en) | Hybrid scanning apparatus and method for radio electronic device | |
| CN103165405A (en) | Mutli-dimensional variable code real-time generation method through general purpose interface bus (GPIB) interface | |
| JP5532134B2 (en) | Semiconductor integrated circuit device, control method thereof, and information processing device | |
| RU2781091C2 (en) | Device and method for hybrid scanning of radio-electronic equipment | |
| US7500165B2 (en) | Systems and methods for controlling clock signals during scan testing integrated circuits | |
| WO2022047566A1 (en) | Hybrid scanning device for radioelectronic equipment | |
| RU2633530C1 (en) | Method and device for automated functional test and fault diagnostics of radioelectronic equipment | |
| RU2261471C1 (en) | Method for forming diagnostical tests | |
| JP3066072U (en) | Semiconductor test equipment | |
| RU157942U1 (en) | HARDWARE AND SOFTWARE COMPLEX FOR SETTING AND TESTS OF A MULTI-CHANNEL COMPUTER BLOCK | |
| Peyyala et al. | Dynamic Simulation of Real-Time Computers thru Field Signal Simulator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |