CN116600565A - Method for manufacturing semiconductor structure and semiconductor structure - Google Patents

Method for manufacturing semiconductor structure and semiconductor structure Download PDF

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Publication number
CN116600565A
CN116600565A CN202310625182.0A CN202310625182A CN116600565A CN 116600565 A CN116600565 A CN 116600565A CN 202310625182 A CN202310625182 A CN 202310625182A CN 116600565 A CN116600565 A CN 116600565A
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China
Prior art keywords
protective layer
dielectric layer
groove structure
substrate
forming
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CN202310625182.0A
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Chinese (zh)
Inventor
郭帅
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202310625182.0A priority Critical patent/CN116600565A/en
Publication of CN116600565A publication Critical patent/CN116600565A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

The embodiment of the disclosure provides a manufacturing method of a semiconductor structure and the semiconductor structure, the manufacturing method of the semiconductor structure comprises the steps of providing a substrate, forming a bit line, a groove structure positioned on the bit line and an active column in the substrate, wherein the active column is arranged at intervals along a first direction and a second direction, and the first direction is intersected with the second direction; adjacent active columns are arranged at intervals on two sides of the groove structure, and bit lines extend along a first direction and are electrically connected with the active columns; forming a protective layer and a first dielectric layer in the groove structure, wherein the first dielectric layer fills the bottom area of the groove structure, and the protective layer at least covers part of the side wall of the groove structure far away from the substrate; and forming a word line extending along the second direction, wherein the word line covers part of the first dielectric layer away from the top surface of the substrate and part of the protective layer.

Description

Method for manufacturing semiconductor structure and semiconductor structure
Technical Field
The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor structure and the semiconductor structure.
Background
Dynamic random access memory (DRAM, dynamic Random Access Memory) is a commonly used semiconductor memory device, consisting of a number of repeated memory cells. Each memory cell typically includes a capacitor and a transistor. The gate of the transistor is connected with the word line, the drain or the source is connected with the bit line or the capacitor, and the voltage information number on the word line can control the transistor to be turned on or turned off, so that the data information in the capacitor is read through the bit line or written into the capacitor through the bit line for storage. In order to reduce the size of the device, crisscrossed word lines and bit lines are generally arranged in the active area of the array arrangement. With the shrinking of device dimensions, the size requirements for structures such as word lines have increased to meet device performance.
Disclosure of Invention
The embodiment of the disclosure provides a manufacturing method of a semiconductor structure and the semiconductor structure, so as to improve the stability of the semiconductor structure and the performance of a device.
According to some embodiments of the present disclosure, an aspect of an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including: providing a substrate, forming a bit line, a groove structure positioned on the bit line and an active column in the substrate, wherein the active column is arranged at intervals along a first direction and a second direction, and the first direction is intersected with the second direction; adjacent active columns are arranged at two sides of the groove structure at intervals, and the bit line extends along the first direction and is electrically connected with the active columns; forming a protective layer and a first dielectric layer in the groove structure, wherein the first dielectric layer fills the bottom area of the groove structure, and the protective layer at least covers part of the side wall of the groove structure far away from the substrate; and forming a word line extending along the second direction, wherein the word line covers part of the first dielectric layer away from the top surface of the substrate and part of the protective layer.
In some embodiments, the process steps of forming the protective layer and the first dielectric layer include: forming a protective layer, wherein the protective layer covers the groove structure; forming a first dielectric film, wherein the first dielectric film fills the groove structure; and removing part of the first dielectric film, wherein the rest of the first dielectric film is used as the first dielectric layer, and the first dielectric layer covers part of the protective layer and part of the substrate.
In some embodiments, the process steps of forming the protective layer and the first dielectric layer include: forming a first dielectric film, wherein the first dielectric film covers the groove structure; removing part of the first dielectric film, and taking the rest of the first dielectric film as the first dielectric layer; and forming the protective layer, wherein the protective layer covers the top surface of the first dielectric layer far away from the substrate and the side wall of the groove structure which is not covered by the first dielectric layer.
In some embodiments, the method of forming the protective layer includes: an initial protective layer is formed first, and rapid heat treatment is carried out on the initial protective layer so as to convert the initial protective layer into the protective layer.
In some embodiments, the material of the first dielectric layer is different from the material of the protective layer, the material of the first dielectric layer is silicon oxide, and the material of the protective layer is α -alumina.
In some embodiments, the rapid thermal processing has an annealing temperature of 900 ℃ to 1000 DEG C
In some embodiments, the method further comprises: and forming a second dielectric layer, wherein the second dielectric layer covers the word line and the residual groove structure.
In some embodiments, the protective layer has a thickness of 1nm to 10nm.
According to some embodiments of the present disclosure, another aspect of embodiments of the present disclosure further provides a semiconductor structure, including: the semiconductor device comprises a substrate, a first substrate and a second substrate, wherein the substrate comprises a bit line, a groove structure and an active column, the groove structure and the active column are positioned on the bit line, the active column is arranged at intervals along a first direction and a second direction, and the first direction is intersected with the second direction; adjacent active columns are arranged at two sides of the groove structure at intervals, and the bit line extends along the first direction and is electrically connected with the active columns; the first dielectric layer is positioned in the groove structure and fills the bottom area of the groove structure, and the protective layer at least covers part of the side wall of the groove structure away from the substrate; and a word line extending along the second direction, wherein the word line covers part of the first dielectric layer away from the top surface of the substrate and part of the protective layer.
In some embodiments, the material of the first dielectric layer is different from the material of the protective layer, the material of the first dielectric layer is silicon oxide, the material of the protective layer is alphA-Alumina, and the thickness of the protective layer is 1nm-10nm.
The technical scheme provided by the embodiment of the disclosure has at least the following advantages:
according to the manufacturing method of the semiconductor structure, the protective layer is formed on the side wall of the part of the active column, and then the word line covering the part of the protective layer is formed. Through being provided with the protective layer, and because protective layer self is difficult to by the sculpture, can effectively avoid active post and protective layer by the sculpture damage in etching process to can guarantee the structural integrity of active post. Meanwhile, the problems of uneven height of the formed word line, inaccurate position of the formed word line and the like caused by etching damage of the active column and the protective layer are avoided, the possibility of communication of source and drain doped regions of the active column caused by uneven height of the word line and inaccurate position of the formed word line is further avoided, occurrence of leakage is reduced, and therefore performance and yield of the semiconductor structure are improved.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise; in order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the conventional technology, the drawings required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.
Fig. 1 is a flow chart illustrating a method for fabricating a semiconductor structure according to an embodiment of the disclosure;
fig. 2 is a top view of a semiconductor structure according to an embodiment of the present disclosure;
FIG. 3 is a cross-sectional view of a semiconductor structure along the A-A1 direction provided in an embodiment of the present disclosure;
fig. 4 is a schematic flow chart corresponding to a method for manufacturing a protective layer and a first dielectric layer according to an embodiment of the disclosure;
fig. 5 to 10 are sectional views along A-A1 corresponding to steps of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;
FIG. 11 is a schematic flow chart of another method for manufacturing a passivation layer and a first dielectric layer according to an embodiment of the disclosure;
fig. 12 to 17 are cross-sectional views along A-A1 corresponding to steps of another method for manufacturing a semiconductor structure according to an embodiment of the present disclosure.
Detailed Description
As known from the background art, with the shrinking of the device size, the size requirements for structures such as word lines are also increased to meet the device performance. Therefore, how to improve the process stability and reduce the process difficulty, and to obtain a uniform and complete word line structure at the same time, is an important technical problem to be solved by those skilled in the art.
Embodiments of the present disclosure will be described in detail below with reference to the attached drawings. However, those of ordinary skill in the art will understand that in the various embodiments of the present disclosure, numerous technical details have been set forth in order to provide a better understanding of the present disclosure. However, the technical solutions claimed in the present disclosure can be implemented without these technical details and with various changes and modifications based on the following embodiments.
Fig. 1 is a flow chart illustrating a method for fabricating a semiconductor structure according to an embodiment of the disclosure, where the method may include:
step S110, providing a substrate, forming bit lines, a groove structure positioned on the bit lines and active columns in the substrate, wherein the active columns are arranged at intervals along a first direction and a second direction, the first direction is intersected with the second direction, adjacent active columns are arranged at intervals on two sides of the groove structure, and the bit lines extend along the first direction and are electrically connected with the active columns.
Referring to fig. 2 and 3, a substrate 100 is provided, and the material of the substrate 100 may be silicon, germanium, silicon germanium, or silicon carbide. Illustratively, the substrate 100 may be silicon-on-insulator (SOI) and germanium-on-insulator (GOI). A bit line 101, a trench structure 102 and an active pillar 103 are formed in a substrate 100, the trench structure being located on the bit line 101, the active pillar 103 being arranged at intervals along a first direction X and a second direction Y, wherein the first direction X intersects the second direction Y.
Adjacent active pillars 103 are disposed at intervals on both sides of the trench structure 102, and the bit line 101 extends along the first direction X and is electrically connected to the active pillars 103. The material of the active pillars 103 may be silicon, germanium, silicon germanium, or silicon carbide. Wherein the substrate 100 and the active pillars 103 may be prepared from the same original substrate.
The active pillar 103 may include a first source-drain doped region 203, a channel region 303, and a second source-drain doped region 403 sequentially connected toward a direction away from the substrate 100, wherein the first source-drain doped region 203, the channel region 303, and the second source-drain doped region 403 may be doped with an N-type element or a P-type element, the N-type element may be a v-group element such As a phosphorus (P) element, a bismuth (Bi) element, an antimony (Sb) element, or an arsenic (As) element, and the P-type element may be a boron (B) element, an aluminum (Al) element, a gallium (Ga) element, or an indium (In) element.
In some embodiments, the conductivity types of the doping elements in the first source drain doping region 203 and the second source drain doping region 403 are the same, and the conductivity types of the doping elements in the channel region 303 and the second source drain doping region 403 are opposite, for example, the first source drain doping region 203 and the second source drain doping region 403 are doped with an N-type doping element, and the channel region 303 is doped with a P-type doping element, so that the transistor formed by the active pillars 103 is a junction transistor. In some embodiments, the conductivity types of the doping elements in the first source drain doping region 203, the second source drain doping region 403, and the channel region 303 are the same, for example, N-type doping elements are doped in the first source drain doping region 203, the second source drain doping region 403, and the channel region 303, so that the transistor formed by the active pillars 103 is a junction-free transistor. Wherein "junction" in "no junction transistor" and "junction with junction transistor" refers to a PN junction.
The bit line 101 contacts the bottom surface of the first source drain doped region 203 of the active pillar 103 to make electrical connection. In some embodiments, the material of the bit line 101 may be a conductive material such as tungsten, tantalum, titanium, tantalum nitride, or titanium nitride, and the conductive material may be deposited in the substrate by a plating or deposition process or the like to form a bit line structure, which is not limited herein.
Step S120, forming a protective layer and a first dielectric layer in the trench structure, wherein the first dielectric layer fills the bottom area of the trench structure, the bottom area of the trench structure refers to the trench structure area between adjacent first source-drain doped areas, and the protective layer at least covers part of the side wall of the trench structure, which is far away from the substrate.
In some embodiments, as shown in fig. 4, the process steps of forming the protective layer and the first dielectric layer may include:
s1211, forming a first dielectric film, wherein the first dielectric film covers the groove structure;
as shown in fig. 5, a first dielectric film 106 is formed, the first dielectric film 106 filling the trench structure 102, and the forming process may include, but is not limited to, physical vapor deposition (Physical Vapor Deposition, PVD), chemical vapor deposition (Chemical Vapor Deposition, CVD), atomic layer deposition (Atomic Layer Deposition, ALD), and the like.
S1212, removing part of the first dielectric film, and taking the rest of the first dielectric film as a first dielectric layer;
as shown in fig. 6, a portion of the first dielectric film 106 is removed, and the remaining first dielectric film 106 is used as the first dielectric layer 105, that is, the first dielectric layer 105 covers the sidewalls of the first source-drain doped region 203, and the process used to remove a portion of the first dielectric film 106 may include a wet etching process, a dry etching process, and the like. The material of the first dielectric layer 105 may be silicon oxide, silicon nitride, silicon oxynitride, or other materials with a high dielectric constant.
S1213, forming a protective layer, wherein the protective layer covers the side wall of the groove structure, which is far away from the top surface of the substrate, of the first dielectric layer and is not covered by the first dielectric layer;
as shown in fig. 7, a protective layer 104 is formed, where the protective layer 104 covers the top surface of the first dielectric layer 106 away from the substrate 100 and the sidewalls of the trench structure 102 not covered by the first dielectric layer 106, and the forming process includes, but is not limited to, PVD, CVD, ALD, etc.
In the subsequent process of forming the word line, the protection layer 104 can effectively protect the sidewall of the active pillar 103 from being damaged by etching, so that the structural integrity of the active pillar 103 can be ensured. Meanwhile, the problems of uneven height of the formed word line, inaccurate position of the formed word line and the like, which are caused by the fact that the active column 103 and the protective layer 104 are damaged by etching, are avoided, and further the thickness of the subsequently formed word line is controlled.
In some embodiments, as shown in fig. 11, another method for manufacturing a protective layer and a first dielectric layer according to an embodiment of the disclosure may include the following specific process steps:
s1221, forming a protective layer, wherein the protective layer covers the groove structure;
as shown in fig. 12, a protective layer 104 is formed in the trench structure 102, the protective layer 104 covering the sidewalls and bottom of the trench structure 102, and the forming process may include, but is not limited to, PVD, CVD, ALD, etc.
S1222, forming a first dielectric film, wherein the first dielectric film fills the groove structure;
as shown in fig. 13, after the protective layer 104 is formed, a first dielectric film 106 is deposited in the trench structure 102 by a process such as PVD, CVD, ALD, and the first dielectric film 106 fills the trench structure 102.
S1223, removing part of the first dielectric film, wherein the rest of the first dielectric film is used as the first dielectric layer, and the first dielectric layer covers part of the protection layer and part of the substrate.
As shown in fig. 14, a part of the thickness of the first dielectric film 106 is removed, and the remaining first dielectric film 106 serves as the first dielectric layer 105, i.e., the first dielectric film 106 located between adjacent first source-drain doped regions 203 serves as the first dielectric layer 105. The process used to remove a portion of the first dielectric film 106 may include a wet etching process, a dry etching process, and the like.
By providing the protection layer 104, the protection layer 104 can effectively protect the sidewall of the active column 103 from being damaged by etching in the process of forming the first dielectric layer 105 and subsequently forming the word line, so that the structural integrity of the active column 103 can be ensured. Meanwhile, the problems of uneven height of the formed word line, inaccurate position of the formed word line and the like, which are caused by the fact that the active column 103 and the protective layer 104 are damaged by etching, are avoided, and further the thickness of the subsequently formed word line is controlled.
In some embodiments, the material of the first dielectric layer 105 is different from the material of the protective layer 104, the material of the first dielectric layer 105 may be silicon oxide, the material of the protective layer 104 may be a high dielectric constant material with stronger corrosion resistance or higher hardness, for example, α -alumina, which has stronger corrosion resistance and is difficult to etch, and α -alumina has a higher dielectric constant, so that the leakage current of the gate dielectric layer can be effectively reduced, which is beneficial to improving the performance reliability of the formed semiconductor structure, the protective layer 104 is realized as the gate dielectric layer, and meanwhile, the side wall of the active column 103 can be protected from being damaged by an etching process, so that the process fluctuation caused by the etching damage of the active column is avoided, the problem that the height of the formed word line is uneven and the position of the word line is inaccurate is avoided, and the possibility that the source-drain doped region of the formed word line is communicated due to the non-uniformity of the height of the word line and the position is avoided, so that the leakage current phenomenon is reduced, and the performance of the protective layer is improved, and the yield of the protective layer 104 can be simplified, and the gate dielectric layer is not required to be used as the gate dielectric layer.
In some embodiments, the protective layer 104 may be formed by first forming an initial protective layer and then subjecting the initial protective layer to a rapid thermal process, such as a rapid annealing process.
Specifically, an initial protection layer is first formed, the initial protection layer covering at least a portion of the sidewalls of the trench structure 102 remote from the substrate 100, for example, the initial protection layer may cover the entire sidewalls of the trench structure, or the initial protection layer may cover the sidewalls of the channel region 303 and the second source drain doped region 403. In some embodiments, the material of the initial protective layer may be aluminum oxide, and the formation process includes, but is not limited to PVD, CVD, ALD, electrodeposition, and the like.
In some embodiments, the annealing temperature for rapid thermal processing of the initial protective layer may range from 900 ℃ to 1000 ℃, e.g., 900 ℃, 930 ℃, 955 ℃, 980 ℃, or 1000 ℃, to convert the alumina in the initial protective layer to alphA-Alumina in the protective layer by a higher annealing temperature to improve the corrosion resistance and hardness of the protective layer 104.
In some embodiments, the thickness of the protective layer 104 may range from 1nm to 10nm, and the thickness of the protective layer 104 may be thinner, for example, 1nm, 3nm, 6nm, 8nm, or 10nm, where the thickness range is advantageous for improving the gate control capability of the formed semiconductor structure.
Referring to fig. 12 to 13, in some embodiments, after forming the protective layer 104 and before forming the first dielectric film 106, the protective layer 104 on the bottom surface of the trench structure 102 may be removed, and by removing the protective layer 104 with a relatively large dielectric constant, parasitic capacitance between the subsequently formed word line and the bit line 101 and leakage between the word line and the active pillar 103 may be reduced, so as to be beneficial to improving performance of the formed semiconductor structure. The process of removing the protective layer 104 on the bottom surface of the trench structure 102 may be, but not limited to, a dry etching process or a wet etching process.
In some embodiments, the protection layer 104 on the bottom surface of the trench structure 102 may be reserved, so as to reduce the possibility of etching damage to the first dielectric layer 105 during the process of etching the protection layer 104 on the top surface of the first dielectric layer 105, where the etching damage easily causes the problems of uneven word line height and inaccurate word line formation position, so as to avoid the possibility of communicating the source-drain doped regions of the active pillars caused by uneven word line height and inaccurate word line formation position, reduce the occurrence of leakage phenomenon, and facilitate improving the performance and yield of the formed semiconductor structure.
In step S130, a word line extending along the second direction is formed, and the word line covers a portion of the first dielectric layer away from the top surface of the substrate and a portion of the protection layer.
In some embodiments, after forming the first dielectric layer 105 and the protective layer 104, forming the word line 107 extending along the second direction is further included, where the word line 107 covers a portion of the first dielectric layer 105 away from the top surface of the substrate 100 and a portion of the protective layer.
In some embodiments, as shown in fig. 7 (a), 8 (a), the protective layer 104 over the first dielectric layer 105 may be etched first, before forming the initial word line 108; word lines are then formed by a deposition process on top of the first dielectric layer 105 and between adjacent channel regions 303. By removing the protective layer 104 with a relatively large dielectric constant on the top surface of the first dielectric layer 105, parasitic capacitance between the subsequently formed word line 107 and the bit line 101 and leakage between the word line 107 and the active column 103 can be reduced, thereby being beneficial to improving performance of the formed semiconductor structure. The process of removing the protective layer 104 above the first dielectric layer 105 may be, but not limited to, a dry etching process or a wet etching process, and the process of forming the initial word line 108 includes, but is not limited to, PVD, CVD, ALD, electroplating deposition, and the like.
It can be appreciated that, in some embodiments, the protection layer 104 on the top surface of the first dielectric layer 105 may be reserved, so as to reduce the possibility of etching damage to the first dielectric layer 105 during the process of etching the protection layer 104 on the top surface of the first dielectric layer 105, where the etching damage easily causes the problems of uneven height of the formed word line and inaccurate position of the formed word line, so as to avoid the possibility of communicating the source-drain doped regions of the active pillars caused by uneven height of the word line and inaccurate position of the formed word line, reduce the occurrence of leakage phenomenon, and facilitate improving the performance and yield of the formed semiconductor structure. Fig. 7 (b), 8 (b), fig. 7 (b) and 8 (b) are further steps for forming a word line according to an embodiment of the present disclosure, including: an initial word line 108 is formed directly on the protective layer 104, the initial word line 108 filling the remaining area of the trench structure 102, i.e. the initial word line 108 covers the protective layer 104 between the channel region 303 and the second source drain doped region 403. Among other things, the process of forming the initial word line 108 includes, but is not limited to PVD, CVD, ALD, electrodeposition, etc., and the material of the initial word line 108 may include, but is not limited to, metals such as copper, aluminum, tungsten, gold, titanium, etc., or metal compounds such as titanium nitride, tantalum nitride, etc. In some embodiments, as shown in fig. 9 (a) and 9 (b), after forming the initial word line 108, etching may further include removing the initial word line 108 located on the sidewall of the second source drain doped region 403, and leaving the initial word line 108 on the sidewall of the channel region 303 as the word line 107. In the step of etching the initial word line 108, the protection layer 104 is disposed between the initial word line 108 and the active pillar 103, and in the step of etching the initial word line 108, the protection layer 104 is difficult to be etched, so that the active pillar 103 and the protection layer 104 are effectively prevented from being damaged by etching in the etching process, thereby ensuring the structural integrity of the active pillar 103, and simultaneously, avoiding the process fluctuation caused by the etching damage of the active pillar 103 and the protection layer 104, which easily causes the problems of uneven height of the formed word line 107, inaccurate forming position of the word line 107, and the like, thereby avoiding the possibility of communication of the active pillar 103 source drain doped region due to uneven height of the word line 107 and inaccurate forming position of the word line 107, reducing the occurrence of leakage phenomenon, and improving the performance and yield of the semiconductor structure.
Fig. 15 to 17 illustrate another word line forming step according to an embodiment of the present disclosure, including:
as shown in fig. 15, an initial word line 108 is formed on the first dielectric layer 105, and the initial word line 108 fills the remaining area of the trench structure 102, that is, the initial word line 108 covers the protection layer 104 between the channel region 303 and the second source drain doped region 403 and the upper surface of the first dielectric layer 105. Among other things, the process of forming the initial word line 108 includes, but is not limited to PVD, CVD, ALD, electrodeposition, etc., and the material of the initial word line 108 may include, but is not limited to, metals such as copper, aluminum, tungsten, gold, titanium, etc., or metal compounds such as titanium nitride, tantalum nitride, etc.
As shown in fig. 16, after forming the initial word line 108, etching is further included to remove the initial word line 108 located at the sidewall of the second source drain doped region 403, and the initial word line 108 located at the sidewall of the channel region 303 remains as the word line 107. In the step of etching the initial word line 108, the protection layer 104 is located between the initial word line 108 and the active column 103, and the protection layer 104 can protect the active column 103 from being damaged by etching, and the protection layer 104 is difficult to be etched, so that the etching object is only the initial word line 108, thereby ensuring the structural integrity of the active column 103, and simultaneously avoiding the process fluctuation caused by the etching damage of the active column 103 and the protection layer 104, which easily causes the problems of uneven height of the formed word line 107, inaccurate forming position of the word line 107, and the like, thereby avoiding the possibility of communication of the source-drain doped region of the active column 103 caused by uneven height of the word line 107 and inaccurate forming position of the word line 107, reducing the occurrence of the leakage phenomenon, and improving the performance and yield of the semiconductor structure.
In some embodiments, the material of the word line 107 may be a metal such as copper, aluminum, tungsten, gold, titanium, or a metal compound such as titanium nitride, tantalum nitride, or the like.
In some embodiments, as shown in fig. 10 (a), 10 (b) and 17, forming the word line 107 may further include forming a second dielectric layer 109, where the second dielectric layer 109 covers the word line 107 and fills the remaining area of the trench structure 102, i.e., the second dielectric layer 109 is located between adjacent second source drain doped regions 403, for isolating adjacent active pillars 103. The material of the second dielectric layer 109 may be silicon oxide, silicon nitride, silicon oxynitride, or other high dielectric constant materials.
Accordingly, in accordance with another aspect of the present disclosure, embodiments of the present disclosure further provide a semiconductor structure, which may be manufactured by the method for manufacturing a semiconductor structure provided by the above embodiments. The semiconductor structure provided in another embodiment of the present disclosure will be described in detail with reference to the accompanying drawings, and the same or corresponding parts as those of the previous embodiment may be referred to for the corresponding description of the previous embodiment, which will not be repeated in detail.
As shown in fig. 10 (a), 10 (b) and 17, the semiconductor structure includes: the substrate 100, the substrate 100 includes a bit line 101, a trench structure on the bit line, and an active pillar 103, wherein the active pillars 103 are arranged at intervals along a first direction X and a second direction Y, and the first direction X intersects the second direction Y. The material of the substrate 100 may include silicon (Si), germanium (Ge), silicon germanium (SiGe), and the like, the material of the bit line 101 may be a conductive material such As tungsten, tantalum, titanium, tantalum nitride, or titanium nitride, and the active pillar 103 may include a first source-drain doped region 203, a channel region 303, and a second source-drain doped region 403 sequentially connected In a direction away from the substrate 100, where the first source-drain doped region 203, the channel region 303, and the second source-drain doped region 403 may be doped with an N-type element or a P-type element, the N-type element may be a v-group element such As a phosphorus (P) element, a bismuth (Bi) element, an antimony (Sb) element, or an arsenic (As) element, and the P-type element may be a iii-group element such As a boron (B) element, an aluminum (Al) element, a gallium (Ga) element, or an indium (In) element.
Adjacent active pillars 103 are disposed at intervals on both sides of the trench structure, and bit lines 101 extend along the first direction and are electrically connected to the active pillars 103.
The first dielectric layer 105 and the protective layer 104 are located in the trench structure, the first dielectric layer 105 fills the bottom region of the trench structure, and the protective layer 104 at least covers the sidewall of the active column 103 away from the substrate 100 for the region between adjacent first source-drain doped regions 203 in the bottom region of the trench structure. For example, the first dielectric layer 105 fills the region between adjacent first source-drain doped regions 203, and the protective layer covers the sidewalls of the channel region 203 and the second source-drain doped regions 403; for another example, the protection layer covers the entire sidewall of the active pillar 103, and the first dielectric layer 105 and the protection layer 104 on the sidewall of the first source drain doped region 203 fill the bottom region of the trench structure.
The material of the first dielectric layer 105 may be silicon oxide, silicon nitride, silicon oxynitride, or other materials with a high dielectric constant. The first dielectric layer 105 is located between adjacent first source drain doped regions 203. As shown in fig. 10 (a), 10 (b) and 17, the protection layer 104 at least covers the channel region 303 and the second source-drain doped region 403 of the active pillar 103, and the protection layer 104 may function as a gate dielectric layer and protect the active pillar 103 from etching damage during formation of the word line 107 by an etching process or the like.
The semiconductor structure further includes: a word line 107 extending in the second direction Y, the word line 107 covering a portion of the first dielectric layer 105 away from the top surface of the substrate and a portion of the protective layer 104. The material of the word line 107 may be a metal such as copper, aluminum, tungsten, gold, or titanium, or a metal compound such as titanium nitride or tantalum nitride. Word line 107 is located between adjacent channel regions 303.
In some embodiments, the material of the first dielectric layer 105 is different from the material of the protective layer 104, the material of the first dielectric layer 104 is silicon oxide, the material of the protective layer 104 is α -alumina, and the thickness of the protective layer 104 is 1nm-10nm. The alphA-Alumina has strong corrosion resistance and is difficult to etch, and has high dielectric constant, so that the leakage current of the gate dielectric layer can be reduced, the performance reliability of the formed semiconductor structure can be improved, and the initial protective layer for forming the protective layer 104 is made of alumina. The annealing temperature may be 900 ℃ to 1000 ℃, for example, the annealing temperature may be 900 ℃, 930 ℃, 955 ℃, 980 ℃ or 1000 ℃, so that the initial protection layer is subjected to rapid heat treatment at a higher annealing temperature, so that the alumina of the initial protection layer is converted into alphA-Alumina of the protection layer, and corrosion resistance and hardness of the protection layer 104 are improved.
In some embodiments, the thickness of the protective layer 104 may be 1nm-10nm, for example, 1nm, 3nm, 6nm, 8nm, or 10nm, and in this thickness range, the thickness of the protective layer 104 is thinner, which is advantageous for improving the gate control capability of the formed semiconductor structure.
With continued reference to fig. 10 (a), 10 (b) and 17, in some embodiments, the semiconductor structure may further include a second dielectric layer 109, the second dielectric layer 109 covering the word line 107 and being located between adjacent second source drain doped regions 403 to isolate adjacent active pillars 103. The material of the second dielectric layer 109 may be silicon oxide, silicon nitride, silicon oxynitride, or other high dielectric constant materials.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the disclosure, and the scope of the disclosure should therefore be assessed as that of the appended claims.

Claims (10)

1. A method of fabricating a semiconductor structure, comprising:
providing a substrate, forming a bit line, a groove structure and an active column, wherein the groove structure and the active column are positioned on the bit line, the active column is arranged at intervals along a first direction and a second direction, the first direction intersects with the second direction, adjacent active columns are arranged at intervals on two sides of the groove structure, and the bit line extends along the first direction and is electrically connected with the active column; forming a protective layer and a first dielectric layer in the groove structure, wherein the first dielectric layer fills the bottom area of the groove structure, and the protective layer at least covers part of the side wall of the groove structure far away from the substrate;
and forming a word line extending along the second direction, wherein the word line covers part of the first dielectric layer away from the top surface of the substrate and part of the protective layer.
2. The method of manufacturing a semiconductor structure of claim 1, wherein the forming the protective layer and the first dielectric layer comprises:
forming a protective layer, wherein the protective layer covers the groove structure;
forming a first dielectric film, wherein the first dielectric film fills the groove structure;
and removing part of the first dielectric film, wherein the rest of the first dielectric film is used as the first dielectric layer, and the first dielectric layer covers part of the protective layer and part of the substrate.
3. The method of manufacturing a semiconductor structure of claim 1, wherein the forming the protective layer and the first dielectric layer comprises:
forming a first dielectric film, wherein the first dielectric film covers the groove structure;
removing part of the first dielectric film, and taking the rest of the first dielectric film as the first dielectric layer;
and forming the protective layer, wherein the protective layer covers the top surface of the first dielectric layer far away from the substrate and the side wall of the groove structure which is not covered by the first dielectric layer.
4. A method of manufacturing a semiconductor structure according to any one of claims 1 to 3, wherein the method of forming the protective layer comprises:
an initial protective layer is formed first, and rapid heat treatment is carried out on the initial protective layer so as to convert the initial protective layer into the protective layer.
5. The method of manufacturing a semiconductor structure according to claim 4, wherein a material of the first dielectric layer is different from a material of the protective layer, the material of the first dielectric layer is silicon oxide, and the material of the protective layer is α -alumina.
6. The method of manufacturing a semiconductor structure according to claim 5, wherein the rapid thermal processing has an annealing temperature of 900 ℃ to 1000 ℃.
7. The method of manufacturing a semiconductor structure of claim 1, further comprising: and forming a second dielectric layer, wherein the second dielectric layer covers the word line and the residual groove structure.
8. The method of manufacturing a semiconductor structure according to claim 1, wherein the thickness of the protective layer is 1nm to 10nm.
9. A semiconductor structure, comprising:
the semiconductor device comprises a substrate, a first substrate and a second substrate, wherein the substrate comprises a bit line, a groove structure and an active column, the groove structure and the active column are positioned on the bit line, the active column is arranged at intervals along a first direction and a second direction, and the first direction is intersected with the second direction;
adjacent active columns are arranged at two sides of the groove structure at intervals, and the bit line extends along the first direction and is electrically connected with the active columns;
the first dielectric layer is positioned in the groove structure and fills the bottom area of the groove structure, and the protective layer at least covers part of the side wall of the groove structure away from the substrate;
and a word line extending along the second direction, wherein the word line covers part of the first dielectric layer away from the top surface of the substrate and part of the protective layer.
10. The semiconductor structure of claim 9, wherein the material of the first dielectric layer is different from the material of the protective layer, the material of the first dielectric layer is silicon oxide, the material of the protective layer is α -alumina, and the thickness of the protective layer is 1nm-10nm.
CN202310625182.0A 2023-05-29 2023-05-29 Method for manufacturing semiconductor structure and semiconductor structure Pending CN116600565A (en)

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