CN116599788A - Communication circuit, method, apparatus, and storage medium - Google Patents

Communication circuit, method, apparatus, and storage medium Download PDF

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Publication number
CN116599788A
CN116599788A CN202310376138.0A CN202310376138A CN116599788A CN 116599788 A CN116599788 A CN 116599788A CN 202310376138 A CN202310376138 A CN 202310376138A CN 116599788 A CN116599788 A CN 116599788A
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China
Prior art keywords
circuit
controller
sub
target
communication port
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CN202310376138.0A
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Chinese (zh)
Inventor
姚贯杰
赵建杰
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Suzhou Inspur Intelligent Technology Co Ltd
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Suzhou Inspur Intelligent Technology Co Ltd
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Priority to CN202310376138.0A priority Critical patent/CN116599788A/en
Publication of CN116599788A publication Critical patent/CN116599788A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/4013—Management of data rate on the bus
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Quality & Reliability (AREA)
  • Information Transfer Systems (AREA)

Abstract

The application discloses a communication circuit, a method, equipment and a storage medium, wherein the communication circuit comprises a motherboard and a signal transmission circuit. The motherboard comprises a first controller and a host communication port; the signal transmission circuit comprises a second controller connected with the first controller, and a plurality of sub-circuits connected with the host communication port, wherein different sub-circuits are used for signal transmission according to different transmission rates, and the signal transmission circuit comprises: the first controller is used for determining a target sub-circuit matched with the target transmission rate based on the target transmission rate of the signal to be transmitted and sending the circuit identification of the target sub-circuit to the second controller; the second controller is used for controlling the target sub-circuit corresponding to the circuit identifier to be communicated with the host communication port based on the received circuit identifier so as to perform signal transmission through the target sub-circuit. The application range is wider.

Description

Communication circuit, method, apparatus, and storage medium
Technical Field
The present application relates to the field of computer technologies, and in particular, to a communication circuit, a method, an apparatus, and a storage medium.
Background
Many current communication protocols support a variety of different communication rates. For example, regarding PCIe (peripheral component interconnect express ) standards widely used in application scenarios such as data centers, servers, PCs, etc., currently, communication rates such as 2.5GT/s, 5GT/s, 8GT/s, 16GT/s, 32GT/s, etc., respectively correspond to PCIe1.0, PCIe2.0, PCIe3.0, PCIe4.0, PCIe5.0, etc., are already supported. This requires that the communication transmission line also be able to support these communication rates. However, in many of the present scenarios, the communication transmission line supports only a part of the communication rate, resulting in a great limitation in the application of many protocol standards (such as PCIe standard).
Disclosure of Invention
In view of the above, the present application provides a communication circuit, a communication method, an electronic device, and a computer readable storage medium, which have a wider application range.
In one aspect, the application provides a communication circuit comprising:
the motherboard comprises a first controller and a host communication port;
the signal transmission circuit comprises a second controller connected with the first controller, and a plurality of sub-circuits connected with the host communication port, wherein different sub-circuits are used for signal transmission according to different transmission rates, and the signal transmission circuit comprises:
the first controller is used for determining a target sub-circuit matched with a target transmission rate based on the target transmission rate of a signal to be transmitted, and sending a circuit identifier of the target sub-circuit to the second controller;
the second controller is used for controlling the target sub-circuit corresponding to the circuit identifier to be communicated with the host communication port based on the received circuit identifier so as to perform signal transmission through the target sub-circuit.
In some embodiments, the second controller comprises a first register, wherein:
the second controller is further configured to write, in the first register, a first status identifier that characterizes that the target sub-circuit is in communication with the host communication port, in a case that the target sub-circuit is controlled to be in communication with the host communication port;
the first controller is further configured to perform signal transmission according to the target transmission rate through the host communication port when the first status identifier is read from the first register.
In some embodiments, the second controller includes a plurality of control ports, different subcircuits being connected to different control ports;
the second controller is specifically configured to control the target sub-circuit to communicate with the host communication port by outputting an enable signal through a target control port corresponding to the target sub-circuit, and control other sub-circuits to disconnect from the host communication port by outputting an enable signal through other control ports other than the target control port.
In some embodiments, the enable signal is used to control a target sub-circuit to initiate operation to place the target sub-circuit in communication with the host communication port; the disabling signal is used for controlling the other sub-circuits to stop working so as to disconnect the other sub-circuits from the host communication port.
In some embodiments, at least some of the plurality of subcircuits include a digital signal processing chip for signal transmission at a first transmission rate, and at least some of the subcircuits include other circuits external to the digital signal processing chip for signal transmission at a second transmission rate, wherein the first transmission rate is greater than the second transmission rate.
In some embodiments, other circuitry outside the digital signal processing chip includes equalization compensation circuitry for compensating and enhancing the transmitted signal.
In some embodiments, the second controller comprises a second register, wherein:
the first controller is specifically configured to write the circuit identifier of the target sub-circuit into the second register;
the second controller is specifically configured to read the circuit identifier from the second register, and control the target sub-circuit corresponding to the circuit identifier to communicate with the host communication port based on the read circuit identifier.
The application also provides a communication method, which comprises the following steps:
the method comprises the steps that a first controller of a host board determines a target sub-circuit matched with a target transmission rate in a signal transmission circuit based on the target transmission rate of a signal to be transmitted, and sends a circuit identifier of the target sub-circuit to a second controller of the signal transmission circuit, wherein the signal transmission circuit comprises a plurality of sub-circuits, and different sub-circuits are used for signal transmission according to different transmission rates; a kind of electronic device with high-pressure air-conditioning system
And the second controller controls the target sub-circuit corresponding to the circuit identifier to be communicated with the host communication port of the mainboard based on the received circuit identifier so as to perform signal transmission through the target sub-circuit.
In some embodiments, the second controller includes a first register, the method further comprising:
the second controller writes a first state identifier in the first register, wherein the first state identifier characterizes that the target sub-circuit is communicated with the host communication port under the condition that the target sub-circuit is controlled to be communicated with the host communication port;
and under the condition that the first controller reads the first state identifier from the first register, signal transmission is carried out through the host communication port according to the target transmission rate.
In some embodiments, the second controller includes a plurality of control ports, different subcircuits being connected to different control ports;
the second controller controls the target sub-circuit corresponding to the circuit identifier to be communicated with a host communication port of the motherboard, and the second controller comprises:
the second controller outputs an enabling signal through a target control port corresponding to the target sub-circuit to control the target sub-circuit to be communicated with the host communication port, and outputs an enabling signal through other control ports except the target control port to control other sub-circuits to be disconnected with the host communication port.
In some embodiments, the second controller includes a second register;
the first controller sends the circuit identification of the target sub-circuit to the second controller, including:
the first controller writes the circuit identification of the target sub-circuit into the second register to send the circuit identification to the second controller.
In a further aspect the application provides an electronic device comprising a processor and a memory for storing a computer program which, when executed by the processor, implements a method as described above.
In a further aspect the application provides a computer readable storage medium for storing a computer program which, when executed by a processor, implements a method as described above.
In some embodiments of the present application, a plurality of sub-circuits are provided in a signal transmission circuit, and different sub-circuits perform signal transmission according to different transmission rates. Based on the target transmission rate of the signal to be transmitted, a target sub-circuit matched with the target transmission rate can be controlled to communicate with the host communication port so as to perform signal transmission according to the target transmission rate through the target sub-circuit. Because the plurality of sub-circuits for signal transmission can be arranged according to different transmission rates, the supported transmission rates are more, and the application range is wider.
Drawings
The features and advantages of the present application will be more clearly understood by reference to the accompanying drawings, which are illustrative and should not be construed as limiting the application in any way, in which:
FIG. 1 shows a schematic diagram of a communication circuit in some techniques;
FIG. 2 shows a block circuit diagram of a communication circuit provided by one embodiment of the application;
FIG. 3 shows a block circuit diagram of a communication circuit provided by another embodiment of the present application;
FIG. 4 is a schematic diagram showing an internal structure of the second controller in FIG. 2;
fig. 5 shows a circuit diagram of the communication circuit in fig. 2;
FIG. 6 shows a flow diagram of a communication method provided by one embodiment of the application;
fig. 7 shows a schematic diagram of an electronic device according to an embodiment of the application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions in the present application will be clearly and completely described below with reference to the accompanying drawings in the present application, and it is apparent that the described embodiments are some embodiments of the present application, not all embodiments of the present application. All other embodiments, based on the embodiments of the application, which are available to the person skilled in the art without any inventive effort, are within the scope of the application.
The problems to be solved by the present application are described below in connection with a specific application. Referring to fig. 1, a schematic diagram of a communication circuit 100 in some technologies is shown. In fig. 1, a communication circuit 100 includes a host 11. The host 11, which may also be referred to as a motherboard, a system board, a motherboard, etc., is typically mounted in a mainframe box of a computer, and is one of the most basic and important components of the computer. The host computer 11 is a generally rectangular circuit board on which the main circuitry constituting the computer is mounted, such as a CPU chip, a BIOS chip, an I/O control chip, a keyboard and panel control switch interface, an expansion slot, and the like.
With hardware resources supported, host 11 may communicate with other devices based on PCIe protocols. At present, PCIe protocols are mostly applied to the field of electrical characteristic transmission, but electrical characteristic transmission has the disadvantages of short transmission distance, large loss and the like, so that application of PCIe protocols in large-scale data center interconnection is greatly limited, and optical transmission largely avoids the disadvantages of electrical characteristic transmission, so that PCIe protocols are gradually applied to the field of optical cable transmission. The communication circuit 100 shown in fig. 1 is a communication circuit when the PCIe protocol is applied to the field of optical cable transmission.
In fig. 1, a communication circuit 100 includes an optical module 12. The optical module 12 includes a processing chip 121, an optical receiving module 122, and an optical transmitting module 123. The processing chip 121 is communicatively connected to the host 11, the light receiving module 122, and the light transmitting module 123.
Based on the above circuit structure, when the host 11 sends a message based on PCIe protocol, the procedure may be as follows: the host 11 transmits a message based on PCIe protocol to the processing chip 121 through an electrical signal. After processing the electrical signal, the processing chip 121 sends the result of the processing to the optical transmission module 123, and the optical transmission module 123 converts the electrical signal into an optical signal, and then transmits a message through a communication line such as an optical cable. Thus, message transmission based on PCIe protocol is realized.
Correspondingly, when the host 11 receives a message based on PCIe protocol, the procedure may be as follows: the light receiving module 122 receives an optical signal via a communication line such as an optical cable, converts the optical signal into an electrical signal, and transmits the electrical signal to the processing chip 121 for processing. The processing chip 121 transmits the processed result to the host 11. Thus, message reception based on PCIe protocol is realized.
Generally, the processing chip 121 includes, but is not limited to, a clock data recovery chip and a digital signal processing chip. The clock data recovery chip is an analog chip, and the digital signal processing chip is a digital chip. The clock data recovery chip is also called CDR (clock data recovery ) chip, and the digital signal processing chip is also called DSP (Digital Signal Processing ) chip.
In the case where the processing chip 121 is a clock data recovery chip, the message transmission process is: the clock data recovery chip converts the electrical signal output by the host 11 into an analog electrical signal, and then the optical transmission module 123 converts the analog electrical signal into an optical signal. The message receiving process is as follows: the optical receiving module 122 converts the received optical signal into an analog electrical signal, and the clock data recovery chip processes the analog electrical signal and then sends the processed result to the host 11.
In the case where the processing chip 121 is a digital signal processing chip, the message transmission process is: the digital signal processing chip converts the electrical signal output from the host 11 into a digital electrical signal, and the optical transmission module 123 converts the digital electrical signal into an optical signal. The message receiving process is as follows: the light receiving module 122 may convert the received optical signal into a digital electrical signal, and then process the digital electrical signal by the digital signal processing chip, and send the processed result to the host 11.
In the two chips, the highest transmission rate supported by the clock data recovery chip is 28GNRZ, and the transmission rate can only meet the rate requirement of the pcie4.0 protocol or the version protocol below pcie4.0, but cannot meet the rate requirement of the 32G NRZ of the pcie5.0 protocol. With the popularization and popularization of the pcie5.0 protocol, new products such as servers will increasingly use the pcie5.0 protocol to perform data transmission, and if the optical module 12 still only supports the pcie4.0 protocol or the pcie4.0 version protocol, the maximum performance of the products such as servers will be limited. In view of this, in the present optical module 12, a digital signal processing chip is generally employed as the processing chip. However, the digital signal processing chips in the optical module 12 are all designed based on ethernet architecture, and the minimum transmission rate supported by the digital signal processing chips is 10 gbps, which cannot meet the rate requirements of pcie1.0 to pcie3.0 protocols. In view of this, if PCIe protocol is applied to the field of optical cable transmission, the problem of transmission rate of the optical module 12 during communication must be solved.
In summary, the present application provides a communication circuit for signal transmission in a communication process, which has a wider application range. Referring to fig. 2, a circuit block diagram of a communication circuit 200 according to an embodiment of the present application is provided. In fig. 2, the communication circuit 200 includes a motherboard 21 and a signal transmission circuit 22. The motherboard 21 is similar to the motherboard 11 in fig. 1 in terms of physical structure, and is not described here again. The motherboard 21 may be communicatively connected to the signal transmission circuit 22 and communicate with other devices via the signal transmission circuit 22. In this embodiment, the motherboard 21 may communicate with other devices through the signal transmission circuit 22 based on PCIe protocol.
In some embodiments, the motherboard 21 and the signal transmission circuit 22 may be designed separately, i.e., the motherboard 21 and the signal transmission circuit 22 are located on different circuit boards. In other embodiments, motherboard 21 and signal transmission circuit 22 may be located on the same circuit board.
The motherboard 21 may include a first controller 211 and a host communication port 212. The signal transmission circuit 22 includes a second controller 221 connected to the first controller 211, and a plurality of sub-circuits 222 connected to the host communication port 212, the different sub-circuits 222 being used for signal transmission at different transmission rates, wherein the first controller 211 and the second controller 221 may be connected by a bus.
The first controller 211 is configured to determine a target sub-circuit 222 that matches a target transmission rate based on the target transmission rate of the signal to be transmitted. Here, the signal to be transmitted may include a signal to be transmitted from the motherboard 21 to other devices, or a signal to be received by the motherboard 21 and transmitted from other devices. The signals to be transmitted may be electrical signals (such as high and low levels), from which communication messages between the motherboard 21 and other devices may be extracted. The first controller 211 may be a control management chip such as a central processing unit on the motherboard 21. The first controller 211 may determine a target transmission rate of a signal to be transmitted based on a link negotiation manner with other devices.
In this embodiment, the sub-circuits 222 may have circuit identifications, with the circuit identifications of different sub-circuits 222 being different. Based on the circuit identifier of the sub-circuit 222, a correspondence between the circuit identifier of the sub-circuit 222 and the transmission rate supported by the sub-circuit 222 may be preset, so that after the target transmission rate is obtained, the first controller 211 may obtain the circuit identifier corresponding to the target sub-circuit 222 matched with the target transmission rate by querying the correspondence.
In the correspondence between the circuit identifier and the transmission rate, the transmission rate may be a specific value indicating the transmission rate, or may be a rate range. If the target transmission rate falls within the transmission rate range corresponding to the sub-circuit 222, the corresponding sub-circuit 222 is the target sub-circuit. For example, the transmission rate supported by the sub-circuit A is 2.5GT/s to 3GT/s, and the transmission rate supported by the sub-circuit B is 4GT/s. In the case of a target transmission rate of 2.6GT/s, indicating that the sub-circuit A is a target sub-circuit; and in case of a target transmission rate of 4GT/s, the sub-circuit B is indicated as a target sub-circuit.
In some embodiments, the correspondence between the circuit identifier and the transmission rate may be stored in a storage accessible to the first controller 211, so that, when the first controller 211 obtains the target transmission rate, the circuit identifier of the target sub-circuit 222 may be obtained based on the correspondence in the storage. In other embodiments, the correspondence between the circuit identifier and the transmission rate may be directly written into the program code and burned into the first controller 211 together with the program code, so that the first controller 211 can determine the circuit identifier of the target sub-circuit 222 based on the code logic of the program code when the target transmission rate is obtained.
In the case of the acquired circuit identification of the target sub-circuit 222, the first controller 211 may transmit the circuit identification to the second controller 221. The second controller 221 is configured to control, based on the received circuit identifier, the target sub-circuit 222 corresponding to the circuit identifier to communicate with the host communication port 212, so as to perform signal transmission through the target sub-circuit 222. In this manner, it is achieved that the corresponding target sub-circuit 222 is selected for signal transmission based on the target transmission rate.
In some embodiments of the present application, a plurality of sub-circuits 222 are disposed in the signal transmission circuit 100, and different sub-circuits 222 perform signal transmission according to different transmission rates. Based on the target transmission rate of the signal to be transmitted, the target sub-circuit 222 matched to the target transmission rate may be controlled to communicate with the host communication port to perform signal transmission at the target transmission rate through the target sub-circuit 222. Since the plurality of sub-circuits 222 for signal transmission are provided, the transmission rates can be supported more and the application range is wider.
The scheme of the application is further described below.
In the embodiment shown in fig. 2, the second controller 221 includes a plurality of control ports 2211, and different sub-circuits 222 are connected to different control ports 2211. The second controller 221 is specifically configured to output an enable signal through a target control port 2211 corresponding to the target sub-circuit 222 to control the target sub-circuit 222 to communicate with the host communication port 212, and output an enable signal through other control ports 2211 except the target control port 2211 to control the other sub-circuits 222 to disconnect from the host communication port 212.
Wherein the enable signal is used to control the target sub-circuit 222 to start operation so that the target sub-circuit 222 communicates with the host communication port 212; the disable signal is used to control the other subcircuits 222 to cease operation, such that the other subcircuits 222 are disconnected from the host communication port 212. For one sub-circuit 222, the control sub-circuit 222 starts to operate, and at least part of circuit components in the control sub-circuit 222 may be changed from a stop operating state to an operating state; the control sub-circuit 222 may be deactivated, and at least some circuit components in the control sub-circuit 222 may be changed from an active state to a deactivated state. When these circuit components cease to operate, the sub-circuit 222 may be in an off state, the sub-circuit 222 not communicating with the host communication port 212; in operation of these circuit components, the sub-circuit 222 communicates with the host communication port 212. In summary, the enable signal may be a signal that controls the circuit components to start up, and the disable signal may be a signal that controls the circuit components to stop. For example, where sub-circuit 222 includes a chip, it is typically necessary to provide a supply voltage to the chip to enable the chip to function properly. Then, for the chip, the enable signal may be the supply voltage provided to the chip. After the chip is powered up normally, subcircuit 222 communicates with host communication port 212. The disable signal may be a voltage other than the supply voltage required by the chip. The chip is not normally powered, stops working, and the sub-circuit 222 is disconnected from the host communication port 212. In these schemes, the sub-circuit 222 is controlled to start or stop working to realize the on-off between the sub-circuit 222 and the host communication port 212, so that the use of circuit components such as a switch can be reduced, the circuit cost can be reduced, and the circuit volume can be reduced.
Of course, it will be appreciated that, given the frequent switching between start-up and stop-up operations, damage may be caused to circuit components, and thus, the switching between the sub-circuits and the host communication port may be achieved in other ways. For example, referring to fig. 3, a circuit block diagram of a communication circuit 300 according to another embodiment of the present application is provided. Fig. 3 is substantially similar to fig. 2, with the main difference that the host communication port 312 is connected to the sub-circuit 322 via a switching circuit 323, and the switching circuit 323 is connected to a control port 3211 of the second controller 321. The second controller 321 connects the target sub-circuit 322 to the host communication port 312 and disconnects the sub-circuits 322 other than the target sub-circuit 322 from the host communication port 312 by controlling the switching circuit 323. The switching circuit 323 may include circuit components such as a switch.
The communication control principle of the first controller 211 and the second controller 221 will be described below with reference to fig. 2. Referring to fig. 4 in combination, an internal structure of the second controller 221 in fig. 2 is shown.
In some embodiments, the second controller 221 includes a first register 2212, wherein the second controller 221 is further configured to write a first status identifier in the first register 2212 that characterizes that the target sub-circuit 222 is in communication with the host communication port 212, in case the target sub-circuit 222 is in communication with the host communication port 212. The first controller 211 is further configured to signal the target transmission rate through the host communication port 212 when the first status identifier is read from the first register 2212.
In particular, the first register 2212 may be used to store a status identifier that characterizes an on-off state between the target sub-circuit 222 and the host communication port 212. The state identifiers may include a first state identifier and a second state identifier. The first state identification characterizes the target sub-circuit 222 as being in communication with the host communication port 212 and the second state identification characterizes the target sub-circuit 222 as being in an off state with the host communication port 212. The first state identification and the second state representation may be different values, such as a first state identification of 1 and a second state identification of 0. In this way, the problem of starting signal transmission when the target sub-circuit 222 is not connected to the host communication port 212 can be prevented, and the reliability of signal transmission can be improved.
In some embodiments, the second controller 221 may further include a second register 2213, where the first controller 211 is specifically configured to write the circuit identifier of the target sub-circuit 222 into the second register 2213, and the second controller 221 is specifically configured to read the circuit identifier from the second register 2213, and based on the read circuit identifier, control the target sub-circuit 222 corresponding to the circuit identifier to communicate with the host communication port 212.
The following describes the embodiment of the present application by way of a specific example.
Please refer to fig. 5, which is a circuit diagram of the communication circuit 200 in fig. 2. In fig. 5, the motherboard 21 communicates with other devices via the signal transmission circuit 22 based on PCIe protocol. Of the plurality of sub-circuits 222 of the signal transmission circuit 22, at least part of the sub-circuits 222 comprise a digital signal processing chip for signal transmission at a first transmission rate, and at least part of the sub-circuits 222 comprise other circuits than the digital signal processing chip for signal transmission at a second transmission rate, wherein the first transmission rate is greater than the second transmission rate. As can be seen from the description related to fig. 1, the lowest transmission rate supported by the digital signal processing chip is 10 gbps, and the rate requirements of the pcie1.0 to pcie3.0 protocols cannot be met, so that in the sub-circuit 222 that does not include the digital signal processing chip, the sub-circuit 222 can meet the rate requirements of the pcie1.0 to pcie3.0 protocols through circuit design. As such, the signaling circuit 22 supports the rate requirements of all versions of the PCIe protocol, with a wider range of applications.
In some embodiments, the first controller 211 may be connected to the second controller 221 through an IIC (Inter-Integrated Circuit, integrated circuit bus) bus. The control port 2211 of the second controller 221 may include a General-purpose input/Output (GPIO) port connected to the sub-circuit 222 not including the digital signal processing chip for controlling the connection or disconnection between the sub-circuit 222 and the host communication port 212 and an MDIO port connected to the digital signal processing chip for controlling the connection or disconnection between the digital signal processing chip and the host communication port 212.
Referring to fig. 4 and 5 in combination, since the communication circuit 200 of fig. 5 has only two sub-circuits 222, the first controller 211 can distinguish the two sub-circuits 222 using a high and low level. Based on this, the specific operating principle of the communication circuit 200 is:
when the motherboard 21 needs to communicate with other devices based on the pcie1.0 to pcie3.0 protocols, the first controller 221 sends a high level to the second controller 221 through the IIC bus, and writes 1 into the second register 2213, the second controller 221 starts working through the GPIO port to control the sub-circuit 222 that does not include the digital signal processing chip, so that the sub-circuit 222 communicates with the host communication port 212, and controls the digital signal processing chip to stop working through the MDIO port, so that the digital signal processing chip is disconnected from the host communication port 212, so that the motherboard 21 can communicate with other devices based on the pcie1.0 to pcie3.0 protocols through the sub-circuit 222 that does not include the digital signal processing chip.
When the motherboard 21 needs to communicate with other devices based on the pcie4.0 to pcie5.0 protocols, the first controller 221 sends a low level to the second controller 221 through the IIC bus, and writes 0 into the second register 2213, the second controller 221 stops working through the GPIO port to control the sub-circuit 222 that does not include the digital signal processing chip, so that the sub-circuit 222 is disconnected from the host communication port 212, and controls the digital signal processing chip to start working through the MDIO port, so that the digital signal processing chip is communicated with the host communication port 212, and thus, the motherboard 21 can communicate with other devices based on the pcie4.0 to pcie5.0 protocols through the digital signal processing chip.
In some embodiments, it should be appreciated by those skilled in the art that in the sub-circuit 222 including the digital signal processing chip, the digital signal processing chip may modulate the electrical signal, so as to effectively reduce the bit error rate in the signal transmission process, and in the sub-circuit 222 not including the digital signal processing chip, in order to effectively reduce the bit error rate, the sub-circuit 222 may include at least an equalization compensation circuit 2221, where the equalization compensation circuit 2221 is used to compensate and enhance the transmitted signal, so as to achieve the purpose of reducing the bit error rate. The equalization compensation circuit 2221 is a circuit design that should be known to those skilled in the art, and the present application is not described herein. It should be noted that, in addition to the equalization compensation circuit 2221, other circuits may be included in the sub-circuit 222 that does not include the digital signal processing chip, and the present application is not limited to the circuits included in the sub-circuit 222.
In some embodiments, the signal transmission circuit 22 may further include an optical receiving module 223 and an optical transmitting module 224, considering that PCIe protocols are gradually being applied to the field of optical cable transmission. The descriptions of the light receiving module 223 and the light transmitting module 224 are similar to those of fig. 1, and are not repeated here.
In some embodiments, signal transmission circuit 22 may also include a memory 227, a power supply 226, and a crystal 225. Wherein the power supply 226 is used to supply power to circuit components (e.g., digital signal processing chips) in the signal transmission circuit 22. Memory 227 may include an EEPROM (Electrically Erasable Programmable read only memory ) for storing digital signal processing chip firmware information. The crystal oscillator 225 is used for providing an external clock for the digital signal processing chip, and the second controller 221 controls the digital signal processing chip through the MDIO port, so that the phase-locked loop of the digital signal processing chip locks the clock provided by the crystal oscillator 225.
In the embodiment shown in fig. 5, the digital signal processing chip is selected as the modulation chip of one of the sub-circuits 222 of the communication circuit 200, so as to adapt to the trend of increasing the signal transmission rate, and further enable the communication circuit 200 to have a wider application range.
Based on the above description, the application also provides a communication method. The communication method is applicable to the above-described communication circuit. Referring to fig. 6, a flow chart of a communication method according to an embodiment of the application is shown. In fig. 6, the communication method includes the steps of:
in step S61, the first controller of the motherboard determines a target sub-circuit in the signal transmission circuit that matches the target transmission rate based on the target transmission rate of the signal to be transmitted, and sends the circuit identifier of the target sub-circuit to the second controller of the signal transmission circuit, where the signal transmission circuit includes a plurality of sub-circuits, and different sub-circuits are used for signal transmission according to different transmission rates.
In step S62, the second controller controls the target sub-circuit corresponding to the circuit identifier to communicate with the host communication port of the motherboard based on the received circuit identifier, so as to perform signal transmission through the target sub-circuit.
In some embodiments, the second controller includes a first register, and the communication method further includes:
under the condition that the control target sub-circuit is communicated with the host communication port, the second controller writes a first state identifier which characterizes that the target sub-circuit is communicated with the host communication port in the first register;
and under the condition that the first controller reads the first state identifier from the first register, signal transmission is carried out according to the target transmission rate through the host communication port.
In some embodiments, the second controller includes a plurality of control ports, different subcircuits being connected to different control ports;
the second controller controls the target sub-circuit corresponding to the circuit identifier to be communicated with the host communication port of the motherboard, and the second controller comprises:
the second controller outputs an enabling signal through a target control port corresponding to the target sub-circuit so as to control the target sub-circuit to be communicated with the host communication port, and outputs the enabling signal through other control ports except the target control port so as to control other sub-circuits to be disconnected with the host communication port.
In some embodiments, the second controller includes a second register;
the first controller sends the circuit identification of the target sub-circuit to the second controller, comprising:
the first controller writes the circuit identification of the target sub-circuit to the second register to send the circuit identification to the second controller.
For specific description and beneficial effects of the communication method, reference may be made to the description of related principles of the communication circuit, which is not repeated here.
Referring to fig. 7, a schematic diagram of an electronic device according to an embodiment of the application is provided. The electronic device comprises a processor and a memory for storing a computer program which, when executed by the processor, implements the method described above.
The processor may be a central processing unit (Central Processing Unit, CPU). The processor may also be any other general purpose processor, digital signal processor (Digital Signal Processor, DSP), application specific integrated circuit (Application Specific Integrated Circuit, ASIC), field programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof.
The memory, as a non-transitory computer readable storage medium, may be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as program instructions/modules, corresponding to the methods in embodiments of the present application. The processor executes various functional applications of the processor and data processing, i.e., implements the methods of the method embodiments described above, by running non-transitory software programs, instructions, and modules stored in memory.
The memory may include a memory program area and a memory data area, wherein the memory program area may store an operating system, at least one application program required for a function; the storage data area may store data created by the processor, etc. In addition, the memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some implementations, the memory optionally includes memory remotely located relative to the processor, the remote memory being connectable to the processor through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
An embodiment of the present application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described communication method.
The application also provides a computer program product comprising a computer program which, when executed by a processor, implements the communication method described above.
Although the method of practicing the application has been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the application, and such modifications and variations fall within the scope defined by the appended claims.

Claims (13)

1. A communication circuit, the circuit comprising:
the motherboard comprises a first controller and a host communication port;
the signal transmission circuit comprises a second controller connected with the first controller, and a plurality of sub-circuits connected with the host communication port, wherein different sub-circuits are used for signal transmission according to different transmission rates, and the signal transmission circuit comprises:
the first controller is used for determining a target sub-circuit matched with a target transmission rate based on the target transmission rate of a signal to be transmitted, and sending a circuit identifier of the target sub-circuit to the second controller;
the second controller is used for controlling the target sub-circuit corresponding to the circuit identifier to be communicated with the host communication port based on the received circuit identifier so as to perform signal transmission through the target sub-circuit.
2. The circuit of claim 1, wherein the second controller comprises a first register, wherein:
the second controller is further configured to write, in the first register, a first status identifier that characterizes that the target sub-circuit is in communication with the host communication port, in a case that the target sub-circuit is controlled to be in communication with the host communication port;
the first controller is further configured to perform signal transmission according to the target transmission rate through the host communication port when the first status identifier is read from the first register.
3. The circuit of claim 1, wherein the second controller comprises a plurality of control ports, different sub-circuits being connected to different control ports;
the second controller is specifically configured to control the target sub-circuit to communicate with the host communication port by outputting an enable signal through a target control port corresponding to the target sub-circuit, and control other sub-circuits to disconnect from the host communication port by outputting an enable signal through other control ports other than the target control port.
4. The circuit of claim 3, wherein the enable signal is to control a target subcircuit to start operation to communicate the target subcircuit with the host communication port; the disabling signal is used for controlling the other sub-circuits to stop working so as to disconnect the other sub-circuits from the host communication port.
5. The circuit of claim 1, wherein at least some of the plurality of subcircuits include a digital signal processing chip for signal transmission at a first transmission rate, and at least some of the subcircuits include other circuits outside of the digital signal processing chip for signal transmission at a second transmission rate, wherein the first transmission rate is greater than the second transmission rate.
6. The circuit of claim 5, wherein circuitry other than the digital signal processing chip includes equalization compensation circuitry for compensating and enhancing the transmitted signal.
7. The circuit of claim 1, wherein the second controller comprises a second register, wherein:
the first controller is specifically configured to write the circuit identifier of the target sub-circuit into the second register;
the second controller is specifically configured to read the circuit identifier from the second register, and control the target sub-circuit corresponding to the circuit identifier to communicate with the host communication port based on the read circuit identifier.
8. A method of communication, the method comprising:
the method comprises the steps that a first controller of a host board determines a target sub-circuit matched with a target transmission rate in a signal transmission circuit based on the target transmission rate of a signal to be transmitted, and sends a circuit identifier of the target sub-circuit to a second controller of the signal transmission circuit, wherein the signal transmission circuit comprises a plurality of sub-circuits, and different sub-circuits are used for signal transmission according to different transmission rates; a kind of electronic device with high-pressure air-conditioning system
And the second controller controls the target sub-circuit corresponding to the circuit identifier to be communicated with the host communication port of the mainboard based on the received circuit identifier so as to perform signal transmission through the target sub-circuit.
9. The method of claim 8, wherein the second controller comprises a first register, the method further comprising:
the second controller writes a first state identifier in the first register, wherein the first state identifier characterizes that the target sub-circuit is communicated with the host communication port under the condition that the target sub-circuit is controlled to be communicated with the host communication port;
and under the condition that the first controller reads the first state identifier from the first register, signal transmission is carried out through the host communication port according to the target transmission rate.
10. The method of claim 8, wherein the second controller comprises a plurality of control ports, different sub-circuits being connected to different control ports;
the second controller controls the target sub-circuit corresponding to the circuit identifier to be communicated with a host communication port of the motherboard, and the second controller comprises:
the second controller outputs an enabling signal through a target control port corresponding to the target sub-circuit to control the target sub-circuit to be communicated with the host communication port, and outputs an enabling signal through other control ports except the target control port to control other sub-circuits to be disconnected with the host communication port.
11. The method of claim 8, wherein the second controller comprises a second register;
the first controller sends the circuit identification of the target sub-circuit to the second controller, including:
the first controller writes the circuit identification of the target sub-circuit into the second register to send the circuit identification to the second controller.
12. A computer readable storage medium for storing a computer program which, when executed by a processor, implements the method of any one of claims 8 to 11.
13. An electronic device comprising a processor and a memory for storing a computer program which, when executed by the processor, implements the method of any of claims 8 to 11.
CN202310376138.0A 2023-04-10 2023-04-10 Communication circuit, method, apparatus, and storage medium Pending CN116599788A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117095713A (en) * 2023-08-23 2023-11-21 上海奎芯集成电路设计有限公司 Signal phase conversion circuit based on transmission rate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117095713A (en) * 2023-08-23 2023-11-21 上海奎芯集成电路设计有限公司 Signal phase conversion circuit based on transmission rate
CN117095713B (en) * 2023-08-23 2024-03-19 上海奎芯集成电路设计有限公司 Signal phase conversion circuit based on transmission rate

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