CN116599499B - Clock output method, circuit and chip - Google Patents
Clock output method, circuit and chip Download PDFInfo
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- CN116599499B CN116599499B CN202310881495.2A CN202310881495A CN116599499B CN 116599499 B CN116599499 B CN 116599499B CN 202310881495 A CN202310881495 A CN 202310881495A CN 116599499 B CN116599499 B CN 116599499B
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/014—Modifications of generator to ensure starting of oscillations
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application relates to the technical field of clock output, and particularly provides a clock output method, a circuit and a chip, wherein the method comprises the following steps: acquiring a first clock cycle number, wherein the first clock cycle number is the clock cycle number continuously generated by an internal crystal oscillator clock when a first condition is met, and the first condition comprises that an enabling switch of the internal crystal oscillator module is turned on; releasing the internal crystal oscillator clock when the number of the first clock cycles is greater than or equal to the preset number of the second clock cycles; the method can output the internal crystal oscillator clock with stable frequency and duty ratio, thereby effectively avoiding the situation that the running clock of the digital circuit is malformed due to the change of the frequency and the duty ratio of the internal crystal oscillator clock, and further effectively avoiding the situation that the time sequence is violated, a trigger in the digital circuit enters a metastable state and the digital circuit crashes and dies due to the malformed running clock of the digital circuit.
Description
Technical Field
The present disclosure relates to the field of clock output technologies, and in particular, to a clock output method, a circuit, and a chip.
Background
The existing digital circuit uses an internal crystal oscillator clock as an operation clock of the system, and the existing internal crystal oscillator circuit can reach a correct and stable internal crystal oscillator clock only after a certain stable period, namely the existing internal crystal oscillator circuit can generate the correct and stable internal crystal oscillator clock only after a period of time after starting oscillation. During the operation of the internal crystal oscillator clock, if the enabling switch of the internal crystal oscillator circuit is suddenly turned off, the internal crystal oscillator circuit may restart or the frequency and the duty ratio of the internal crystal oscillator clock may change, and the restarting of the internal crystal oscillator circuit may cause the abnormal condition of the operation clock of the digital circuit, which may cause the timing violation caused by the operation clock of the digital circuit not meeting the duty ratio requirement, the flip-flop in the digital circuit entering a metastable state, and the digital circuit crashing.
In view of the above problems, no effective technical solution is currently available.
Disclosure of Invention
The invention aims to provide a clock output method, a circuit and a chip, which can output an internal crystal oscillator clock with stable frequency and duty ratio.
In a first aspect, the present application provides a clock output method, applied in a clock output circuit, where the clock output circuit includes an internal crystal oscillator module, and the internal crystal oscillator module is configured to generate an internal crystal oscillator clock, and the clock output method includes the following steps:
acquiring a first clock cycle number, wherein the first clock cycle number is the clock cycle number continuously generated by an internal crystal oscillator clock when a first condition is met, and the first condition comprises that an enabling switch of the internal crystal oscillator module is turned on;
and when the number of the first clock cycles is greater than or equal to the preset number of the second clock cycles, releasing the internal crystal oscillator clock.
According to the clock output method, the internal crystal oscillator clock can be released only when the number of the first clock cycles is larger than or equal to that of the second clock cycles, so that the method can output the internal crystal oscillator clock with stable frequency and duty ratio, the situation that the running clock of the digital circuit is deformed due to the fact that the frequency and the duty ratio of the internal crystal oscillator clock are changed is effectively avoided, and further the situation that time sequence violations are caused due to the fact that the running clock of the digital circuit is deformed, the trigger in the digital circuit enters a metastable state, and the digital circuit crashes and dies are effectively avoided.
Optionally, the first condition further includes that the power-on reset is completed and/or the starting frequency adjustment of the internal crystal oscillator module is finished.
The first condition further comprises that the power-on reset is completed and/or the starting frequency of the internal crystal oscillator module is adjusted, so that the condition that the frequency and the duty ratio of the internal crystal oscillator clock are changed due to the power-on reset and the starting frequency of the internal crystal oscillator module is adjusted can be effectively avoided, the condition that the operating clock of the digital circuit is deformed due to the change of the frequency and the duty ratio of the internal crystal oscillator clock is further avoided, and further the condition that time sequence violations are caused due to the fact that the operating clock of the digital circuit is deformed, the trigger in the digital circuit enters a metastable state, and the digital circuit crashes is further avoided.
Optionally, the clock output circuit stores enable switch flag bit information, power-on reset flag bit information and/or oscillation starting frequency adjustment flag bit information, the enable switch flag bit information is used for identifying whether an enable switch of the internal crystal oscillator module is turned on, the power-on reset flag bit information is used for identifying whether the power-on reset of the internal crystal oscillator module is completed, and the oscillation starting frequency adjustment flag bit information is used for identifying whether the oscillation starting frequency of the internal crystal oscillator module is adjusted.
Optionally, if the enabling switch flag bit information indicates that the enabling switch of the internal crystal oscillator module is turned on, the enabling switch flag bit information is 1, if the enabling switch flag bit information indicates that the enabling switch of the internal crystal oscillator module is turned off, the enabling switch flag bit information is 0, if the power-on reset flag bit information indicates that the power-on reset of the internal crystal oscillator module is not completed, the power-on reset flag bit information is 0, if the power-on reset flag bit information indicates that the power-on reset of the internal crystal oscillator module is completed, the power-on reset flag bit information is 1, if the starting frequency adjustment flag bit information indicates that the starting frequency of the internal crystal oscillator module is not adjusted, the starting frequency adjustment flag bit information is 0, if the starting frequency adjustment flag bit information indicates that the starting frequency adjustment of the internal crystal oscillator module is ended, the starting frequency adjustment flag bit information is 1, and the first condition is that: osc_en=1 & & por_n=1 & & change_osc_trim_b=1;
wherein osc_en represents enable switch flag bit information, por_n represents power-on reset flag bit information, and change_osc_trim_b represents oscillation starting frequency adjustment flag bit information.
Optionally, the step of obtaining the first number of clock cycles comprises:
and counting the rising edge number of the internal crystal oscillator clock based on the counting module so as to acquire the first clock cycle number.
In a second aspect, the present application also provides a clock output circuit, the clock output circuit comprising:
the internal crystal oscillator module is used for generating an internal crystal oscillator clock;
the condition module is used for judging whether a first condition is met or not, wherein the first condition comprises that an enabling switch of the internal crystal oscillator module is opened;
the counting module is electrically connected with the condition module and the internal crystal oscillator module, and is used for acquiring the number of first clock cycles, wherein the number of the first clock cycles is the number of clock cycles continuously generated by the internal crystal oscillator clock when the first condition is met, and outputting a high-level signal when the number of the first clock cycles is greater than or equal to the number of preset second clock cycles;
and the releasing module is electrically connected with the internal crystal oscillator module, the condition module and the counting module and is used for releasing the internal crystal oscillator clock when receiving the high-level signal output by the counting module.
The clock output circuit provided by the application can release the internal crystal oscillator clock only when the number of the first clock cycles is greater than or equal to that of the second clock cycles, so that the circuit can output the internal crystal oscillator clock with stable frequency and duty ratio, the situation that the running clock of the digital circuit is abnormal due to the fact that the frequency and the duty ratio of the internal crystal oscillator clock are changed is effectively avoided, and further the situation that time sequence violations are caused by the fact that the running clock of the digital circuit is abnormal, and the trigger in the digital circuit enters a metastable state and the digital circuit crashes is effectively avoided.
Optionally, the release module includes a D trigger and a clock gating module, a CLR port of the D trigger is electrically connected with the condition module, a D port of the D trigger is electrically connected with the counting module, a CP port of the D trigger is electrically connected with the internal crystal oscillator module, and two input ends of the clock gating module are respectively electrically connected with a Q port of the D trigger and the internal crystal oscillator module.
Optionally, the first condition further includes that the power-on reset is completed and/or the starting frequency adjustment of the internal crystal oscillator module is finished, and the condition module is a multiple-input and gate.
The first condition further comprises that the power-on reset is completed and/or the starting frequency of the internal crystal oscillator module is adjusted, so that the condition that the frequency and the duty ratio of the internal crystal oscillator clock are changed due to the power-on reset and the starting frequency of the internal crystal oscillator module is adjusted can be effectively avoided, the condition that the operating clock of the digital circuit is deformed due to the change of the frequency and the duty ratio of the internal crystal oscillator clock is further avoided, and further the condition that time sequence violations are caused due to the fact that the operating clock of the digital circuit is deformed, the trigger in the digital circuit enters a metastable state, and the digital circuit crashes is further avoided.
Optionally, the counting module is a 4-bit counter, a Reset port of the 4-bit counter is electrically connected with the condition module, a CP port of the 4-bit counter is electrically connected with the internal crystal oscillator module, and an ENB port and a carryover port of the 4-bit counter are electrically connected with the release module.
In a third aspect, the present application also provides a chip comprising a clock output circuit as provided in the second aspect above.
The chip provided by the application can release the internal crystal oscillator clock only when the number of the first clock cycles is greater than or equal to that of the second clock cycles, so that the chip can output the internal crystal oscillator clock with stable frequency and duty ratio, the situation that the running clock of the digital circuit is deformed due to the change of the frequency and the duty ratio of the internal crystal oscillator clock is effectively avoided, and further the situation that timing violations are caused due to the fact that the running clock of the digital circuit is deformed, and the flip-flop in the digital circuit enters a metastable state and the digital circuit crashes and dies are effectively avoided.
Therefore, the clock output method, the circuit and the chip can release the internal crystal oscillator clock only when the number of the first clock cycles is greater than or equal to that of the second clock cycles, so that the method can output the internal crystal oscillator clock with stable frequency and duty ratio, thereby effectively avoiding the situation that the running clock of the digital circuit is malformed due to the change of the frequency and the duty ratio of the internal crystal oscillator clock, and further effectively avoiding the situation that the time sequence is violated, a trigger in the digital circuit enters a metastable state and the digital circuit crashes and dies due to the malformed running clock of the digital circuit.
Drawings
Fig. 1 is a flowchart of a clock output method according to an embodiment of the present application.
Fig. 2 is a schematic structural diagram of a clock output circuit according to an embodiment of the present application.
Reference numerals: 1. an internal crystal oscillator module; 2. a condition module; 3. a counting module; 4. and releasing the module.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
In a first aspect, as shown in fig. 1-2, the present application provides a clock output method, applied in a clock output circuit, where the clock output circuit includes an internal crystal oscillator module 1 (crystal oscillator in fig. 2), and the internal crystal oscillator module 1 is configured to generate an internal crystal oscillator clock (osc_clk in fig. 2), and the clock output method includes the following steps:
s1, acquiring a first clock cycle number, wherein the first clock cycle number is the clock cycle number continuously generated when an internal crystal oscillator clock meets a first condition, and the first condition comprises that an enabling switch of an internal crystal oscillator module 1 is opened;
s2, when the number of the first clock cycles is greater than or equal to the number of the preset second clock cycles, releasing the internal crystal oscillator clock.
The clock output method is applied to a clock output circuit, is used for outputting a clock signal with stable frequency and stable duty ratio, and is particularly suitable for being used as an operation clock of a digital circuit. The internal crystal oscillator module 1 is used for generating an internal crystal oscillator clock, and the working principle of the internal crystal oscillator module 1 belongs to the prior art and is not discussed in detail here.
Because the internal crystal oscillator clock is a periodic signal, the step S1 may acquire the first clock cycle number by acquiring the rising edge number or the falling edge number of the internal crystal oscillator clock, and the step S1 may also acquire the first clock cycle number by acquiring the high level number or the low level number of the internal crystal oscillator clock. The first condition is a necessary condition to be satisfied when the internal crystal oscillator module 1 generates an internal crystal oscillator clock with stable frequency and stable duty ratio, and only when the first condition is satisfied, the internal crystal oscillator module 1 can generate the internal crystal oscillator clock with stable frequency and duty ratio. The enabling switch of the internal crystal oscillator module 1 is opened correspondingly under the following conditions: the internal crystal oscillator module 1 starts to start or restarts, and since the internal crystal oscillator module 1 needs a period of time to generate a correct and stable internal crystal oscillator clock after starting to generate the internal crystal oscillator clock, that is, the internal crystal oscillator clock generated at this time is unstable and may cause system breakdown, the internal crystal oscillator clock generated at this time cannot be used as an operation clock of the digital circuit, that is, the first condition includes that an enabling switch of the internal crystal oscillator module 1 is turned on. Because the first clock period number is the clock period number continuously generated by the internal crystal oscillator clock when the first condition is satisfied, the step S1 starts to acquire the time node of the first clock period number as the corresponding time node when the first condition is satisfied. It should be appreciated that this embodiment does not acquire the first number of clock cycles when the first condition is not met.
The second clock cycle number in step S2 is a preset value, where the second clock cycle number is the number of clock cycles required by the internal crystal oscillator module 1 to generate a correct and stable internal crystal oscillator clock after the first condition is satisfied, and the second clock cycle number can reflect the time required by the internal crystal oscillator module 1 to generate a correct and stable internal crystal oscillator clock after the first condition is satisfied, and a person skilled in the art can adjust the size of the second clock cycle number according to the actual need. Because the second clock cycle number is the clock cycle number required by the internal crystal oscillator module 1 to generate the internal crystal oscillator clock with correct stability after the first condition is met, if the first clock cycle number is greater than or equal to the second clock cycle number, the frequency and the duty cycle of the internal crystal oscillator clock are stable, so that when the first clock cycle number is greater than or equal to the second clock cycle number, the step S2 releases the internal crystal oscillator clock. It should be appreciated that if the internal crystal oscillator module 1 is first started, the number of first clock cycles is initially zero, so that the embodiment does not release the internal crystal oscillator clock when the internal crystal oscillator module 1 is first started and the number of first clock cycles is smaller than the number of second clock cycles; if the internal crystal oscillator module 1 restarts, the first number of clock cycles is refreshed, so that the embodiment stops releasing the internal crystal oscillator clock when the internal crystal oscillator module 1 restarts and the first number of clock cycles is less than the second number of clock cycles.
The working principle of the embodiment is as follows: when the first condition is met, the first clock cycle number is obtained, and the internal crystal oscillator clock is released according to the first clock cycle number and the second clock cycle number, and the internal crystal oscillator clock is released only when the first clock cycle number is greater than or equal to the second clock cycle number, so that the method can output the internal crystal oscillator clock with stable frequency and duty ratio, thereby effectively avoiding the situation that the running clock of the digital circuit is abnormal due to the change of the frequency and the duty ratio of the internal crystal oscillator clock, and further effectively avoiding the situation that the time sequence violations are caused due to the abnormal running clock of the digital circuit, the flip-flop in the digital circuit enters a metastable state, and the digital circuit crashes.
According to the clock output method, the internal crystal oscillator clock can be released only when the number of the first clock cycles is larger than or equal to that of the second clock cycles, so that the method can output the internal crystal oscillator clock with stable frequency and duty ratio, the situation that the running clock of the digital circuit is deformed due to the fact that the frequency and the duty ratio of the internal crystal oscillator clock are changed is effectively avoided, and further the situation that time sequence violations are caused due to the fact that the running clock of the digital circuit is deformed, the trigger in the digital circuit enters a metastable state, and the digital circuit crashes and dies are effectively avoided.
In some embodiments, the first condition further includes that the power-on reset is completed and/or that the start-up frequency adjustment of the internal crystal oscillator module 1 is completed. Since the internal crystal oscillator module 1 may restart or the frequency and the duty ratio of the internal crystal oscillator clock may change when the power-on reset and the oscillation starting frequency of the internal crystal oscillator module 1 are adjusted, that is, the internal crystal oscillator clock generated at this time is unstable and cannot be used as an operation clock of the digital circuit, the first condition further includes that the power-on reset is completed and/or the oscillation starting frequency adjustment of the internal crystal oscillator module 1 is finished. The first condition further comprises that the power-on reset is completed and/or the starting frequency adjustment of the internal crystal oscillator module 1 is finished, so that the situation that the frequency and the duty ratio of the internal crystal oscillator clock are changed due to the power-on reset and the starting frequency adjustment of the internal crystal oscillator module 1 can be effectively avoided, the situation that the operating clock of the digital circuit is deformed due to the change of the frequency and the duty ratio of the internal crystal oscillator clock is further avoided, and further the situation that timing violations are caused due to the abnormal condition of the operating clock of the digital circuit, the trigger in the digital circuit enters a metastable state and the digital circuit crashes and dies are further avoided.
Example 1
The clock output circuit stores enable switch flag bit information, power-on reset flag bit information and/or oscillation starting frequency adjustment flag bit information, the enable switch flag bit information is used for identifying whether an enable switch of the internal crystal oscillator module 1 is turned on, the power-on reset flag bit information is used for identifying whether the power-on reset of the internal crystal oscillator module 1 is completed, and the oscillation starting frequency adjustment flag bit information is used for identifying whether the oscillation starting frequency of the internal crystal oscillator module 1 is adjusted.
If the clock output circuit stores the enable switch flag bit information and the power-on reset flag bit information, the first condition at this time is: the enable switch flag bit information identifies that the enable switch of the internal crystal oscillator module 1 is turned on and the power-on reset flag bit information identifies that the power-on reset of the internal crystal oscillator module 1 is completed.
If the clock output circuit stores the enable switch flag bit information and the oscillation starting frequency adjustment flag bit information, the first condition at this time is: the enable switch flag bit information identifies that the enable switch of the internal crystal oscillator module 1 is turned on and the oscillation starting frequency adjustment flag bit information identifies that the oscillation starting frequency adjustment of the internal crystal oscillator module 1 is ended.
If the clock output circuit stores the enable switch flag bit information, the power-on reset flag bit information and the oscillation starting frequency adjustment flag bit information, the first condition at this time is: the enabling switch flag bit information indicates that an enabling switch of the internal crystal oscillator module 1 is turned on, the power-on reset flag bit information indicates that power-on reset of the internal crystal oscillator module 1 is completed, and the oscillation starting frequency adjustment flag bit information indicates that oscillation starting frequency adjustment of the internal crystal oscillator module 1 is completed.
Example 2
The clock output circuit comprises an enabling switch detection module, a power-on reset detection module and a starting frequency adjustment module, wherein the enabling switch detection module is used for detecting whether an enabling switch of the internal crystal oscillator module 1 is opened, the power-on reset detection module is used for detecting whether power-on reset is completed, and the starting frequency adjustment module is used for detecting whether the starting frequency of the internal crystal oscillator module 1 is adjusted to be ended.
If the clock output circuit includes an enable switch detection module and a power-on reset detection module, the first condition is: the enabling switch detection module detects that an enabling switch of the internal crystal oscillator module 1 is turned on, and the power-on reset detection module detects that power-on reset is completed.
If the clock output circuit comprises an enabling switch detection module and a starting frequency adjustment module, the first condition is that: the enabling switch detection module detects that an enabling switch of the internal crystal oscillator module 1 is turned on, and the starting frequency adjustment module detects that starting frequency adjustment of the internal crystal oscillator module 1 is finished.
If the clock output circuit comprises an enabling switch detection module, a power-on reset detection module and/or a starting frequency adjustment module, the first condition is that: the enabling switch detection module detects that an enabling switch of the internal crystal oscillator module 1 is turned on, the power-on reset detection module detects that power-on reset is completed, and the starting frequency adjustment module detects that starting frequency adjustment of the internal crystal oscillator module 1 is finished.
The clock output method provided by the present application can determine whether the first condition is satisfied by embodiment 1 or embodiment 2.
In some embodiments, if the enable switch flag information identifies that the enable switch of the internal crystal oscillator module 1 is turned on, the enable switch flag information is 1, if the enable switch flag information identifies that the enable switch of the internal crystal oscillator module 1 is turned off, the enable switch flag information is 0, if the power-on reset flag information identifies that the power-on reset of the internal crystal oscillator module 1 is incomplete, the power-on reset flag information is 0, if the power-on reset flag information identifies that the power-on reset of the internal crystal oscillator module 1 is complete, the power-on reset flag information is 1, if the start-up frequency adjustment flag information identifies that the start-up frequency of the internal crystal oscillator module 1 is not adjusted, the start-up frequency adjustment flag information is 0, and if the start-up frequency adjustment flag information identifies that the start-up frequency adjustment of the internal crystal oscillator module 1 is ended, the start-up frequency adjustment flag information is 1, the first condition is: osc_en=1 & & por_n=1 & & change_osc_trim_b=1;
wherein osc_en represents enable switch flag bit information, por_n represents power-on reset flag bit information, and change_osc_trim_b represents oscillation starting frequency adjustment flag bit information. It should be appreciated that, since the reset signal is low after the power-on reset is completed, in this embodiment, if the power-on reset flag information identifies that the power-on reset of the internal crystal oscillator module 1 is completed, the power-on reset flag information is 1, and thus the power-on reset flag information in this embodiment is substantially the inverse signal of the reset signal.
In some embodiments, the step of obtaining the first number of clock cycles comprises:
the number of rising edges of the internal crystal oscillator clock is counted based on the counting module 3 to obtain the number of first clock cycles.
The counting module 3 of this embodiment is a prior art which is capable of counting the number of rising edges of an internal crystal oscillator clock, the working principle of which is not discussed in detail here.
Therefore, the clock output method can only release the internal crystal oscillator clock when the number of the first clock period is greater than or equal to that of the second clock period, so that the clock output method can output the internal crystal oscillator clock with stable frequency and duty ratio, thereby effectively avoiding the situation that the running clock of the digital circuit is malformed due to the change of the frequency and the duty ratio of the internal crystal oscillator clock, and further effectively avoiding the situation that the time sequence is abnormal due to the malformed running clock of the digital circuit, the trigger in the digital circuit enters a metastable state, and the digital circuit crashes and dies.
In a second aspect, the present application also provides a clock output circuit, the clock output circuit comprising:
the internal crystal oscillator module 1 is used for generating an internal crystal oscillator clock;
the condition module 2 is used for judging whether a first condition is met, wherein the first condition comprises that an enabling switch of the internal crystal oscillator module 1 is opened;
the counting module 3 is electrically connected with the condition module 2 and the internal crystal oscillator module 1, and is used for obtaining the first clock cycle number, wherein the first clock cycle number is the clock cycle number continuously generated by the internal crystal oscillator clock when the first condition is met, and outputting a high-level signal when the first clock cycle number is greater than or equal to the preset second clock cycle number;
and the releasing module 4 is electrically connected with the internal crystal oscillator module 1, the condition module 2 and the counting module 3 and is used for releasing the internal crystal oscillator clock when receiving the high-level signal output by the counting module 3.
The clock output circuit is used for outputting a clock signal with stable frequency and stable duty ratio, and is particularly suitable for being used as an operation clock of a digital circuit. The internal crystal oscillator module 1 is used for generating an internal crystal oscillator clock, and the working principle of the internal crystal oscillator module 1 belongs to the prior art and is not discussed in detail here.
The condition module 2 is configured to determine whether a first condition is satisfied, where the first condition is a necessary condition that needs to be satisfied when the internal crystal oscillator module 1 generates an internal crystal oscillator clock with stable frequency and stable duty cycle, and only when the first condition is satisfied, the internal crystal oscillator module 1 may generate the internal crystal oscillator clock with stable frequency and stable duty cycle. The enabling switch of the internal crystal oscillator module 1 is opened correspondingly under the following conditions: the internal crystal oscillator module 1 starts to start or restarts, and since the internal crystal oscillator module 1 needs a period of time to generate a correct and stable internal crystal oscillator clock after starting, that is, the internal crystal oscillator clock generated at this time is unstable and cannot be used as an operation clock of the digital circuit, the first condition includes that an enable switch of the internal crystal oscillator module 1 is turned on.
The counting module 3 is in the prior art, the counting module 3 is electrically connected with the condition module 2 and the internal crystal oscillator module 1, the counting module 3 is used for obtaining the number of first clock cycles, and outputting a high-level signal when the number of the first clock cycles is greater than or equal to the number of preset second clock cycles, the number of the second clock cycles is a preset value, the number of the second clock cycles is the number of clock cycles required by the internal crystal oscillator module 1 to generate a correct and stable internal crystal oscillator clock after the first condition is met, the number of the second clock cycles can reflect the time required by the internal crystal oscillator module 1 to generate the correct and stable internal crystal oscillator clock after the first condition is met, and a person skilled in the art can adjust the size of the number of the second clock cycles according to actual needs. The counting module 3 may obtain the first clock cycle number by counting the rising edge number or the falling edge number of the internal crystal oscillator clock, and the counting module 3 may also obtain the first clock cycle number by counting the high level number or the low level number of the internal crystal oscillator clock. Because the first clock cycle number is the clock cycle number continuously generated by the internal crystal oscillator clock when the first condition is met, the counting module 3 starts to acquire the time node of the first clock cycle number, which is the corresponding time node when the condition module 2 judges that the first condition is met. It should be appreciated that the counting module 3 of this embodiment does not acquire the first number of clock cycles when the condition module 2 determines that the first condition is not satisfied.
The releasing module 4 is electrically connected with the internal crystal oscillator module 1, the condition module 2 and the counting module 3, and the releasing module 4 is used for releasing the internal crystal oscillator clock when receiving the high-level signal output by the counting module 3.
The working principle of the embodiment is as follows: when the first condition is met, the first clock cycle number is obtained, the internal crystal oscillator clock is released according to the first clock cycle number and the second clock cycle number, and the internal crystal oscillator clock can be released only when the first clock cycle number is greater than or equal to the second clock cycle number, so that the circuit can output the internal crystal oscillator clock with stable frequency and duty ratio, the situation that the running clock of the digital circuit is abnormal due to the fact that the frequency and the duty ratio of the internal crystal oscillator clock are changed is effectively avoided, and further the situation that time sequence violations are caused due to the fact that the running clock of the digital circuit is abnormal, and the flip-flop in the digital circuit enters a metastable state and the digital circuit crashes is effectively avoided.
The clock output circuit provided by the application can release the internal crystal oscillator clock only when the number of the first clock cycles is greater than or equal to that of the second clock cycles, so that the circuit can output the internal crystal oscillator clock with stable frequency and duty ratio, the situation that the running clock of the digital circuit is abnormal due to the fact that the frequency and the duty ratio of the internal crystal oscillator clock are changed is effectively avoided, and further the situation that time sequence violations are caused by the fact that the running clock of the digital circuit is abnormal, and the trigger in the digital circuit enters a metastable state and the digital circuit crashes is effectively avoided.
Preferably, in some embodiments, the releasing module 4 includes a D flip-flop and a clock gating module (ICG in fig. 2), where a CLR port of the D flip-flop is electrically connected to the condition module 2, a D port of the D flip-flop is electrically connected to the counting module 3, a CP port of the D flip-flop is electrically connected to the internal crystal oscillator module 1, and two input ends of the clock gating module are electrically connected to a Q port of the D flip-flop and the internal crystal oscillator module 1, respectively. The D flip-flop and the clock gating module of this embodiment are both in the prior art, when the D end of the D flip-flop receives the high level signal output by the counting module 3, the Q end of the D flip-flop also outputs the high level signal, and the clock gating module releases the internal crystal oscillator clock after receiving the high level signal of the D flip-flop.
Preferably, in some embodiments, the counting module 3 is a 4-bit counter, the Reset port of the 4-bit counter is electrically connected with the conditioning module 2, the CP port of the 4-bit counter is electrically connected with the internal crystal oscillator module 1, and the ENB port and the carryover port of the 4-bit counter are electrically connected with the releasing module 4. Specifically, B in FIG. 2 1 -B 4 The ports are the count bits of a 4-bit counter, and the release module 4 includes a D flip-flop and a clock gating module, and the ENB port and the carryover port of the 4-bit counter of this embodiment are electrically connected to the D port of the D flip-flop.
Preferably, in some embodiments, the first condition further includes that the power-on reset is completed and/or the starting frequency adjustment of the internal crystal oscillator module 1 is finished, and the condition module 2 is a multiple input and gate. If the first condition includes that the enable switch of the internal crystal oscillator module 1 is turned on and the power-on reset is completed, the multiple-input and gate includes two input terminals electrically connected to the enable switch signal terminal (osc_en terminal in fig. 2) and the power-on reset signal terminal (por_n terminal in fig. 2), respectively; if the first condition includes that the enabling switch of the internal crystal oscillator module 1 is turned on and the oscillation starting frequency adjustment of the internal crystal oscillator module 1 is finished, the multi-input and gate comprises two input ends which are respectively electrically connected with the enabling switch signal end and the oscillation starting frequency adjustment signal end (change_osc_trim_b end in fig. 2); if the first condition includes that the enabling switch of the internal crystal oscillator module 1 is turned on, the power-on reset is completed, and the oscillation starting frequency of the internal crystal oscillator module 1 is adjusted, the multi-input and gate comprises three input ends which are respectively electrically connected with the enabling switch signal end, the power-on reset signal end and the oscillation starting frequency adjusting signal end.
The first condition further comprises that the power-on reset is completed and/or the starting frequency adjustment of the internal crystal oscillator module 1 is finished, so that the situation that the frequency and the duty ratio of the internal crystal oscillator clock are changed due to the power-on reset and the starting frequency adjustment of the internal crystal oscillator module 1 can be effectively avoided, the situation that the operating clock of the digital circuit is deformed due to the change of the frequency and the duty ratio of the internal crystal oscillator clock is further avoided, and further the situation that timing violations are caused due to the abnormal condition of the operating clock of the digital circuit, the trigger in the digital circuit enters a metastable state and the digital circuit crashes and dies are further avoided.
Therefore, the clock output circuit can release the internal crystal oscillator clock only when the number of the first clock cycles is greater than or equal to that of the second clock cycles, so that the circuit can output the internal crystal oscillator clock with stable frequency and duty ratio, the situation that the running clock of the digital circuit is malformed due to the fact that the frequency and the duty ratio of the internal crystal oscillator clock are changed is effectively avoided, and further the situation that time sequence violations are caused due to the fact that the running clock of the digital circuit is malformed, the trigger in the digital circuit enters a metastable state, and the digital circuit crashes and dies are effectively avoided.
In a third aspect, the present application also provides a chip comprising a clock output circuit as provided in the second aspect above.
The working principle of the chip provided in the embodiments of the present application is the same as that of the clock output circuit provided in the second aspect, and will not be discussed in detail here.
Therefore, the chip can output the internal crystal oscillator clock with stable frequency and duty ratio only when the number of the first clock cycles is larger than or equal to that of the second clock cycles, so that the situation that the running clock of the digital circuit is abnormal due to the fact that the frequency and the duty ratio of the internal crystal oscillator clock are changed is effectively avoided, and further the situation that time sequence violations are caused due to the fact that the running clock of the digital circuit is abnormal, the trigger in the digital circuit enters a metastable state, and the digital circuit crashes and dies are effectively avoided.
Therefore, the clock output method, the circuit and the chip can release the internal crystal oscillator clock only when the number of the first clock cycles is greater than or equal to that of the second clock cycles, so that the method can output the internal crystal oscillator clock with stable frequency and duty ratio, thereby effectively avoiding the situation that the running clock of the digital circuit is malformed due to the change of the frequency and the duty ratio of the internal crystal oscillator clock, and further effectively avoiding the situation that the time sequence is violated, a trigger in the digital circuit enters a metastable state and the digital circuit crashes and dies due to the malformed running clock of the digital circuit.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The above described embodiments of the apparatus are only illustrative, e.g. the above described division of units is only one logical function division, and there may be another division in practice, and e.g. multiple units or components may be combined or integrated into another robot, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may rise to one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
Furthermore, functional modules in various embodiments of the present application may be integrated together to form a single portion, or each module may exist alone, or two or more modules may be integrated to form a single portion.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The foregoing is merely exemplary embodiments of the present application and is not intended to limit the scope of the present application, and various modifications and variations may be suggested to one skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
Claims (7)
1. The clock output method is characterized in that the clock output method is applied to a clock output circuit, the clock output circuit comprises an internal crystal oscillator module, the clock output circuit stores enable switch flag bit information, power-on reset flag bit information and/or starting frequency adjustment flag bit information, the enable switch flag bit information is used for identifying whether an enable switch of the internal crystal oscillator module is opened or not, the power-on reset flag bit information is used for identifying whether power-on reset of the internal crystal oscillator module is completed or not, the starting frequency adjustment flag bit information is used for identifying whether starting frequency of the internal crystal oscillator module is completed or not, if the enable switch flag bit information identifies that the enable switch of the internal crystal oscillator module is opened, the enable switch flag bit information is 1, if the enable switch flag bit information identifies that the enable switch of the internal crystal oscillator module is closed, the enable switch flag bit information is 0, if the power-on reset flag bit information identifies that the internal crystal oscillator module is not completed in power-on reset, the power-on reset flag bit information is 0, if the power-on reset flag bit information identifies that the power-on reset of the internal crystal oscillator module is completed by the internal crystal oscillator module is completed, the starting frequency adjustment flag bit information is 1, the enable switch flag bit information indicates that the internal crystal oscillator module is not completed in the power-on reset frequency, and the internal crystal oscillator module is reset by the internal crystal oscillator module is adjusted by the frequency, and the 1.
Acquiring a first clock cycle number, wherein the first clock cycle number is the clock cycle number continuously generated by the internal crystal oscillator clock when a first condition is met, and the first condition is that: osc_en=1 & & por_n=1 & & change_osc_trim_b=1;
wherein osc_en represents enable switch flag bit information, por_n represents power-on reset flag bit information, and change_osc_trim_b represents oscillation starting frequency adjustment flag bit information;
and when the number of the first clock cycles is greater than or equal to the number of the preset second clock cycles, releasing the internal crystal oscillator clock.
2. The method of claim 1, wherein the step of obtaining the first number of clock cycles comprises:
and counting the rising edge number of the internal crystal oscillator clock based on a counting module so as to acquire the first clock cycle number.
3. The clock output circuit is characterized by comprising an internal crystal oscillator module, wherein the internal crystal oscillator module is used for generating an internal crystal oscillator clock, the clock output circuit stores enable switch flag bit information, power-on reset flag bit information and/or starting frequency adjustment flag bit information, the enable switch flag bit information is used for marking whether an enable switch of the internal crystal oscillator module is opened or not, the power-on reset flag bit information is used for marking whether the power-on reset of the internal crystal oscillator module is completed or not, the starting frequency adjustment flag bit information is used for marking whether the starting frequency of the internal crystal oscillator module is completed or not, if the enable switch flag bit information marks that the enable switch of the internal crystal oscillator module is opened, the enable switch flag bit information is 1, if the enable switch flag bit information marks that the enable switch of the internal crystal oscillator module is closed, the enable switch flag bit information is 0, if the power-on reset flag bit information marks that the internal crystal oscillator module is not completed, the power-on reset flag bit information is 0, the power-on reset flag bit information is 1, and if the power-on reset flag bit information is marked that the starting frequency of the internal crystal oscillator module is completed, the internal crystal oscillator module is not completed, the starting frequency adjustment flag bit information is 1, and the enable switch flag bit information is adjusted, and the internal crystal oscillator module is not reset, and the starting frequency is adjusted.
The condition module is used for judging whether a first condition is met, and the first condition is as follows: osc_en=1 & & por_n=1 & & change_osc_trim_b=1;
wherein osc_en represents enable switch flag bit information, por_n represents power-on reset flag bit information, and change_osc_trim_b represents oscillation starting frequency adjustment flag bit information;
the counting module is electrically connected with the condition module and the internal crystal oscillator module, and is used for obtaining the first clock cycle number, wherein the first clock cycle number is the clock cycle number continuously generated when the internal crystal oscillator clock meets the first condition, and outputting a high-level signal when the first clock cycle number is greater than or equal to the preset second clock cycle number;
and the releasing module is electrically connected with the internal crystal oscillator module, the condition module and the counting module and is used for releasing the internal crystal oscillator clock when receiving the high-level signal output by the counting module.
4. The clock output circuit of claim 3, wherein the release module comprises a D flip-flop and a clock gating module, wherein a CLR port of the D flip-flop is electrically connected with the condition module, a D port of the D flip-flop is electrically connected with the counting module, a CP port of the D flip-flop is electrically connected with the internal crystal oscillator module, and two input ends of the clock gating module are electrically connected with a Q port of the D flip-flop and the internal crystal oscillator module, respectively.
5. A clock output circuit as claimed in claim 3, wherein the condition module is a multiple input and gate.
6. The clock output circuit of claim 3, wherein the counting module is a 4-bit counter, a Reset port of the 4-bit counter is electrically connected to the conditioning module, a CP port of the 4-bit counter is electrically connected to the internal crystal oscillator module, and an ENB port and a carryover port of the 4-bit counter are electrically connected to the release module.
7. A chip comprising a clock output circuit as claimed in any one of claims 3 to 6.
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