CN116598357A - Trench type power MOSFET device integrated with Schottky diode and manufacturing method - Google Patents
Trench type power MOSFET device integrated with Schottky diode and manufacturing method Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The application discloses a groove type power MOSFET device integrated with a Schottky diode and a manufacturing method thereof. The device comprises: the epitaxial layer and the MOSFET structure are positioned on the top of the epitaxial layer; the MOSFET structure comprises: a plurality of cells with the same shape and structure, a first highly doped P-type region and a groove; each cell comprises a well region, a source region, a second highly doped P-type region, a Schottky region and a JFET region; the well region and the epitaxial layer form a first PN junction; the source electrode region and the well region form a second PN junction; forming a schottky region in the well region and the inner surrounding region of the second highly doped P-type region; the groove is positioned between the cells, and the bottom of the groove is wrapped by the first highly doped P-type region; forming a third PN junction between the first highly doped P-type region and the epitaxial layer; and a junction field effect tube JFET region is formed between the well region and the adjacent first high-doped P-type region. The technical problem that the schottky structure and the MOSFET structure occupy the active area of the device together and cannot be considered in both electrical performance is solved.
Description
Technical Field
The application relates to the technical field of power semiconductor manufacturing, in particular to a groove type power MOSFET device integrated with a Schottky diode and a manufacturing method thereof.
Background
Basal Plane Dislocations (BPD) exist in silicon carbide crystals, and under certain conditions, the Basal Plane Dislocations (BPD) may be converted into Stacking Faults (SF). When the body diode in a silicon carbide power MOSFET device is turned on, electron-hole recombination can continue to expand the Stacking Fault (SF) under bipolar operation, causing bipolar degradation. This phenomenon increases the on-resistance of the silicon carbide power MOSFET, increases the leakage current in the blocking mode, and increases the on-voltage drop of the body diode, thereby reducing the reliability of the device.
In practical circuit applications, to avoid bipolar degradation, designers typically use external anti-parallel schottky diodes to suppress the body diode in the power MOSFET device. However, for cost reasons, a schottky diode may be embedded into each cell unit in a power MOSFET device while the entire device shares the same termination structure, which may reduce the overall chip size.
For the silicon carbide trench type power MOSFET device with the Schottky diode integrated in the cell, the Schottky structure and the MOSFET structure occupy the active area part of the device together, so that the two have a trade-off and trade-off contradiction relationship. If the two are unbalanced, larger MOSFET conduction loss can be caused, or the current conduction capacity of the Schottky diode is weaker, and the comprehensive electrical performance of the device is reduced.
Disclosure of Invention
The embodiment of the application provides a groove type power MOSFET device integrated with a Schottky diode and a manufacturing method thereof, which are used for solving the following technical problems: the schottky structure and the MOSFET structure occupy the active area of the device together, if the schottky structure and the MOSFET structure are unbalanced, larger MOSFET conduction loss can be caused, or the current conduction capacity of the schottky diode is weaker, and the practicability of the device is reduced.
In one aspect, an embodiment of the present application provides a trench power MOSFET device integrated with a schottky diode, where the device includes: the epitaxial layer and the MOSFET structure are positioned on the top of the epitaxial layer; the epitaxial layer is an N-type region; the MOSFET structure comprises: a plurality of cells with the same shape and structure, a first highly doped P-type region and a groove; each cell comprises a well region, a source region, a second highly doped P-type region, a Schottky region and a JFET region; wherein: the well region is a P-type region, and the source region is an N-type region; the Schottky region is positioned in the central region of the cell, the well region and the second highly doped P-type region encircle the Schottky region, and the source region encircles the second highly doped P-type region; the well region is positioned on the top surface of the epitaxial layer and forms a first PN junction with the epitaxial layer; the source electrode region and the second highly doped P-type region are both positioned on the surface of one side, away from the epitaxial layer, of the well region, and the well region and the source electrode region form a second PN junction; the grooves are positioned among cells, the cross sections of the grooves among the cells are U-shaped, and the corners at the bottom of the grooves are fillets; the first highly doped P-type region wraps the bottom of the groove; the first highly doped P-type region and the epitaxial layer form a third PN junction; and a Junction Field Effect Transistor (JFET) region is formed between the well region and the adjacent first highly doped P-type region.
In one implementation of the present application, the MOSFET structure further includes: ohmic contact metal, schottky contact metal; the ohmic contact metal covers the top of the second highly doped P-type region and part of the source electrode region, and forms ohmic contact with the second highly doped P-type region and part of the source electrode region at the contact position at the same time so as to inhibit parasitic bipolar transistor effect in the MOSFET device; the schottky contact metal covers the top of the schottky region and forms a schottky contact at the contact location.
In one implementation of the present application, the MOSFET structure further includes: insulating the gate oxide layer from the gate conductive polysilicon; the insulating gate oxide layer covers the inner wall of the groove; the gate conductive polysilicon fills the trench.
In one implementation of the present application, the MOSFET structure further includes: an insulating dielectric layer; and the insulating medium layer covers the top of the filled groove and the top of part of the source electrode area of each cell.
In one implementation of the present application, the device further includes: a source electrode; the source electrode is covered on the ohmic contact metal and the Schottky contact metal; the insulating dielectric layer separates the gate conductive polysilicon from the source metal.
In one implementation of the present application, the device further includes: a silicon carbide substrate, a drain electrode; the top of the silicon carbide substrate is contacted with the bottom of the epitaxial layer; wherein the silicon carbide substrate is an N-type region; the drain electrode covers the bottom of the silicon carbide substrate.
In one implementation of the application, the ion doping concentration in the silicon carbide substrate is greater than the ion doping concentration in the epitaxial layer; and the ion doping concentration of the JFET region and the Schottky region is greater than or equal to that of the epitaxial layer.
In one implementation of the present application, the value range of the width of the JFET region and the value range of the width of the schottky region are both within the same preset interval; wherein the preset interval is [ 0.8-5 μm ].
In one implementation of the present application, the shape of the cells is circular or polygonal.
On the other hand, the embodiment of the application also provides a manufacturing method of the trench type power MOSFET device integrated with the Schottky diode, which is characterized by comprising the following steps: s1, forming a silicon carbide substrate, and forming an epitaxial layer on one surface of the silicon carbide substrate; s2, forming a reinforced Schottky region of the first conductivity type on the surface of the epitaxial layer; s3, forming a plurality of well regions of the second conductivity type on the surface of the epitaxial layer; wherein the first conductivity type is N type, and the second conductivity type is P type; s4, forming a plurality of highly doped source regions of the first conductivity type inside the well region containing the second conductivity type; s5, forming a plurality of groove structures on the surface of the epitaxial layer; s6, forming a reinforced JFET region of a first conductivity type on the side wall of the groove; s7, forming a plurality of first highly doped P-type regions at the bottom of the groove, and forming a plurality of second highly doped P-type regions on the surface of the platform; s8, forming an insulating gate oxide layer at the bottom and the side wall of the groove; s9, forming grid conductive polysilicon in the groove, filling the groove, and enabling the height of the grid conductive polysilicon to be close to the position flush with the epitaxial layer platform; s10, forming a plurality of insulating medium layers on the surface of the device; s11, forming ohmic contact metal above a source region of the high doping first conductivity type and a second high doping P-type region on the surface of the device; s12, forming a Schottky contact metal above the reinforced Schottky region of the surface of the device; s13, forming a source electrode at the top of the device; s14, forming a drain electrode on the other surface of the silicon carbide substrate.
According to the trench type power MOSFET device integrating the Schottky diode and the manufacturing method, the Schottky diode is integrated in the cell structure of the trench type power MOSFET, and the performance of the Schottky diode and the performance of the trench type power MOSFET are balanced and balanced through the layout of circular or polygonal cells. The MOSFET and the Schottky diode simultaneously realize lower conduction loss, and the comprehensive electrical performance of the device is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:
fig. 1 is a cross-sectional view of an active area of a trench type power MOSFET device integrated with a schottky diode according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a regular hexagonal cell structure according to an embodiment of the present application;
fig. 3 is a cross-sectional view of an active region of another trench-type power MOSFET device incorporating a schottky diode according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a circular cell structure according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a regular quadrilateral cell according to an embodiment of the present application;
FIG. 6 is a schematic diagram of another regular quadrilateral cell according to an embodiment of the present application;
fig. 7 is a schematic diagram of a step 1 of a method for manufacturing a MOSFET device according to an embodiment of the present application;
fig. 8 is a schematic diagram of step 2 of a method for manufacturing a MOSFET device according to an embodiment of the present application;
fig. 9 is a schematic diagram of step 3 of a method for manufacturing a MOSFET device according to an embodiment of the present application;
fig. 10 is a schematic diagram of a step 4 of a method for manufacturing a MOSFET device according to an embodiment of the present application;
fig. 11 is a schematic diagram of a 5 th step of a method for manufacturing a MOSFET device according to an embodiment of the present application;
fig. 12 is a schematic diagram of a step 6 of a method for manufacturing a MOSFET device according to an embodiment of the present application;
fig. 13 is a schematic diagram of a step 7 of a method for manufacturing a MOSFET device according to an embodiment of the present application;
fig. 14 is a schematic diagram of step 8 of a method for manufacturing a MOSFET device according to an embodiment of the present application;
fig. 15 is a schematic diagram of step 9 of a method for manufacturing a MOSFET device according to an embodiment of the present application;
fig. 16 is a schematic diagram of a 10 th step of a method for manufacturing a MOSFET device according to an embodiment of the present application;
fig. 17 is a schematic diagram of step 11 of a method for manufacturing a MOSFET device according to an embodiment of the present application;
fig. 18 is a schematic diagram of step 12 of a method for manufacturing a MOSFET device according to an embodiment of the present application;
fig. 19 is a schematic diagram of step 13 of a method for manufacturing a MOSFET device according to an embodiment of the present application;
fig. 20 is a schematic diagram of step 2 of another MOSFET device manufacturing method according to an embodiment of the present application.
Reference numerals illustrate:
a cell 10; a silicon carbide substrate 101; an epitaxial layer 102; a well region 103; a source region 104; a second highly doped P-type region 105; an insulating gate oxide layer 106; gate conductive polysilicon 107; an insulating dielectric layer 108; ohmic contact metal 109; a schottky contact metal 110; a source electrode 111; a drain electrode 112; JFET region 113; a schottky region 114; a first PN junction 115; a second PN junction 116; a trench 117; a first highly doped P-type region 118; and a third PN junction 119.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be clearly and completely described below with reference to specific embodiments of the present application and corresponding drawings. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The embodiment of the application provides a groove type power MOSFET device integrating a Schottky diode and a manufacturing method thereof, which are used for solving the technical problem that the existing Schottky structure and MOSFET structure have conflict when the active area part of the device is occupied together.
The following describes the technical scheme provided by the embodiment of the application in detail through the attached drawings.
Fig. 1 is a cross-sectional view of an active area of a trench type power MOSFET device integrated with a schottky diode according to an embodiment of the present application. As shown in fig. 1, the schottky diode integrated trench power MOSFET device includes an epitaxial layer 102; the epitaxial layer is an N-type region. In addition, as shown in fig. 1, a MOSFET structure is provided on top of the epitaxial layer 102.
It should be noted that, under the same device area, due to the MOSFET device designed by the circular and polygonal cells, a higher channel width and total area of JFET region can be achieved, and thus a lower specific on-resistance can be achieved. Therefore, the cell shape in the embodiment of the present application is designed in a polygonal shape or a circular shape.
In fig. 2, a schematic structural diagram of a regular hexagonal cell is provided according to an embodiment of the present application, and taking the regular hexagonal cell structure shown in fig. 2 as an example, a cross-sectional view corresponding to a dashed line AA' in fig. 2 is a cross-sectional view of an active area of a trench type power MOSFET device integrated with a schottky diode shown in fig. 1. As can be seen in conjunction with fig. 1 and 2, the MOSFET structure on top of the epitaxial layer includes: a plurality of cells 10 with the same shape and structure, a first highly doped P-type region 118, and a trench 117; each cell 10 includes: well 103, source 104, second highly doped P-type 105, schottky 114, JFET 113, trench 117 between cells 10, and first highly doped P-type 118 at the bottom of trench 117.
It should be noted that, since the first heavily doped P-type region 118 wraps around the bottom of the trench 117, the two portions overlap in the top view of fig. 2, the solid line in fig. 2 represents the trench boundary, and the two-dot chain line represents the boundary projection of the first heavily doped P-type region 118 at the bottom of the trench on the epitaxial layer platform portion. Meanwhile, the well region 103 is blocked by the source region 104 and the second highly doped P-type region 105, and thus cannot be shown in fig. 2.
As shown in fig. 2, the boundaries of the trench 117, the source region 104, the second highly doped P-type region 105 and the schottky region 114 are all regular hexagons in shape, and the center points coincide. As can be seen from fig. 1, the well region 103 of the cell 10 is also regular hexagon in shape and has the same center point as other structures of the cell 10.
Further, as shown in fig. 1, each cell 10 has a structure as follows: the well region 103 is located on the top surface of the epitaxial layer 102, and forms a first PN junction 115 with the epitaxial layer 102; the source region 104 and the second highly doped P-type region 105 are both located on a side surface of the well region 103 away from the epitaxial layer 102, the well region 103 and the source region 104 form a second PN junction 116, the schottky region 114 is located in a central region of the cell 10, the well region 103 and the second highly doped P-type region 105 surround the schottky region 114, and the source region 104 surrounds the second highly doped P-type region 105.
Further, the grooves 117 are positioned among the cells 10, the cross sections of the grooves among the cells 10 are U-shaped, and the corners of the bottoms of the grooves 117 are rounded; the first highly doped P-type region 118 wraps around the bottom of the trench 117; the first highly doped P-type region 118 and the epitaxial layer 102 form a third PN junction 119;
further, a junction field effect transistor JFET region 113 is formed between the well region 103 of the cell 10 and the adjacent first highly doped P-type region 118.
Further, as shown in fig. 2, the cross-sectional view corresponding to the dashed line BB' in fig. 2 is a cross-sectional view of the active region of another trench type power MOSFET device integrated with a schottky diode shown in fig. 3. As can be seen from fig. 1 and 3, the ion implantation depth of the source region 104 in the cell 10 is smaller than the ion implantation depth of the well region 103, and the ion implantation depth of the second highly doped P-type region 105 may be smaller than, equal to, or greater than the ion implantation depth of the well region 103.
It should be noted that the well region 103, the second highly doped P-type region 105, and the first highly doped P-type region 118 are P-type regions, and the source region 104 is an N-type region.
In one embodiment of the present application, the ion doping concentration range of the well region 103 is: 5E15cm -3 ～1E19cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The ion doping concentration range of the source region 104 is: 1E18cm -3 ～1E22cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The ion doping concentration ranges of the second highly doped P-type region 105 and the first highly doped P-type region 118 are as follows: 1E18cm -3 ～1E22 cm -3 。
It should be noted that, due to the design of the width n and the ion doping concentration of the JFET region 113, it is necessary to ensure that the MOSFET has a small on-resistance, and in the blocking mode, the well region 103 and the adjacent first highly doped P-type region 118 can play an effective role in electric field shielding, so as to ensure the reliability of the device. Similarly, the ion doping concentration and the width s in the schottky region 114 need to ensure that the schottky diode has sufficient current conduction capability, and in the blocking mode, the adjacent second highly doped P-type region 105 can play an effective role in shielding an electric field, so as to ensure the reliability of the device. Therefore, in the embodiment of the present application, the value range of the width n of the JFET region 113 and the value range of the width s of the schottky region 114 are all within the preset interval; the ion doping concentration in JFET region 113, the ion doping concentration in schottky region 114, are all greater than or equal to the ion doping concentration of epitaxial layer 102.
In one embodiment of the present application, the preset interval is 0.8um to 5um; the ion doping concentration ranges in JFET region 113 and schottky region 114 are: 1E15cm -3 ～5E17cm -3 。
In one embodiment of the present application, the trench power MOSFET device integrating the schottky diode further comprises: a silicon carbide substrate 101 and a drain electrode 112.
As shown in fig. 1, the top of silicon carbide substrate 101 is in contact with the bottom of epitaxial layer 102; wherein the silicon carbide substrate 101 is an N-type region; the drain electrode 112 covers the bottom of the silicon carbide substrate 101; the ion doping concentration in the silicon carbide substrate 101 is greater than the ion doping concentration in the epitaxial layer 102.
In one embodiment of the present application, the silicon carbide substrate 101 has an ion doping concentration range of: 1E18cm -3 ～1E20 cm -3 The epitaxial layer 102 has an ion doping concentration in the range of: 1E14cm -3 ～5E17 cm -3 。
In one embodiment of the present application, the MOSFET structure on top of the epitaxial layer further comprises: ohmic contact metal 109 and schottky contact metal 110.
As shown in fig. 1, an ohmic contact metal 109 covers the top of the second highly doped P-type region 105 and a portion of the source region 104, and forms an ohmic contact with the second highly doped P-type region 105 and a portion of the source region 104 at the same time at the contact location, so as to suppress parasitic bipolar transistor effects inside the MOSFET device. The schottky contact metal 110 overlies the top of the schottky region 114 and forms a schottky contact at the contact location.
In one embodiment of the present application, the MOSFET structure on top of the epitaxial layer further comprises: the gate oxide 106 is insulated from the gate conductive polysilicon 107.
As shown in fig. 1, the insulating gate oxide layer 106 covers the inner wall of the trench 117; gate conductive polysilicon 107 fills trench 117. It will be appreciated that the gate conductive polysilicon 107 fills the trench 117 that has been covered with the gate insulation oxide 106, and that the top of the trench is level with the mesa height of the epitaxial layer 102 after filling.
In one embodiment of the present application, the MOSFET structure on top of the epitaxial layer further comprises: insulating dielectric layer 108.
As shown in fig. 1, an insulating dielectric layer 108 covers the top of the filled trench 117 and the top of a portion of the source region 104 of each cell 10.
In one embodiment of the present application, the trench power MOSFET device integrating the schottky diode further comprises: a source electrode 111.
As shown in fig. 1, a source electrode 111 is covered on the ohmic contact metal 109 and the schottky contact metal 110; an insulating dielectric layer 108 separates the gate conductive polysilicon 107 from the source metal 104.
Fig. 4 is a schematic diagram of a circular cell structure according to an embodiment of the present application. As shown in fig. 4, the boundary of the trench 117, the source region 104, the second highly doped P-type region 105 and the schottky region 114 are all concentric ring structures. The cross-sectional view corresponding to the dashed line AA' in fig. 4 is a cross-sectional view of an active region of a trench type power MOSFET device integrated with a schottky diode shown in fig. 1; the cross-sectional view corresponding to the dashed line BB' in FIG. 4 is a cross-sectional view of the active region of another trench-type power MOSFET device integrated with a Schottky diode shown in FIG. 3.
Fig. 5 is a schematic diagram of a regular quadrilateral cell structure according to an embodiment of the present application. As shown in fig. 5, the boundary of the trench 117, the source region 104, the second highly doped P-type region 105 and the schottky region 114 are all concentric regular tetragonal structures. In addition, the regular tetragonal cells shown in fig. 5 are arranged in a staggered manner in two adjacent rows or two adjacent columns. The cross-sectional view corresponding to the dashed line AA' in fig. 5 is a cross-sectional view of an active region of a trench type power MOSFET device integrated with a schottky diode shown in fig. 1; the cross-sectional view corresponding to the dashed line BB' in FIG. 5 is a cross-sectional view of the active region of another trench-type power MOSFET device integrated with a Schottky diode shown in FIG. 3.
Fig. 6 is a schematic diagram of a regular quadrilateral cell structure according to an embodiment of the present application. As shown in fig. 6, the boundary of the trench 117, the source region 104, the second highly doped P-type region 105 and the schottky region 114 are all concentric regular tetragonal structures. The regular tetragonal cells shown in fig. 6 are arranged in such a manner that the regular tetragonal cells of each row and each column are aligned. The cross-sectional view corresponding to the dashed line AA' in fig. 6 is a cross-sectional view of an active region of a trench type power MOSFET device integrated with a schottky diode shown in fig. 1;
the cross-sectional view corresponding to the dashed line BB' in FIG. 5 is a cross-sectional view of the active region of another trench-type power MOSFET device integrated with a Schottky diode shown in FIG. 3.
As a possible implementation manner, the method for manufacturing the trench type power MOSFET device integrated with the schottky diode of the present application is shown in fig. 7 to 20, and mainly includes the following steps:
1. as shown in fig. 7, a substrate 101 and an epitaxial layer 102 are formed;
2. as shown in fig. 8 or fig. 20, a schottky region 114 of the enhanced first conductivity type is formed on the surface of the epitaxial layer 102;
3. as shown in fig. 9, a plurality of well regions 103 of the second conductivity type are formed on the surface of the epitaxial layer 102; wherein the first conductivity type is N type, and the second conductivity type is P type;
4. as shown in fig. 10, a plurality of highly doped source regions 104 of the first conductivity type are formed inside the well region 103 containing the second conductivity type;
5. as shown in fig. 11, a plurality of trench structures 117 are formed on the surface of the epitaxial layer 102;
6. as shown in fig. 12, a JFET region 113 of the enhanced first conductivity type is formed in the sidewall of trench 117;
7. as shown in fig. 13, a plurality of first highly doped P-type regions 118 are formed at the bottom of the trench 117, and a plurality of second highly doped P-type regions 105 are formed on the surface of the mesa;
8. as shown in fig. 14, an insulating gate oxide layer 106 is formed at the bottom and sidewalls of the trench 117;
9. as shown in fig. 15, gate conductive polysilicon 107 is formed inside trench 117, filling the trench, and having a height near the level of the epitaxial layer 102 mesa;
10. as shown in fig. 16, a plurality of insulating dielectric layers 108 are formed on the surface of the device;
11. as shown in fig. 17, an ohmic contact metal 109 is formed over the highly doped first conductivity type source region 104 and the second highly doped P-type region 105 of the device surface;
12. as shown in fig. 17, a schottky contact metal 110 is formed over the enhanced schottky region 114 of the device surface;
13. as shown in fig. 18, a source electrode 111 is formed on top of the device;
14. as shown in fig. 19, a drain electrode 112, which is also an ohmic contact metal, is formed on the back surface of the substrate 101.
Wherein the step of forming the substrate 101 includes using n+ type SiC as the substrate. The step of forming the epitaxial layer 102 includes forming an epitaxial layer made of N-type silicon carbide on the surface of the substrate. In an embodiment of the present application, as shown in fig. 8, the first step of forming a region 114 of the reinforced first type includes forming an epitaxial layer of higher N-doped silicon carbide on the surface of the chip. As shown in fig. 20, a second step of forming regions of the reinforced first type 114 includes depositing a mask layer 200, photolithography and etching the mask layer to form pattern transitions. The step of forming the region 114 of the enhanced first type includes ion implantation at the surface of the chip to achieve N-type impurity doping, which may be nitrogen or phosphorus, at specific locations on the surface of the epitaxial layer (regions where the mask layer is windowed). The step of forming the well region 103 of the second conductivity type comprises depositing a mask layer 201, photolithography and etching the mask layer to form a pattern transfer. The step of forming the well region 103 of the second conductivity type includes performing ion implantation on the surface of the chip, thereby implementing P-type impurity doping at a specific portion (a region where the mask layer is windowed) of the surface of the epitaxial layer, and the doping impurity type may be aluminum or boron. The step of forming the highly doped source region 104 of the first conductivity type includes depositing a mask layer 202, photolithography and etching the mask layer to form a pattern transfer. The step of forming the source region 104 of the highly doped first conductivity type includes performing ion implantation on the surface of the chip, thereby implementing N-type impurity doping at a specific portion (a region where the mask layer is windowed) of the surface of the epitaxial layer, and the doping impurity type may be nitrogen or phosphorus. The step of forming trench structure 117 includes depositing a mask layer 203, photolithography and etching the mask layer to form a pattern transfer. The step of forming the trench structure 117 includes etching on the surface of the chip, thereby forming the trench structure at a specific portion (a region where the mask layer opens) on the surface of the epitaxial layer. The step of forming the stiffening first type 113 region includes using the mask layer 203 to achieve stiffening N-type impurity doping, which may be nitrogen or phosphorous, at specific locations on the surface of the epitaxial layer (trench sidewalls). The step of forming the plurality of highly doped second conductivity type regions 105 and regions 118 includes again photolithography and etching the mask layer 203 to form a pattern transfer. The step of forming the plurality of highly doped second conductivity type regions 105 and 118 includes etching the surface of the chip to achieve P-type impurity doping at specific locations (windowed regions of the mask layer) on the surface of the epitaxial layer, the doping impurity type being aluminum or boron. The step of forming the gate oxide layer 106 includes forming an oxide by forming an oxide at the bottom and sidewalls of the trench. The step of forming gate conductive polysilicon 107 includes depositing polysilicon on top of the device. The step of forming the gate conductive polysilicon 107 includes photolithography, etching, and finally the polysilicon in the trench has a height that is similar to or slightly lower than the silicon carbide mesa. The step of forming insulating dielectric layer 108 includes dielectric layer growth, photolithography, and etching the dielectric layer to form a source contact window. The step of forming ohmic contact metal 109 and schottky contact metal 110 includes depositing metal on top of the epitaxial layer containing the dielectric layer. The step of forming the ohmic contact metal 109 and the schottky contact metal 110 includes annealing the metal to simultaneously form the ohmic contact and the schottky metal at an interface where the metal is in direct contact with the surface of the epitaxial layer. The step of forming ohmic contact metal 112 includes depositing metal on the back side of the substrate. The step of forming the ohmic contact metal 112 includes annealing the metal on the back side of the substrate to form an ohmic contact between the metal and the surface of the substrate. In one embodiment, when the doping concentration of the JFET region 113 of the enhanced first type conductivity and the schottky region 114 of the enhanced first type conductivity is the same as that of the epitaxial layer, no additional process steps are required for ion implantation or double layer epitaxy, and the manufacturing method steps are as follows:
1. forming a substrate 101;
2. forming an epitaxial layer 102;
3. forming a plurality of well regions 103 of the second conductivity type on the surface of the epitaxial layer 102;
4. forming a plurality of highly doped regions 104 of the first conductivity type inside the well region 103 containing the second conductivity type;
5. forming a plurality of trench structures 117 on a surface of the epitaxial layer 102;
6. forming a plurality of highly doped second conductivity type regions 118 at the bottom of the trench, and forming a plurality of highly doped second conductivity type regions 105 at the mesa surface;
7. forming an oxide layer 106 at the bottom and sidewalls of the trench;
8. forming gate polysilicon 107 inside the trench, filling the trench, and having a height near a level with the mesa;
9. forming a plurality of insulating dielectric layers 108 on the surface of the device;
10. forming an ohmic contact metal 109 over the highly doped first conductivity type region 104 and the highly doped second conductivity type region 105 of the device surface;
11. forming a schottky contact 110 over the enhanced region 114 of the device surface;
12. a source electrode 111 is formed on top of the device;
13. forming ohmic contact metal 112 on the back surface of the substrate;
the formation of the highly doped source region 104 of the first conductivity type may also be accomplished by a self-aligned process using the existing mask layer 201 to form the mask layer 202, which is etched to form the pattern transfer. The enhanced first type conductivity region 113 and the enhanced first type conductivity region 114 may be formed simultaneously by the same process or may be formed stepwise. The region 105 of the highly doped second conductivity type and the region 118 of the highly doped second conductivity type may be formed simultaneously by the same process or may be formed stepwise. The ohmic contact metal 109 and the schottky contact metal 110 may be formed simultaneously by the same process or may be formed in steps.
In addition, in the method for manufacturing the MOSFET device, the forming sequence of the well region 103, the source region 104, the second highly doped P-type region 105, the first highly doped P-type region 118, the JFET region 113, the schottky region 114, and the trench structure 117 may be adjusted according to the process requirement.
In one embodiment, the manufacturing mode sequence may be as follows:
1. forming a substrate 101;
2. forming an epitaxial layer 102;
3. forming a reinforced first conductivity type region 114 on a surface of the epitaxial layer 102;
4. forming a plurality of highly doped second conductivity type regions 105 on the mesa surface;
5. forming a plurality of well regions 103 of a second conductivity type different from the first conductivity type on the surface of the epitaxial layer 102;
6. forming a plurality of highly doped regions 104 of the first conductivity type inside the well region 103 containing the second conductivity type;
7. forming a plurality of trench structures 117 on the surface of the epitaxial layer;
8. forming a reinforced first conductivity type region 113 at a sidewall of the trench structure 117;
9. forming a plurality of highly doped second conductivity type regions 118 at the bottom of the trench;
10. forming an oxide layer 106 at the bottom and sidewalls of the trench;
11. forming gate polysilicon 107 inside the trench, filling the trench, and having a height near a level with the mesa;
12. forming a plurality of insulating dielectric layers 108 on the surface of the device;
13. forming an ohmic contact metal 109 over the highly doped first conductivity type region 104 and the highly doped second conductivity type region 105 of the device surface;
14. forming a schottky contact 110 over the enhanced region 114 of the device surface;
15. a source electrode 111 is formed on top of the device;
16. ohmic contact metal 112 is formed on the back side of the substrate.
In another embodiment, the manufacturing method sequence may also be as follows:
1. forming a substrate 101;
2. forming an epitaxial layer 102;
3. forming a plurality of highly doped second conductivity type regions 105 on the mesa surface;
4. forming a plurality of well regions 103 of the second conductivity type on the surface of the epitaxial layer 102;
5. forming a plurality of highly doped regions 104 of the first conductivity type inside the well region 103 containing the second conductivity type;
6. forming a reinforced first conductivity type region 114 on a surface of the epitaxial layer 102;
7. forming a plurality of trench structures 117 on a surface of the epitaxial layer 102;
8. forming a reinforced first conductivity type region 113 at a sidewall of the trench structure 117;
9. forming a plurality of highly doped second conductivity type regions 118 at the bottom of the trench;
10. forming an oxide layer 106 at the bottom and sidewalls of the trench;
11. forming gate polysilicon 107 inside the trench, filling the trench, and having a height near a level with the mesa;
12. forming a plurality of insulating dielectric layers 108 on the surface of the device;
13. forming an ohmic contact metal 109 over the highly doped first conductivity type region 104 and the highly doped second conductivity type region 105 of the device surface;
14. forming a schottky contact 110 over the enhanced region 114 of the device surface;
15. a source electrode 111 is formed on top of the device;
16. ohmic contact metal 112 is formed on the back side of the substrate.
In another embodiment, the manufacturing method sequence may also be as follows:
1. forming a substrate 101;
2. forming an epitaxial layer 102;
3. forming a plurality of trench structures 117 on a surface of the epitaxial layer 102;
4. forming a reinforced first conductivity type region 113 at a sidewall of the trench structure 117;
5. forming a plurality of highly doped P-type regions 118 of the second conductivity type at the bottom of the trench;
6. forming a reinforced first conductivity type region 114 on a surface of the epitaxial layer 102;
7. forming a plurality of highly doped second conductivity type regions 105 on the mesa surface;
8. forming a plurality of well regions 103 of the second conductivity type on the surface of the epitaxial layer 102;
9. forming a plurality of highly doped regions 104 of the first conductivity type inside the well region 103 containing the second conductivity type;
10. forming an oxide layer 106 at the bottom and sidewalls of the trench;
11. forming gate polysilicon 107 inside the trench, filling the trench, and having a height near a level with the mesa;
12. forming a plurality of insulating dielectric layers 108 on the surface of the device;
13. forming an ohmic contact metal 109 over the highly doped first conductivity type region 104 and the highly doped second conductivity type region 105 of the device surface;
14. forming a schottky contact 110 over the enhanced region 114 of the device surface;
15. a source electrode 111 is formed on top of the device;
16. ohmic contact metal 112 is formed on the back side of the substrate.
The trench type power MOSFET device integrating the Schottky diode provided by the embodiment of the application has a polygonal or circular cell design, and the trench design is introduced, so that the proportion of the Schottky structure and the MOSFET structure occupying the active area of the device can be balanced, the higher channel width, the total area of the JFET region and the total Schottky conduction area are realized, the MOSFET structure and the Schottky structure have lower conduction loss, and the comprehensive electrical performance of the device is improved.
The embodiments of the present application are described in a progressive manner, and the same and similar parts of the embodiments are all referred to each other, and each embodiment is mainly described in the differences from the other embodiments. In particular, for the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments in part.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and variations of the present application will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the application are to be included in the scope of the claims of the present application.
Claims (10)
1. A schottky diode integrated trench power MOSFET device, said device comprising:
the epitaxial layer and the MOSFET structure are positioned on the top of the epitaxial layer; the epitaxial layer is an N-type region;
the MOSFET structure comprises: a plurality of cells with the same shape and structure, a first highly doped P-type region and a groove;
each cell comprises a well region, a source region, a second highly doped P-type region, a Schottky region and a JFET region; wherein: the well region is a P-type region, and the source region is an N-type region;
the Schottky region is positioned in the central region of the cell, the well region and the second highly doped P-type region encircle the Schottky region, and the source region encircles the second highly doped P-type region;
the well region is positioned on the top surface of the epitaxial layer and forms a first PN junction with the epitaxial layer;
the source electrode region and the second highly doped P-type region are both positioned on the surface of one side, away from the epitaxial layer, of the well region, and the well region and the source electrode region form a second PN junction;
the grooves are positioned among cells, the cross sections of the grooves among the cells are U-shaped, and the corners at the bottom of the grooves are fillets; the first highly doped P-type region wraps the bottom of the groove;
the first highly doped P-type region and the epitaxial layer form a third PN junction;
and a Junction Field Effect Transistor (JFET) region is formed between the well region and the adjacent first highly doped P-type region.
2. The schottky diode integrated trench power MOSFET device of claim 1 wherein said MOSFET structure further comprises: ohmic contact metal, schottky contact metal;
the ohmic contact metal covers the top of the second highly doped P-type region and part of the source electrode region, and forms ohmic contact with the second highly doped P-type region and part of the source electrode region at the contact position at the same time so as to inhibit parasitic bipolar transistor effect in the MOSFET device;
the schottky contact metal covers the top of the schottky region and forms a schottky contact at the contact location.
3. The schottky diode integrated trench power MOSFET device of claim 1 wherein said MOSFET structure further comprises: insulating the gate oxide layer from the gate conductive polysilicon;
the insulating gate oxide layer covers the inner wall of the groove;
the gate conductive polysilicon fills the trench.
4. The schottky diode integrated trench power MOSFET device of claim 3 wherein said MOSFET structure further comprises: an insulating dielectric layer;
and the insulating medium layer covers the top of the filled groove and the top of part of the source electrode area of each cell.
5. The schottky diode integrated trench power MOSFET device of claim 4, further comprising: a source electrode;
the source electrode is covered on the ohmic contact metal and the Schottky contact metal;
the insulating dielectric layer separates the gate conductive polysilicon from the source metal.
6. The schottky diode integrated trench power MOSFET device of claim 1 further comprising: a silicon carbide substrate, a drain electrode;
the top of the silicon carbide substrate is contacted with the bottom of the epitaxial layer; wherein the silicon carbide substrate is an N-type region;
the drain electrode covers the bottom of the silicon carbide substrate.
7. The schottky diode-integrated trench power MOSFET device of claim 6 wherein,
the ion doping concentration in the silicon carbide substrate is greater than the ion doping concentration in the epitaxial layer;
and the ion doping concentration of the JFET region and the Schottky region is greater than or equal to that of the epitaxial layer.
8. The schottky diode integrated trench power MOSFET device of claim 1 wherein,
the value range of the width of the JFET region and the value range of the width of the Schottky region are both in the same preset interval; wherein the preset interval is [ 0.8-5 μm ].
9. The schottky diode integrated trench power MOSFET device of claim 1 wherein said cells are circular or polygonal in shape.
10. The manufacturing method of the trench type power MOSFET device integrating the Schottky diode is characterized by comprising the following steps of:
s1, forming a silicon carbide substrate, and forming an epitaxial layer on one surface of the silicon carbide substrate;
s2, forming a reinforced Schottky region of the first conductivity type on the surface of the epitaxial layer;
s3, forming a plurality of well regions of the second conductivity type on the surface of the epitaxial layer; wherein the first conductivity type is N type, and the second conductivity type is P type;
s4, forming a plurality of highly doped source regions of the first conductivity type inside the well region containing the second conductivity type;
s5, forming a plurality of groove structures on the surface of the epitaxial layer;
s6, forming a reinforced JFET region of a first conductivity type on the side wall of the groove;
s7, forming a plurality of first highly doped P-type regions at the bottom of the groove, and forming a plurality of second highly doped P-type regions on the surface of the platform;
s8, forming an insulating gate oxide layer at the bottom and the side wall of the groove;
s9, forming grid conductive polysilicon in the groove, filling the groove, and enabling the height of the grid conductive polysilicon to be close to the position flush with the epitaxial layer platform;
s10, forming a plurality of insulating medium layers on the surface of the device;
s11, forming ohmic contact metal above a source region of the high doping first conductivity type and a second high doping P-type region on the surface of the device;
s12, forming a Schottky contact metal above the reinforced Schottky region of the surface of the device;
s13, forming a source electrode at the top of the device;
s14, forming a drain electrode on the other surface of the silicon carbide substrate.
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