CN116597883A - Device and method for improving flash memory scratch resistance - Google Patents

Device and method for improving flash memory scratch resistance Download PDF

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Publication number
CN116597883A
CN116597883A CN202310637317.5A CN202310637317A CN116597883A CN 116597883 A CN116597883 A CN 116597883A CN 202310637317 A CN202310637317 A CN 202310637317A CN 116597883 A CN116597883 A CN 116597883A
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China
Prior art keywords
word line
flash memory
gate
trimming
generating circuit
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CN202310637317.5A
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Chinese (zh)
Inventor
杨光军
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Priority to CN202310637317.5A priority Critical patent/CN116597883A/en
Publication of CN116597883A publication Critical patent/CN116597883A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The invention discloses a device for improving the scrubbing resistance of a flash memory, wherein storage units are all separated grid floating gate devices, a second grid structure formed by overlapping a grid medium layer and a grid is positioned between first grid structures with floating gates, and the second grid structure is formed by overlapping a grid medium layer and a grid. The device for improving the flash memory scratch resistance comprises: the memory device comprises a word line programming voltage generating circuit, a memory area, a trimming signal generating circuit and a control device. Control means for realizing: reading the cycle number during programming; the trimming signal generating circuit forms a trimming signal according to the cycle times; the word line programming voltage generating circuit outputs a word line programming voltage according to the trimming signal, and programs the word line by using the word line programming voltage, and the word line programming voltage is larger as the number of cycles is larger. The invention also discloses a method for improving the scratch resistance of the flash memory. The invention can compensate the influence of erasing times on programming depth and can improve the erasing resistance.

Description

Device and method for improving flash memory scratch resistance
Technical Field
The present invention relates to the field of semiconductor integrated circuits, and more particularly, to a device for improving flash (endurance) endurance. The invention also relates to a method for improving the scratch resistance of the flash memory.
Background
FIG. 1 is a schematic cross-sectional view of a memory cell of a conventional flash memory, wherein the flash memory shown in FIG. 1 is a NORD type flash memory; the existing flash memory comprises a plurality of memory cells (cells) 101, wherein an array unit is formed by the plurality of memory cells 101, and an array structure of the flash memory is formed by arranging the plurality of array units. Each of the memory cells 101 employs a split gate floating gate device.
As shown in fig. 1, the split gate floating gate device includes: a first source drain region 205a and a second source drain region 206 that are symmetrical, a plurality of separate first gate structures with floating gates 104 between the first source drain region 205a and the second source drain region 205b, a second gate structure 103 between the first gate structures; the first gate structure has a control gate 105 located on top of the floating gate 104.
The split gate floating gate device is a dual split gate floating gate device, and the number of first gate structures is two, indicated by reference numerals 102a and 102b, respectively.
The split gate floating gate device is an N-type device, and the first source drain region 205a and the second source drain region 205b are both composed of n+ regions.
A P-doped channel region is located between the first source drain region 205a and the second source drain region 205b and is covered by each of the first gate structure and the second gate structure 103. The first source drain region 205a and the second source drain region 205b are both formed on the P-type semiconductor substrate 201 and self-aligned to the outer side surfaces of the corresponding two first gate structures, and the channel region is formed by the P-type semiconductor substrate 201 between the first source drain region 205a and the second source drain region 205b or further formed by doping on the P-type semiconductor substrate 201.
The second source drain region 205b of the memory cell 101 is connected to a second source drain electrode, which is connected to the bit line BL1.
The first source drain region 205a of the memory cell 101 is connected to a first source drain electrode, which is connected to a bit line BL0.
Each of the first gate structures is formed by stacking a tunneling dielectric layer 202, the floating gate 104, a control gate dielectric layer 203, and the control gate 105.
Each of the second gate structures 103 is formed by overlapping a word line gate dielectric layer 204 and a word line gate 106.
The control gates 105 are connected to corresponding control gate lines, and the word line gate 106 is connected to the word line WL. In fig. 1, the memory cell 101 includes two first gate structures, so the control gate lines also include two control gate lines, respectively denoted by CG0 and CG1, the control gate 105 of the first gate structure 102a is connected to the control gate line CG0, and the control gate 105 of the first gate structure 102b is connected to the control gate line CG1.
In programming (Program) the selected memory bit of the memory cell 101, taking the memory bit 'a' corresponding to the floating gate 104 in the first gate structure 102a of fig. 1 as the selected memory bit, in some implementations, the applied voltages are as shown in table one:
list one
CG0(V) WL(V) CG1(V) BL0(V) BL1
9 1.5 5 4.5 Idp
As shown in Table one, the voltages applied during programming of memory bit 'a' include:
the control gate line CG1 is connected to 5V, and is used for opening, that is, conducting, a region section of the channel region controlled by the first gate structure 102 b;
the word line WL is connected to 1.5V, and is used for opening the region segment of the channel region controlled by the second gate structure 103;
bit line BL1 is coupled to programming current Idp.
The control gate line CG0 is connected to a high voltage of 9V, and the bit line BL0 is connected to a high voltage of 4.5V, so that after the programming current reaches the bottom of the first gate structure 102a through the area segments of the channel region controlled by the first gate structure 102b and the second gate structure 103, the source hot electron injection programming can be realized because the control gate line CG0 and the bit line BL1 are both high voltages.
The word line program voltage Vwlp, which is the voltage to which the word line WL is connected, is a fixed voltage, such as 1.5V as exemplified above. As shown in FIG. 2A, a curve 301 of the threshold voltage of the word line gate of a memory cell of a conventional flash memory with respect to the number of cycles is shown, vt represents the threshold voltage of the word line gate, tcyc represents the test time corresponding to the number of cycles; in practical use, the threshold voltage of the region of the channel region controlled by the second gate structure 103 of each memory cell, i.e., the word line gate threshold voltage Vt, will change as the number of cycles increases, because the amount of charge trapped by the defect in the second gate structure 103 will increase as the number of cycles increases, thereby increasing the word line gate threshold voltage Vt, so curve 301 is a curve that continuously increases with Tcyc, indicating a deeper and deeper programming depth (Program deep & deep).
With the word line programming voltage Vwlp fixed, the word line gate threshold voltage Vt increases, the programming depth of the memory cell increases because, as an example, the memory bit 'a' is programmed:
the voltage on the source side of the region of the channel region controlled by the second gate structure 103 is the word line programming voltage Vwlp minus the word line gate threshold voltage Vt, and after the word line gate threshold voltage Vt increases, it is obvious that the voltage on the source side of the region of the channel region controlled by the second gate structure 103 also decreases, which increases the voltage difference between the source side voltages of the bit line BL0 and the region of the channel region controlled by the second gate structure 103, i.e., the source-drain voltages increase, the voltage settings of CG0 and BL0 operate in the linear region, so that the source-drain voltage increases, the source-drain current increases, the source hot electron injection efficiency increases, the storage electrons injected into the storage bit 'a' by the source hot electron injection effect increases, and the programming depth of the storage bit 'a' increases. As shown in fig. 2B, which is a graph 302 of the read current of the memory cell of the conventional flash memory according to the cycle number, ir10 represents the read current after programming the memory bit 'a' in fig. 1 and programming another bit, and Ir10 is continuously decreased with the increase of Tcyc, which means that Ir10 sigma is larger and larger.
Disclosure of Invention
The invention aims to provide a device for improving the scratch resistance of a flash memory, which can compensate the influence of erasing times on programming depth, thereby improving the scratch resistance of the flash memory. Therefore, the invention also provides a method for improving the scratch resistance of the flash memory.
In order to solve the technical problems, in the device for improving the scratch resistance of the flash memory provided by the invention, the flash memory comprises a plurality of storage units; each of the memory cells employs a split gate floating gate device.
The split gate floating gate device includes: the first source drain region and the second source drain region are symmetrically arranged, a plurality of separated first grid structures with floating gates are arranged between the first source drain region and the second source drain region, and the second grid structures are arranged between the first grid structures; the first grid structure is provided with a control grid positioned on the top of the floating gate.
A channel region is located between the first source drain region and the second source drain region and is covered by each of the first gate structure and the second gate structure, each of the first gate structure and the second gate structure controlling a region segment of the covered channel region, respectively.
The second grid structure is formed by overlapping a word grid medium layer and a word grid; as the number of cycles increases, charge may accumulate in the word line gate dielectric layer and increase the word line gate threshold voltage of the region of the channel region covered by the second gate structure.
The device for improving the flash memory scratch resistance comprises:
and the input end of the word line programming voltage generating circuit is connected with the trimming signal, and the output end of the word line programming voltage generating circuit outputs the word line programming voltage.
And the storage area is used for storing the cycle times of the storage unit.
And the trimming signal generating circuit is used for forming the trimming signal related to the cycle times according to the cycle times of the storage unit.
Control means for realizing:
the number of loops is read while programming the selected memory cell.
The trimming signal generating circuit forms the trimming signal according to the number of cycles.
The word line programming voltage generating circuit outputs the word line programming voltage according to the trimming signal, programming is performed by adopting the word line programming voltage, and the word line programming voltage is larger as the word line threshold voltage is larger as the cycle number is larger, so that the programming influence of the increase of the word line threshold voltage on the memory cell is eliminated.
A further improvement is that the control device is also used for realizing:
and updating the circulation times in the storage area.
A further improvement is that the storage area is implemented with additional words in a sector of the flash memory.
Further, the trimming signal generating circuit includes:
a multiplexer having n input terminals and 1 output terminal, the output terminal of the multiplexer outputting the trimming signal; n is an integer greater than 1.
n trimming code units, the output end of each trimming code unit is connected to one input end of the multiplexer.
And the control signal generating circuit is used for decomposing the cycle times into n control signals, and each control signal corresponds to one interval of the cycle times.
Each of the control signals is connected to one input terminal of one of the trim code units and sets an output signal of the trim code unit by the control signal.
The multiplexer also selects one of the output signals of the n trim code units as the trim signal according to the control signal.
In a further improvement, the control device updates the cycle number in the storage area by controlling erasure including:
the number of loops in the additional word is read.
And erasing the sector.
And adding 1 to the cycle number and writing the added word.
A further improvement is that the control signal generating circuit is realized by adopting the control device; under the control device, the programming includes:
reading the cycle times;
generating n control signals according to the cycle times; n control signals are transmitted to the trimming signal generating circuit, the trimming signal generating circuit outputs the trimming signals according to the n control signals, and the word line programming voltage generating circuit outputs the word line programming voltages according to the trimming signals;
programming is performed using the word line programming voltage.
A further improvement is that in the programming, the word line programming voltage is used to effect programming of a word.
The separation gate floating gate device is a double separation gate floating gate device, and the number of the first gate structures is two.
In order to solve the technical problems, in the method for improving the scratch resistance of the flash memory provided by the invention, the flash memory comprises a plurality of storage units; each of the memory cells employs a split gate floating gate device.
The split gate floating gate device includes: the first source drain region and the second source drain region are symmetrically arranged, a plurality of separated first grid structures with floating gates are arranged between the first source drain region and the second source drain region, and the second grid structures are arranged between the first grid structures; the first grid structure is provided with a control grid positioned on the top of the floating gate.
A channel region is located between the first source drain region and the second source drain region and is covered by each of the first gate structure and the second gate structure, each of the first gate structure and the second gate structure controlling a region segment of the covered channel region, respectively.
The second grid structure is formed by overlapping a word grid medium layer and a word grid; as the number of cycles increases, charge may accumulate in the word line gate dielectric layer and increase the word line gate threshold voltage of the region of the channel region covered by the second gate structure.
The method for improving the scratch resistance of the flash memory comprises the following steps:
the word line programming voltage generating circuit is arranged, the input end of the word line programming voltage generating circuit is connected with the trimming signal, and the output end of the word line programming voltage generating circuit outputs the word line programming voltage.
And setting a storage area for storing the cycle times of the storage unit.
A trimming signal generating circuit is provided for forming the trimming signal in association with the number of cycles of the memory cell based on the number of cycles.
When programming the selected memory cell, the step of programming is set to:
and reading the cycle times of the storage unit.
And forming the trimming signal according to the cycle times, and outputting the word line programming voltage according to the trimming signal.
The word line programming voltage is used for programming, and the word line programming voltage is larger as the number of loops is larger, so that the influence of the increase of the word line threshold voltage on the programming of the memory cell is eliminated.
In a further improvement, the method for improving the endurance of the flash memory further comprises the following steps:
and updating the circulation times in the storage area.
A further improvement is that the storage area is implemented with additional words in a sector of the flash memory.
Further, the trimming signal generating circuit includes:
a multiplexer having n input terminals and 1 output terminal, the output terminal of the multiplexer outputting the trimming signal; n is an integer greater than 1.
n trimming code units, the output end of each trimming code unit is connected to one input end of the multiplexer.
And the control signal generating circuit is used for decomposing the cycle times into n control signals, and each control signal corresponds to one interval of the cycle times.
Each of the control signals is connected to one input terminal of one of the trim code units and sets an output signal of the trim code unit by the control signal.
The multiplexer also selects one of the output signals of the n trim code units as the trim signal according to the control signal.
In a further improvement, the method for improving the flash memory endurance updates the cycle number in the storage area by controlling erasure, and the step of erasing includes:
the number of loops in the additional word is read.
And erasing the sector.
And adding 1 to the cycle number and writing the added word.
The control signal generating circuit is realized by a control device; under the control of the control device, the programming step includes:
reading the cycle times of the storage unit;
the control signal generating circuit generates n control signals according to the cycle times, the trimming signal generating circuit outputs the trimming signals according to the n control signals, and the word line programming voltage generating circuit outputs the word line programming voltages according to the trimming signals;
programming is performed using the word line programming voltage.
A further improvement is that in the programming step, programming of a word is achieved using the word line programming voltage.
The separation gate floating gate device is a double separation gate floating gate device, and the number of the first gate structures is two.
In a flash memory such as a NORD type flash memory, wherein a memory cell adopts a split gate floating gate device, the invention provides a device for improving the scratch resistance of the flash memory, the word line programming voltage can be adjusted according to the cycle number, namely the erasing cycle number, and the adjusted word line programming voltage can compensate the influence of the increase of the word line gate threshold voltage on programming when the cycle number is increased, thereby avoiding the increase of the programming depth along with the increase of the cycle number, and finally improving the scratch resistance of the flash memory.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
FIG. 1 is a schematic cross-sectional view of a memory cell of a conventional flash memory;
FIG. 2A is a graph showing the variation of word line gate threshold voltage with cycle number for a memory cell of a conventional flash memory;
FIG. 2B is a graph showing the read current of a memory cell of a conventional flash memory according to the number of cycles;
FIG. 3 is a schematic diagram illustrating an apparatus for improving endurance of a flash memory according to an embodiment of the present invention;
FIG. 4A is a schematic diagram of a memory area of a device for improving the endurance of a flash memory according to a preferred embodiment of the present invention;
FIG. 4B is a flow chart of an erase operation in the device for improving the endurance of the flash memory according to the preferred embodiment of the present invention;
FIG. 4C is a flow chart of programming in the apparatus for improving the endurance of the flash memory according to the preferred embodiment of the present invention;
FIG. 5 is a schematic diagram showing the structures of the trimming signal generating circuit and the word line programming voltage generating circuit in the device for improving the endurance of the flash memory according to the preferred embodiment of the present invention.
Detailed Description
FIG. 3 is a schematic diagram of an apparatus for improving endurance of a flash memory according to an embodiment of the present invention; in the device for improving the endurance of the flash memory according to the embodiment of the invention, the flash memory includes a plurality of memory cells 101, and the memory cells 101 of the flash memory are also shown in fig. 1, which is a memory cell 101 of a NORD type flash memory; each of the memory cells 101 employs a split gate floating gate 104 device.
As shown in fig. 1, the split gate floating gate device includes: a first source drain region 205a and a second source drain region 206 that are symmetrical, a plurality of separate first gate structures with floating gates 104 between the first source drain region 205a and the second source drain region 205b, a second gate structure 103 between the first gate structures; the first gate structure has a control gate 105 located on top of the floating gate 104.
A channel region is located between the first source drain region 205a and the second source drain region 205b and is covered by each of the first gate structure and the second gate structure 103, and each of the first gate structure and the second gate structure 103 controls a region segment of the covered channel region, respectively.
The second gate structure 103 is formed by overlapping a word line grating 106 medium layer 204 and a word line grating 106; as the number of cycles increases, charges accumulate in the dielectric layer 204 of the word line gate 106 and increase the word line gate threshold voltage Vt of the region of the channel region covered by the second gate structure 103, as shown in fig. 2A, which is also shown by curve 301.
In the embodiment of the present invention, the split gate floating gate device is a dual split gate floating gate device, and the number of the first gate structures is two, which are respectively denoted by reference numerals 102a and 102 b.
The split gate floating gate device is an N-type device, and the first source drain region 205a and the second source drain region 205b are both composed of n+ regions. The channel region is doped with P type. The first source drain region 205a and the second source drain region 205b are both formed on the P-type semiconductor substrate 201 and self-aligned to the outer side surfaces of the corresponding two first gate structures, and the channel region is formed by the P-type semiconductor substrate 201 between the first source drain region 205a and the second source drain region 205b or further formed by doping on the P-type semiconductor substrate 201. In other embodiments can also be: the split gate floating gate device is a P-type device, the first source drain region 205a and the second source drain region 205b are both composed of p+ regions, and the channel region is doped with N-type.
The second source drain region 205b of the memory cell 101 is connected to a second source drain electrode, which is connected to the bit line BL1.
The first source drain region 205a of the memory cell 101 is connected to a first source drain electrode, which is connected to a bit line BL0.
Each of the first gate structures is formed by stacking a tunneling dielectric layer 202, the floating gate 104, a control gate dielectric layer 203, and the control gate 105.
Each of the second gate structures 103 is formed by overlapping a word line gate dielectric layer 204 and a word line gate 106.
The control gates 105 are connected to corresponding control gate lines, and the word line gate 106 is connected to the word line WL. In fig. 1, the memory cell 101 includes two first gate structures, so the control gate lines also include two control gate lines, respectively denoted by CG0 and CG1, the control gate 105 of the first gate structure 102a is connected to the control gate line CG0, and the control gate 105 of the first gate structure 102b is connected to the control gate line CG1.
The device for improving the flash memory scratch resistance comprises:
the word line program voltage Vwlp generates the circuit 404, and the input terminal of the word line program voltage Vwlp generates the circuit 404 is connected to the trimming signal trim, and the output terminal outputs the word line program voltage Vwlp.
A storage area 401 for storing the number of cycles of the storage unit 101.
In some preferred embodiments, as shown in fig. 4A, a schematic structure of a storage area of the cycle number in the apparatus for improving the endurance of the flash memory according to the preferred embodiment of the present invention is shown, where the storage area 401 is implemented by an additional word 401a in a sector 405 of the flash memory, and in fig. 4A, the sector 405 is also denoted by a sector, and the additional word 401a is also denoted by extra world to store cycling info.
A trimming signal generating circuit 403 for forming the trimming signal trim related to the number of cycles of the memory unit 101 according to the number of cycles.
Control means 402 for implementing:
the number of loops, indicated in figure 3 by Cycling, is read when programming the selected memory cell 101.
The trimming signal generation circuit 403 forms the trimming signal trim according to the number of cycles.
The word line program voltage Vwlp generating circuit 404 outputs the word line program voltage Vwlp according to the trimming signal trim, and programs with the word line program voltage Vwlp, the word line program voltage Vwlp is larger as the number of loops is larger, so as to eliminate the program effect of the increase of the word line program voltage Vwlp on the memory cell 101.
In the embodiment of the present invention, the control device 402 is further configured to implement: the number of loops in the storage area 401 is updated. In some preferred embodiments, the control means 402 updates the number of loops in the storage area 401 by controlling the erase implementation. FIG. 4B is a flow chart of an erase operation in the device for improving the endurance of the flash memory according to the preferred embodiment of the present invention; the erasing includes:
step S101, receiving an erasure command, and starting erasure. In FIG. 4B, the Erase command is also indicated by the Erase CMD.
Step S102, reads the number of loops in the additional word 401a, i.e. Read cycling info shown in fig. 4B.
Step S103, erasing the sector 405, namely the Erase sector shown in fig. 4B.
Step S104, writing the cycle number added with 1 into the additional word 401a, namely, the cycle+1 shown in FIG. 4B; write extra word.
As shown in fig. 5, the trimming signal generating circuit 403 includes:
a multiplexer 407 having n input terminals and 1 output terminal, the output terminal of the multiplexer 407 outputting the trimming signal trim; n is an integer greater than 1. In fig. 5, the multiplexer 407 is also represented by a MUX.
n trimming code units 406, the output of each of which is connected to one input of the multiplexer 407. In fig. 5, the trim code unit 406 is also represented by a trim code with a number.
And the control signal generating circuit is used for decomposing the cycle times into n control signals, and each control signal corresponds to one interval of the cycle times.
Each of the control signals is connected to one input terminal of one of the trim code units 406 and sets an output signal of the trim code unit 406 by the control signal.
The multiplexer 407 also selects one out of the output signals of the n trim code units 406 as the trim signal trim according to the control signal.
In some preferred embodiments, the control signal generating circuit is implemented by the control device 402, and under the control device 402, as shown in fig. 4C, a flow chart of programming in the apparatus for improving the endurance of the flash memory according to the preferred embodiment of the present invention is shown; the programming includes:
step S201, receiving a programming command, and starting programming. In FIG. 4C, the Program command is also represented by a Program CMD.
Step S202, the number of loops is read, i.e. Read cycling info shown in fig. 4C.
Step S203, generating n control signals according To the cycle number, namely To generate S1/…/Sn shown in FIG. 4C. S1, S2 to Sn represent numbers of the control signals, and each control signal corresponds to one section of the number of cycles, and each control signal is obtained by dividing the number of cycles into a plurality of steps (divide cycling count into several steps).
The trimming signal generation circuit 403 outputs the trimming signal trim according to n pieces of the control signals. As shown in fig. 5, the corresponding trim code unit 406 is selected according to S1, S2 to Sn, and then the multiplexer 407 regards the output of the selected trim code unit 406 as the trim signal trim.
The word line program voltage Vwlp generating circuit 404 outputs the word line program voltage Vwlp according to the trim signal trim.
Step S204, programming is performed using the word line programming voltage Vwlp. In the programming, the word line programming voltage Vwlp is used to Program one word, i.e., the word Program shown in fig. 4C.
In a flash memory such as a NORD type flash memory, in which a split gate floating gate 104 device is used as a memory cell 101, an embodiment of the present invention provides a device for improving the endurance of the flash memory, which can adjust a word line programming voltage Vwlp according to the number of cycles, that is, the number of erase cycles, and the adjusted word line programming voltage Vwlp can compensate for the influence of an increase in the word line gate threshold voltage Vt on programming when the number of cycles increases, thereby avoiding an increase in the programming depth with an increase in the number of cycles, and finally improving the endurance of the flash memory. Therefore, in the embodiment of the present invention, the variation curve of the word line gate threshold voltage Vt is the same as that of fig. 2A, but Ir10 will not decrease with increasing Tcye after programming in the embodiment of the present invention, so that the endurance of the device can be improved finally.
The method for improving the scratch resistance of the flash memory comprises the following steps:
in the method for improving the endurance of the flash memory according to the embodiment of the invention, the flash memory includes a plurality of memory cells 101, and the memory cells 101 of the flash memory are also shown in fig. 1, which is a memory cell 101 of a NORD type flash memory; each of the memory cells 101 employs a split gate floating gate 104 device.
As shown in fig. 1, the split gate floating gate device includes: a first source drain region 205a and a second source drain region 206 that are symmetrical, a plurality of separate first gate structures with floating gates 104 between the first source drain region 205a and the second source drain region 205b, a second gate structure 103 between the first gate structures; the first gate structure has a control gate 105 located on top of the floating gate 104.
A channel region is located between the first source drain region 205a and the second source drain region 205b and is covered by each of the first gate structure and the second gate structure 103, and each of the first gate structure and the second gate structure 103 controls a region segment of the covered channel region, respectively.
The second gate structure 103 is formed by overlapping a word line grating 106 medium layer 204 and a word line grating 106; as the number of cycles increases, charges accumulate in the dielectric layer 204 of the word line gate 106 and increase the word line gate threshold voltage Vt of the region of the channel region covered by the second gate structure 103, as shown in fig. 2A, which is also shown by curve 301.
In the method of the embodiment of the invention, the split gate floating gate device is a double split gate floating gate device, and the number of the first gate structures is two, which are respectively denoted by reference numerals 102a and 102 b.
The split gate floating gate device is an N-type device, and the first source drain region 205a and the second source drain region 205b are both composed of n+ regions. The channel region is doped with P type. The first source drain region 205a and the second source drain region 205b are both formed on the P-type semiconductor substrate 201 and self-aligned to the outer side surfaces of the corresponding two first gate structures, and the channel region is formed by the P-type semiconductor substrate 201 between the first source drain region 205a and the second source drain region 205b or further formed by doping on the P-type semiconductor substrate 201. Other embodiments of the method can also be: the split gate floating gate device is a P-type device, the first source drain region 205a and the second source drain region 205b are both composed of p+ regions, and the channel region is doped with N-type.
The second source drain region 205b of the memory cell 101 is connected to a second source drain electrode, which is connected to the bit line BL1.
The first source drain region 205a of the memory cell 101 is connected to a first source drain electrode, which is connected to a bit line BL0.
Each of the first gate structures is formed by stacking a tunneling dielectric layer 202, the floating gate 104, a control gate dielectric layer 203, and the control gate 105.
Each of the second gate structures 103 is formed by overlapping a word line gate dielectric layer 204 and a word line gate 106.
The control gates 105 are connected to corresponding control gate lines, and the word line gate 106 is connected to the word line WL. In fig. 1, the memory cell 101 includes two first gate structures, so the control gate lines also include two control gate lines, respectively denoted by CG0 and CG1, the control gate 105 of the first gate structure 102a is connected to the control gate line CG0, and the control gate 105 of the first gate structure 102b is connected to the control gate line CG1.
The method for improving the scratch resistance of the flash memory comprises the following steps:
the word line program voltage Vwlp generating circuit 404 is set, and an input terminal of the word line program voltage Vwlp generating circuit 404 is connected to the trimming signal trim, and an output terminal of the word line program voltage Vwlp is output.
A storage area 401 is provided for storing the number of cycles of the storage unit 101.
In some preferred embodiments, as shown in fig. 4A, a schematic structure of a storage area of the cycle number in the apparatus for improving the endurance of the flash memory according to the preferred embodiment of the present invention is shown, where the storage area 401 is implemented by an additional word 401a in a sector 405 of the flash memory, and in fig. 4A, the sector 405 is also denoted by a sector, and the additional word 401a is also denoted by extra world to store cycling info.
A trimming signal generating circuit 403 is provided for forming the trimming signal trim in relation to the number of cycles of the memory unit 101 according to the number of cycles.
When programming the selected memory cell, the step of programming is set to:
and reading the cycle times.
And forming the trimming signal trim according to the cycle times.
The word line program voltage Vwlp is output according to the trim signal trim.
The word line program voltage Vwlp is used to program, the greater the number of loops the greater the word line gate threshold voltage Vt, the greater the word line program voltage Vwlp to eliminate the programming effect of the increase in the word line gate threshold voltage Vt on the memory cell 101.
The method of the embodiment of the invention further comprises the steps of: the number of loops in the storage area 401 is updated. In some preferred embodiments, the control means 402 updates the number of loops in the storage area 401 by controlling the erase implementation. FIG. 4B is a flowchart illustrating an erase operation in a method for improving the endurance of a flash memory according to a preferred embodiment of the present invention; the erasing includes:
step S101, receiving an erasure command, and starting erasure. In FIG. 4B, the Erase command is also indicated by the Erase CMD.
Step S102, reads the number of loops in the additional word 401a, i.e. Read cycling info shown in fig. 4B.
Step S103, erasing the sector 405, namely the Erase sector shown in fig. 4B.
Step S104, writing the cycle number added with 1 into the additional word 401a, namely, the cycle+1 shown in FIG. 4B; write extra word.
As shown in fig. 5, the trimming signal generating circuit 403 includes:
a multiplexer 407 having n input terminals and 1 output terminal, the output terminal of the multiplexer 407 outputting the trimming signal trim; n is an integer greater than 1. In fig. 5, the multiplexer 407 is also represented by a MUX.
n trimming code units 406, the output of each of which is connected to one input of the multiplexer 407. In fig. 5, the trim code unit 406 is also represented by a trim code with a number.
And the control signal generating circuit is used for decomposing the cycle times into n control signals, and each control signal corresponds to one interval of the cycle times.
Each of the control signals is connected to one input terminal of one of the trim code units 406 and sets an output signal of the trim code unit 406 by the control signal.
The multiplexer 407 also selects one out of the output signals of the n trim code units 406 as the trim signal trim according to the control signal.
In some preferred embodiments, the control signal generating circuit is implemented by the control device 402, and under the control device 402, as shown in fig. 4C, a flowchart of programming in the apparatus for improving the endurance of the flash memory according to the preferred embodiment of the present invention is shown; the programming includes:
step S201, receiving a programming command, and starting programming. In FIG. 4C, the Program command is also represented by a Program CMD.
Step S202, the number of loops is read, i.e. Read cycling info shown in fig. 4C.
Step S203, generating n control signals according To the cycle number, namely To generate S1/…/Sn shown in FIG. 4C. S1, S2 to Sn represent numbers of the control signals, and each control signal corresponds to one section of the number of cycles, and each control signal is obtained by dividing the number of cycles into a plurality of steps (divide cycling count into several steps).
The trimming signal generation circuit 403 outputs the trimming signal trim according to n pieces of the control signals. As shown in fig. 5, the corresponding trim code unit 406 is selected according to S1, S2 to Sn, and then the multiplexer 407 regards the output of the selected trim code unit 406 as the trim signal trim.
The word line program voltage Vwlp generating circuit 404 outputs the word line program voltage Vwlp according to the trim signal trim.
Step S204, programming is performed using the word line programming voltage Vwlp. In the programming, the word line programming voltage Vwlp is used to Program one word, i.e., the word Program shown in fig. 4C.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.

Claims (16)

1. An apparatus for improving the endurance of a flash memory, wherein the flash memory comprises a plurality of memory cells; each storage unit adopts a split gate floating gate device;
the split gate floating gate device includes: the first source drain region and the second source drain region are symmetrically arranged, a plurality of separated first grid structures with floating gates are arranged between the first source drain region and the second source drain region, and the second grid structures are arranged between the first grid structures; the first grid structure is provided with a control grid positioned at the top of the floating gate;
a channel region is positioned between the first source drain region and the second source drain region and is covered by each of the first gate structure and the second gate structure, and each of the first gate structure and the second gate structure respectively controls a region section of the covered channel region;
the second grid structure is formed by overlapping a word grid medium layer and a word grid; as the number of cycles increases, charge will accumulate in the word line gate dielectric layer and increase the word line gate threshold voltage of the region segment of the channel region covered by the second gate structure;
the device for improving the flash memory scratch resistance comprises:
the word line programming voltage generating circuit is characterized in that the input end of the word line programming voltage generating circuit is connected with a trimming signal, and the output end of the word line programming voltage generating circuit outputs word line programming voltage;
a storage area for storing the cycle number of the storage unit;
a trimming signal generating circuit for forming the trimming signal related to the number of cycles of the memory unit according to the number of cycles;
control means for realizing:
reading the number of loops while programming the selected memory cell;
the trimming signal generating circuit forms the trimming signal according to the cycle number;
the word line programming voltage generating circuit outputs the word line programming voltage according to the trimming signal, programming is performed by adopting the word line programming voltage, and the word line programming voltage is larger as the word line threshold voltage is larger as the cycle number is larger, so that the programming influence of the increase of the word line threshold voltage on the memory cell is eliminated.
2. The apparatus for improving the endurance of a flash memory as claimed in claim 1, wherein: the control device is further configured to implement:
and updating the circulation times in the storage area.
3. The apparatus for improving the endurance of a flash memory as claimed in claim 2, wherein: the storage area is implemented with additional words in a sector of the flash memory.
4. The apparatus for improving the endurance of a flash memory as claimed in claim 3, wherein: the trimming signal generation circuit includes:
a multiplexer having n input terminals and 1 output terminal, the output terminal of the multiplexer outputting the trimming signal; n is an integer greater than 1;
n trimming code units, the output end of each trimming code unit is connected to one input end of the multiplexer;
a control signal generating circuit for decomposing the cycle number to form n control signals, each of the control signals corresponding to one section of the cycle number;
each control signal is connected to one input end of one trimming code unit and sets an output signal of the trimming code unit through the control signal;
the multiplexer also selects one of the output signals of the n trim code units as the trim signal according to the control signal.
5. The apparatus for improving the endurance of a flash memory as claimed in claim 3, wherein: the control device updates the cycle number in the storage area by controlling erasure including:
reading the number of loops in the additional word;
erasing the sector;
and adding 1 to the cycle number and writing the added word.
6. The apparatus for improving the endurance of a flash memory as claimed in claim 4, wherein: the control signal generating circuit is realized by adopting the control device; under the control device, the programming includes:
reading the cycle times;
generating n control signals according to the cycle times; n control signals are transmitted to the trimming signal generating circuit, the trimming signal generating circuit outputs the trimming signals according to the n control signals, and the word line programming voltage generating circuit outputs the word line programming voltages according to the trimming signals;
programming is performed using the word line programming voltage.
7. The apparatus for improving the endurance of a flash memory as recited in claim 6, wherein: in the programming, the word line programming voltage is employed to effect programming of a word.
8. The apparatus for improving the endurance of a flash memory as claimed in claim 1, wherein: the split gate floating gate device is a double split gate floating gate device, and the number of the first gate structures is two.
9. A method for improving the scratch resistance of a flash memory is characterized in that the flash memory comprises a plurality of storage units; each storage unit adopts a split gate floating gate device;
the split gate floating gate device includes: the first source drain region and the second source drain region are symmetrically arranged, a plurality of separated first grid structures with floating gates are arranged between the first source drain region and the second source drain region, and the second grid structures are arranged between the first grid structures; the first grid structure is provided with a control grid positioned at the top of the floating gate;
a channel region is positioned between the first source drain region and the second source drain region and is covered by each of the first gate structure and the second gate structure, and each of the first gate structure and the second gate structure respectively controls a region section of the covered channel region;
the second grid structure is formed by overlapping a word grid medium layer and a word grid; as the number of cycles increases, charge will accumulate in the word line gate dielectric layer and increase the word line gate threshold voltage of the region segment of the channel region covered by the second gate structure;
the method for improving the scratch resistance of the flash memory comprises the following steps:
setting a word line programming voltage generating circuit, wherein the input end of the word line programming voltage generating circuit is connected with a trimming signal, and the output end of the word line programming voltage generating circuit outputs word line programming voltage;
setting a storage area for storing the cycle times of the storage unit;
a trimming signal generating circuit is arranged for forming the trimming signal related to the cycle number according to the cycle number of the storage unit;
when programming the selected memory cell, the step of programming is set to:
reading the cycle times of the storage unit;
forming the trimming signal according to the cycle number, and outputting the word line programming voltage according to the trimming signal;
the word line programming voltage is used for programming, and the word line programming voltage is larger as the number of loops is larger, so that the influence of the increase of the word line threshold voltage on the programming of the memory cell is eliminated.
10. The method for improving the endurance of a flash memory as claimed in claim 9, wherein: the method for improving the scratch resistance of the flash memory further comprises the following steps:
and updating the circulation times in the storage area.
11. The method for improving the endurance of a flash memory as claimed in claim 10, wherein: the storage area is implemented with additional words in a sector of the flash memory.
12. The method for improving the endurance of a flash memory as claimed in claim 11, wherein: the trimming signal generation circuit includes:
a multiplexer having n input terminals and 1 output terminal, the output terminal of the multiplexer outputting the trimming signal; n is an integer greater than 1;
n trimming code units, the output end of each trimming code unit is connected to one input end of the multiplexer;
a control signal generating circuit for decomposing the cycle number to form n control signals, each of the control signals corresponding to one section of the cycle number;
each control signal is connected to one input end of one trimming code unit and sets an output signal of the trimming code unit through the control signal;
the multiplexer also selects one of the output signals of the n trim code units as the trim signal according to the control signal.
13. The method for improving the endurance of a flash memory as claimed in claim 11, wherein: the method for improving the scratch resistance of the flash memory updates the cycle times in the storage area by controlling erasure, and the step of erasure comprises the following steps:
reading the number of loops in the additional word;
erasing the sector;
and adding 1 to the cycle number and writing the added word.
14. The method for improving the endurance of a flash memory as claimed in claim 12, wherein: the control signal generating circuit is realized by a control device; under the control of the control device, the programming step includes:
reading the cycle times of the storage unit;
the control signal generating circuit generates n control signals according to the cycle times, the trimming signal generating circuit outputs the trimming signals according to the n control signals, and the word line programming voltage generating circuit outputs the word line programming voltages according to the trimming signals;
programming is performed using the word line programming voltage.
15. The method for improving the endurance of a flash memory as recited in claim 14, wherein: in the programming step, programming of one word is achieved using the word line programming voltage.
16. The method for improving the endurance of a flash memory as claimed in claim 9, wherein: the split gate floating gate device is a double split gate floating gate device, and the number of the first gate structures is two.
CN202310637317.5A 2023-05-31 2023-05-31 Device and method for improving flash memory scratch resistance Pending CN116597883A (en)

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