CN116597876A

CN116597876A - Bit line sense amplifier and bit line sensing method of semiconductor memory device

Info

Publication number: CN116597876A
Application number: CN202310095779.9A
Authority: CN
Inventors: 朴采焕; 权奇元
Original assignee: Sungkyunkwan University School Industry Cooperation; Samsung Electronics Co Ltd
Current assignee: Sungkyunkwan University School Industry Cooperation; Samsung Electronics Co Ltd
Priority date: 2022-02-11
Filing date: 2023-02-07
Publication date: 2023-08-15

Abstract

A bit line sense amplifier and a bit line sensing method of a semiconductor memory device are disclosed. The bit line sense amplifier includes: a first inverter configured to receive an input signal from a bit line via an input terminal and output a first signal to a first node; a second inverter configured to receive the first signal and output a second signal to a second node; a differential amplifier configured to receive an input signal as a positive input and a second signal as a negative input; a first switch configured to electrically connect the input terminal to a positive input of the differential amplifier; and a second switch configured to electrically connect the second node to the negative input of the differential amplifier.

Description

Bit line sense amplifier and bit line sensing method of semiconductor memory device

The present application is based on and claims priority of korean patent application No. 10-2022-0018468 filed on the korean intellectual property office on the 2 nd month 11 of 2022 and korean patent application No. 10-2022-0067700 filed on the korean intellectual property office on the 2 nd month 6 of 2022, the disclosures of which are incorporated herein by reference in their entirety.

Technical Field

The inventive concept relates to a bit line sense amplifier and a bit line sensing method of a semiconductor memory device, and more particularly, to a bit line sensing method using a bit line sense amplifier implemented as a single ended sense amplifier.

Background

Semiconductor memory devices tend to require high capacity and low power, high speed operation, depending on the needs of the user. As the capacity of the semiconductor memory device increases, a load mismatch phenomenon between a bit line connected to a bit line sense amplifier and a complementary bit line or a threshold voltage mismatch phenomenon between transistors in the bit line sense amplifier occurs according to a fine process. These phenomena may reduce the sensing efficiency (such as sensing margin and sensing speed) of the bit line sense amplifier.

Disclosure of Invention

According to the disclosed embodiments, a bit line sense amplifier configured as a single ended sense amplifier type is provided.

In addition, the disclosed bit line sense amplifier converts an input signal and continuously provides feedback for the converted input signal to provide a bit line sensing method for reducing capacitive loading of an offset compensation target signal.

According to an aspect of the inventive concept, a bit line sense amplifier includes: a first inverter configured to receive an input signal from a bit line via an input terminal and output a first signal to a first node; a second inverter configured to receive the first signal and output a second signal to a second node; a differential amplifier configured to receive an input signal as a positive input and a second signal as a negative input; a first switch configured to connect the input terminal to a positive input of the differential amplifier; and a second switch configured to connect the second node to the negative input of the differential amplifier, wherein the first inverter is connected to the second inverter through a first current source and a second current source, the first current source configured to regulate the first signal by providing a pull-up current to the first inverter, the second current source configured to regulate the first signal by providing a pull-down current to the second inverter.

According to another aspect of the inventive concept, a bit line sensing method performed by a bit line sense amplifier includes: inputting an input signal via an input terminal; outputting a first signal to a first node when an input signal is input to a first inverter; outputting the second signal to the second node through the second inverter after the first signal is input to the second inverter; inputting the input signal as a positive input and the second signal as a negative input to the differential amplifier; when the first switch is closed, inputting an input signal to the differential amplifier; and when the second switch is closed, inputting a second signal to the differential amplifier, wherein the first signal is regulated by a first current source providing a pull-up current and a second current source providing a pull-down current.

According to another aspect of the inventive concept, a bit line sense amplifier configured to perform a bit line sense operation includes: a first inverter configured to receive an input signal via an input terminal and output a first signal; a second inverter configured to receive the first signal and output a second signal to a second node; a differential amplifier configured to receive an input signal as a positive input and a second signal as a negative input; a first switch configured to connect the input terminal to a positive input of the differential amplifier; a second switch configured to connect the second node to the negative input of the differential amplifier; a first current source configured to regulate a first signal by providing a pull-up current; a second current source configured to regulate the first signal by providing a pull-down current; and a switching unit configured to connect the input terminal to the plurality of bit lines.

Drawings

The embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a diagram of a memory device according to an embodiment;

FIG. 2 is a circuit diagram of a bit line sense amplifier according to an embodiment;

FIG. 3 is a circuit diagram illustrating a case where a bit line sense amplifier performs an offset compensation operation according to an embodiment;

fig. 4 is a circuit diagram showing a case where a bit line sense amplifier performs a sense operation according to an embodiment;

FIG. 5 is a circuit diagram illustrating a case where a bit line sense amplifier performs a restore operation according to an embodiment;

FIG. 6 is a timing diagram illustrating a sense operation of a bit line sense amplifier according to an embodiment;

FIGS. 7-9 are circuit diagrams of bit line sense amplifiers according to other embodiments;

FIG. 10 is a flow chart of a bit line sensing method according to an embodiment;

FIGS. 11 and 12 are flowcharts of offset compensation operations according to embodiments;

fig. 13 and 14 show examples to which a memory device according to an embodiment is applied;

FIG. 15 is a block diagram illustrating an example of an applied bit line sense amplifier according to an embodiment;

FIG. 16 is a circuit diagram illustrating an example of an applied bit line sense amplifier according to an embodiment;

Fig. 17 is a block diagram of an example of implementation of a semiconductor memory device according to an embodiment;

fig. 18 is a block diagram of an example of a server system including a semiconductor memory device according to an embodiment; and

FIG. 19 is a block diagram of a computing system including a memory device according to an embodiment.

Detailed Description

The terminology used in the inventive concept is briefly described and the embodiments are described in detail.

FIG. 1 is a diagram of a memory device 100 according to an embodiment.

Referring to fig. 1, a memory device 100 may include a semiconductor-based memory device. For example, memory device 100 may include dynamic Random Access Memory (RAM) (DRAM) (such as Synchronous DRAM (SDRAM), double Data Rate (DDR) SDRAM (DDR SDRAM), low power double data rate SDRAM (PLDDR SDRAM), graphics DDR (GDDR), DDR3SDRAM, and DDR4 SDRAM), or resistive memory (such as Phase Change RAM (PCRAM), magnetic RAM (MRAM), and Resistive RAM (RRAM)).

The memory device 100 may output data via the data lines DQ in response to a command CMD, an address ADDR, and a control signal received from an external device (e.g., a memory controller). Memory device 100 may include a memory cell array 110, a command Decoder (DEC) 115, an address buffer 120, a ROW (ROW) decoder 130, a Column (COL) decoder 140, bit line sense amplifiers (S/A) 150, and data in/out (I/O) circuits 160.

The memory cell array 110 may include a plurality of memory cells arranged in a matrix form arranged in rows and columns. The memory cell array 110 may include a plurality of word lines and a plurality of bit lines BL respectively connected to the memory cells. A plurality of word lines may be connected to rows of memory cells, respectively, and a plurality of bit lines BL may be connected to columns of memory cells, respectively.

The command decoder 115 may generate a control signal corresponding to the command CMD by decoding a write enable signal/WE, a row address strobe signal/RAS, a column address strobe signal/CAS, a chip select signal/CS, etc., received from an external device (e.g., a memory controller). The commands CMD may include an activate command, a read command, a write command, a precharge command, and the like. The command decoder 115 may generate an activation signal ACTIVE based on the activation command.

Address buffer 120 may receive address ADDR from an external device (e.g., a memory controller). The address ADDR may include a row address RA for addressing a row of the memory cell array 110 and a column address CA for addressing a column of the memory cell array 110. The address buffer 120 may send the row address RA to the row decoder 130 and the column address CA to the column decoder 140.

The row decoder 130 may select any word line of the plurality of word lines connected to the memory cell array 110. The row decoder 130 may decode the row address RA received from the address buffer 120, select any word line corresponding to the row address RA, and activate the selected word line.

The column decoder 140 may select a specific bit line BL among the plurality of bit lines BL of the memory cell array 110. The column decoder 140 may decode the column address CA received from the address buffer 120, select a specific bit line BL corresponding to the column address CA, and activate the selected bit line BL.

The bit line sense amplifier 150 may be connected to a bit line BL of the memory cell array 110. The bit line sense amplifier 150 may sense a voltage change of a selected bit line BL among the plurality of bit lines BL and amplify and output the sensed voltage change. The data input/output circuit 160 may output data output based on the voltage variation sensed and amplified by the bit line sense amplifier 150 to the outside via the data line DQ.

The bit line sense amplifier 150 may receive switching signals Φ1 through Φ8 from the row decoder 130. The switching signals Φ1 through Φ8 may be supplied from the row decoder 130 corresponding to the activation signal ACTIVE received from the command decoder 115, and may be selectively activated when a word line driving voltage is applied to a word line corresponding to the row address RA.

The switching signals Φ1 through Φ8 can control a plurality of switches included in the bit line sense amplifier 150. When the switches are closed or opened by the switching signals Φ1 through Φ8, the bit line sense amplifier 150 can perform a precharge operation, an offset removal operation, a charge sharing operation, and a sensing and recovery operation. For convenience of description, the bit line sense amplifier 150 operated based on a switching operation by switching the switches of the signals Φ1 through Φ8 may be referred to as a switchable bit line sense amplifier S/a.

Hereinafter, the construction and operation of the bit line sense amplifier 150 are described in detail with reference to various embodiments.

Fig. 2 is a circuit diagram of a bit line sense amplifier 150 according to an embodiment.

Referring to fig. 2, the bit line sense amplifier 150 according to an embodiment may include a first inverter INV1, a second inverter INV2, a first current source 151, a second current source 152, and a differential amplifier 153. In addition, the bit line sense amplifier 150 according to an embodiment may further include a first switch SW1, a second switch SW2, and a third switch SW3.

The first inverter INV1 may receive an input signal IN from the bit line BL, convert the input signal IN, and output a first signal SG1. IN this case, the input signal IN may include a signal input from the bit line BL outside the bit line sense amplifier 150, and may include a signal having a large capacitive load. The first inverter INV1 may include a first transistor TR1 and a second transistor TR2.

The second inverter INV2 may receive the first signal SG1 from the first node ND1, convert the first signal SG1, and output the second signal SG2. The second inverter INV2 may include a third transistor TR3 and a fourth transistor TR4, and may perform an offset control operation of the differential amplifier 153 by outputting the second signal SG2. The second signal SG2 and the offset control operation are described in detail with reference to fig. 3.

The first current source 151 may adjust the intensity of the first signal SG1 by adjusting the current input from the first inverter INV 1. For example, the first current source 151 may include a pull-up current source, and the first current source 151 may adjust the first signal SG1 by adjusting the output of the first inverter INV1, the second signal SG2 may be adjusted as a result of adjusting the first signal SG1, and the bit line sense amplifier 150 may perform an offset compensation operation on the first signal SG1.

Similar to the first current source 151, the second current source 152 may regulate the first signal SG1. For example, the second current source 152 may include a pull-down current source, and the second current source 152 may adjust the intensity of the first signal SG1, the second signal SG2 may be adjusted as a result of adjusting the intensity of the first signal SG1, and the bit line sense amplifier 150 may perform an offset compensation operation on the first signal SG1.

The differential amplifier 153 may output the output signal OUT by using the input signal IN and the second signal SG2 as inputs. In this case, the output signal OUT may be used as a signal for controlling the operation of the second current source 152. For example, the output signal OUT may be used as a voltage control signal of the second current source 152, and the first signal SG1 may be controlled when a pull-down current control operation of the second current source 152 is controlled. As a result, the first signal SG1 may be controlled according to the feedback of the second signal SG2, and offset compensation of the first signal SG1 may be possible according to the feedback of the second signal SG 2.

The bit line sense amplifier 150 according to the inventive concept may include a first switch SW1, a second switch SW2 and a third switch SW3. In addition, the bit line sense amplifier 150 according to the inventive concept may receive a precharge control signal VEQ for performing a precharge operation and a restore operation. The first switch SW1 and the second switch SW2 may be closed when the offset compensation operation is performed, and the third switch SW3 may be closed when the bit line sense amplifier 150 performs the recovery operation. In addition, when all of the first switch SW1, the second switch SW2 and the third switch SW3 are turned off, a bit line sensing operation may be performed. A description is given in detail of an offset compensation operation, a bit line sensing operation, and a recovery operation of the bit line sense amplifier 150 according to the disclosed embodiment with reference to fig. 3 to 5.

Fig. 3 is a circuit diagram illustrating a case where the bit line sense amplifier 150 performs an offset compensation operation according to an embodiment.

Referring to fig. 3, when the first switch SW1 and the second switch SW2 of the bit line sense amplifier 150 according to an embodiment are closed, an offset compensation operation of the differential amplifier 153 may be performed. IN this case, when the bit line sense amplifier 150 performs an offset compensation operation, the input signal IN and the second signal SG2 may be used as inputs of the differential amplifier 153.

For example, the first switch SW1 and the second switch SW2 may be closed, and the input signal IN may be input as a positive input to the differential amplifier 153. In addition, the second signal SG2 may be input to the differential amplifier 153 as a negative input. The differential amplifier 153 may receive the input signal IN of the bit line BL and the second signal SG2 and generate an output signal OUT. In this case, the output signal OUT may be used as a voltage control signal of the second current source 152. When the output signal OUT is input to the second current source 152, the second current source 152 may generate a pull-down current for adjusting the first signal SG1 for an offset compensation operation of the differential amplifier 153. When the pull-down current is generated, the value of the first signal SG1 may be adjusted, and the adjusted first signal SG1 may be input to the second inverter INV2 again. In this case, when the amplitude of the first signal SG1 is smaller than a value required for offset compensation, the first current source 151 may adjust the first signal SG1 by generating a pull-up current. In other words, the bit line sense amplifier 150 according to the embodiment may continuously provide the first signal SG1 as feedback, generate a new second signal SG2, and finally perform an offset compensation operation of the first signal SG1.

Fig. 4 is a circuit diagram illustrating a case where the bit line sense amplifier 150 performs a sensing operation according to an embodiment.

Referring to fig. 4, according to an embodiment, when data of the bit line BL is sensed, the first, second and third switches SW1, SW2 and SW3 may be turned off. For example, when the magnitudes of the second signal SG2 and the input signal IN output to the second node ND2 are equal and the first switch SW1, the second switch SW2 and the third switch SW3 are turned off, an offset compensation operation for the first signal SG1 may not be performed at the first node ND1 and the bit line sense amplifier 150 may perform a charge sharing operation and a sensing operation on the bit line BL. In this case, the first and second current sources 151 and 152 may not generate a pull-up current and a pull-down current, respectively.

Fig. 5 is a circuit diagram illustrating a case where the bit line sense amplifier 150 performs a restore operation according to an embodiment.

Referring to fig. 5, when the third switch SW3 is closed, a restoration operation of the bit line sense amplifier 150 according to an embodiment may be performed. When the third switch SW3 is closed and the first and second switches SW1 and SW2 are opened, the input terminal NIP of the bit line sense amplifier 150 may be connected to the second node ND2 of the bit line sense amplifier 150. When the input terminal NIP of the bit line sense amplifier 150 is connected to the second node ND2 of the bit line sense amplifier 150, data can be restored in the memory cell.

Fig. 6 is a timing diagram illustrating a sensing operation of the bit line sense amplifier 150 according to an embodiment.

Referring to fig. 6, the bit line sense amplifier 150 according to the embodiment may perform a bit line sense operation after completing the processing of the first to fourth sections T1 to T4. According to an embodiment, the first interval T1 may represent a precharge interval, the second interval T2 may represent an offset compensation interval, the third interval T3 may represent a charge sharing interval, and the fourth interval T4 may represent a recovery interval. The third section T3 may include "a section in which the connection relationship between the first node ND1 of the first inverter INV1 and the second node ND2 of the second inverter INV2 in fig. 2 to 4 is changed" together with "a section in which the charge sharing operation is waited for" before the charge sharing section. In addition, the first to fourth sections T1 to T4 may be continuously repeated according to the operation of the bit line sense amplifier 150.

In the first interval T1, the precharge control signal VEQ supplied to the equalizer EQ may be activated, and the bit line BL may be precharged to a preset precharge voltage. The precharge control signal VEQ may be in, for example, a logic "high" state. In this case, the third switch SW3 may be in a closed state, and the first switch SW1 and the second switch SW2 may be in an open state. In addition, the voltage V1 output from the first transistor TR1 of the first inverter INV1 may be the same as the voltage V2 output from the second transistor TR 2. For example, the voltage V1 output from the first transistor TR1 of the first inverter INV1 and the voltage V2 output from the second transistor TR2 may be in a precharged level state. After the first interval T1, the precharge control signal VEQ may be deactivated, for example, in a logic "low" state.

IN the second interval T2, the input signal IN may be input to the first inverter INV1 while maintaining a constant state. In this case, the first and second switches SW1 and SW2 may be closed, and the first and second signals SG1 and SG2 may be output to the first and second nodes ND1 and ND2 of the first and second inverters INV1 and INV2, respectively. In this case, the voltage V1 output from the first transistor TR1 of the first inverter INV1 may be different from the voltage V2 output from the second transistor TR 2. For example, the voltage V1 output from the first transistor TR1 of the first inverter INV1 may be in a logic "high" state, and the voltage V2 output from the second transistor TR2 may be in a logic "low" state. In this case, the voltage V1 output from the first transistor TR1 may include an input of the first current source 151. In addition, the voltage V3 applied to the differential amplifier 153 may be in a logic "high" state. When the offset compensation operation of the first signal SG1 is performed, the input signal IN may be input to the differential amplifier 153 as a positive input, and the second signal SG2 may be input as a negative input. As a result, the differential amplifier 153 may output the output signal OUT according to a change of the second signal SG2, and the offset compensation operation for the first signal SG1 may be performed for the first signal SG1 by a feedback operation using the second signal SG 2.

IN the third interval T3, the input signal IN may be input to the first inverter INV1 while maintaining a constant state. In the third section T3, all of the first switch SW1, the second switch SW2 and the third switch SW3 may be turned off. In other words, all signals applied to the first switch SW1, the second switch SW2 and the third switch SW3 may be in a logic "low" state. In addition, the voltage V1 output from the first transistor TR1 of the first inverter INV1 may be different from the voltage V2 output from the second transistor TR 2. For example, the voltage V1 output from the first transistor TR1 of the first inverter INV1 may be in a logic "high" state, and the voltage V2 output from the second transistor TR2 may be in a logic "low" state. In addition, the voltage V3 applied to the differential amplifier 153 may be in a logic "low" state, and the output signal OUT of the differential amplifier 153 may be in a logic "low" state. When all of the first switch SW1, the second switch SW2 and the third switch SW3 are turned off, the input signal IN may transition to a charge sharing level IN a precharge state. When the input signal IN is converted into the charge sharing level, the first signal SG1 may have a level inverted by the first inverter INV1 (inverted IN), and as a result, the second signal SG2 may have a level inverted by the second inverter INV2 (inverted SG 1). In this case, a precharge voltage may be supplied to the power line of the bit line sense amplifier 150.

Next, in the fourth section T4, the third switch SW3 may be closed, and the first switch SW1 and the second switch SW2 may be opened. Accordingly, the voltage applied to the third switch SW3 may be in a "high" state. In addition, the voltage V1 output from the first transistor TR1 of the first inverter INV1 may be different from the voltage V2 output from the second transistor TR 2. For example, the voltage V1 output from the first transistor TR1 of the first inverter INV1 may be in a logic "high" state, and the voltage V2 output from the second transistor TR2 may be in a logic "low" state. In addition, the voltage V3 applied to the differential amplifier 153 may be in a logic "low" state, and the output signal OUT of the differential amplifier 153 may be in a logic "low" state. In this case, the positive terminal of the differential amplifier 153 may include a non-inverting input terminal, and the negative terminal may include an inverting input terminal. In addition, the magnitude of the voltage applied to the differential amplifier 153 may be a value having a difference between the voltage input to the positive terminal and the voltage input to the negative terminal. When the first switch SW1 and the second switch SW2 are opened and the third switch SW3 is closed, the input signal IN may transition from the charge sharing level to a logic "high" state. When the input signal IN is transitioned to the logic "high" state, the first signal SG1 may be transitioned to the logic "low" state by the first inverter INV1, and as a result, the second signal SG2 may be transitioned to the logic "high" state by the second inverter INV 2. The input terminal NIP may be connected to the second node ND2 through the operation of the fourth section T4, and the state of the memory cell may be restored through the complementary operation of the input signal IN and the second signal SG 2.

Fig. 7 to 9 are circuit diagrams of bit line sense amplifiers 150a, 150b, and 150c, respectively, according to other embodiments.

Referring to fig. 7, the first current source 151 and the second current source 152 of the bit line sense amplifier 150a according to an embodiment may be non-independent current sources. In addition, the differential amplifier 153 may be connected to the first current source 151. In addition, referring to fig. 7, the first current source 151 of the bit line sense amplifier 150a according to an embodiment may include a non-independent current source, and the second current source 152 may include an independent current source. When the differential amplifier 153 is connected to the first current source 151, the output signal OUT of the differential amplifier 153 may be used as a voltage control signal of the first current source 151. IN one example, IN the case where the first current source 151 and the second current source 152 of the bit line sense amplifier 150 according to the embodiment are each non-independent current sources, when the differential amplifier 153 is connected to the first current source 151, the first current source 151 may adjust the first signal SG1 based on the output signal OUT of the differential amplifier 153, and the second current source 152 may adjust the first signal SG1 based on the input signal IN; when the differential amplifier 153 is connected to the second current source 152, the first current source 151 may adjust the first signal SG1 based on the input signal IN, and the second current source 152 may adjust the first signal SG1 based on the output signal OUT of the differential amplifier 153.

For example, when the bit line sense amplifier 150a according to the embodiment performs an offset compensation operation of the first signal SG1, the third switch SW3 may be opened, and the first and second switches SW1 and SW2 may be closed, and the second signal SG2 may include a negative input signal of the differential amplifier 153. IN addition, the input signal IN may include a positive input signal of the differential amplifier 153. When the input signal IN and the second signal SG2 are input to the differential amplifier 153, the output signal OUT of the differential amplifier 153 may control the voltage of the first current source 151, and the first current source 151 may adjust the first signal SG1 by generating a pull-up current.

In addition, when the bit line sense amplifier 150a according to the embodiment performs a sensing operation, all of the first switch SW1, the second switch SW2 and the third switch SW3 may be turned off, and the bit line sense amplifier 150a may sense a state of the memory cell by using the operation of the third section T3 described with reference to fig. 6. In addition, when the bit line sense amplifier 150a according to the embodiment performs a recovery operation, the third switch SW3 may be closed, the first switch SW1 and the second switch SW2 may be opened, and the bit line sense amplifier 150a may recover the state of the memory cell by using the process of the fourth section T4 described with reference to fig. 6.

Referring to fig. 8, the first current source 151 of the bit line sense amplifier 150b according to an embodiment may include an independent current source, and the second current source 152 may include a non-independent current source. In addition, a differential amplifier 153 may be connected to the second current source 152. When the differential amplifier 153 is connected to the second current source 152, the output signal OUT of the differential amplifier 153 may be used as a voltage control signal of the second current source 152.

For example, when the bit line sense amplifier 150b according to the embodiment performs the offset compensation operation of the first signal SG1, the third switch SW3 may be opened, and the first and second switches SW1 and SW2 may be closed, and the second signal SG2 may include a negative input signal of the differential amplifier 153. IN addition, the input signal IN may include a positive input signal of the differential amplifier 153. When the input signal IN and the second signal SG2 are input to the differential amplifier 153, the output signal OUT of the differential amplifier 153 may control the voltage of the second current source 152, and the second current source 152 may adjust the first signal SG1 by generating a pull-down current. In this case, since the first current source 151 is an independent current source, the first current source 151 may continuously generate a current of a preset value.

In addition, when the bit line sense amplifier 150b according to the embodiment performs a sensing operation, all of the first switch SW1, the second switch SW2 and the third switch SW3 may be turned off, and the bit line sense amplifier 150b may sense a state of the memory cell by using the operation of the third section T3 described with reference to fig. 6. In addition, when the bit line sense amplifier 150b according to the embodiment performs a restore operation, the third switch SW3 may be closed, the first switch SW1 and the second switch SW2 may be opened, and the bit line sense amplifier 150b may restore the state of the memory cell by using the process of the fourth section T4 described with reference to fig. 6.

Referring to fig. 9, the first current source 151 of the bit line sense amplifier 150c according to an embodiment may include a non-independent current source, and the second current source 152 may include an independent current source. In addition, the differential amplifier 153 may be connected to the first current source 151. When the differential amplifier 153 is connected to the first current source 151, the output signal OUT of the differential amplifier 153 may be used as a voltage control signal of the first current source 151.

For example, when the bit line sense amplifier 150c according to the embodiment performs the offset compensation operation of the first signal SG1, the third switch SW3 may be opened, and the first and second switches SW1 and SW2 may be closed, and the second signal SG2 may include a negative input signal of the differential amplifier 153. IN addition, the input signal IN may include a positive input signal of the differential amplifier 153. When the input signal IN and the second signal SG2 are input to the differential amplifier 153, the output signal OUT of the differential amplifier 153 may control the voltage of the first current source 151, and the first current source 151 may adjust the first signal SG1 by generating a pull-up current. In this case, since the second current source 152 is an independent current source, the second current source 152 may continuously generate a current of a preset value.

In addition, when the bit line sense amplifier 150c according to the embodiment performs a sensing operation, all of the first switch SW1, the second switch SW2 and the third switch SW3 may be turned off, and the bit line sense amplifier 150c may sense a state of the memory cell by using the operation of the third section T3 described with reference to fig. 6. In addition, when the bit line sense amplifier 150c according to the embodiment performs a recovery operation, the third switch SW3 may be closed, the first switch SW1 and the second switch SW2 may be opened, and the bit line sense amplifier 150c may recover the state of the memory cell by using the process of the fourth section T4 described with reference to fig. 6.

FIG. 10 is a flow chart of a bit line sensing method according to an embodiment.

Referring to fig. 10, according to an embodiment of a bit line sensing method, an input signal IN may be input from a bit line BL to a bit line sense amplifier 150 (S110). IN this case, the input signal IN may be input to the first inverter INV1 via the input terminal NIP. In addition, the input terminal NIP may include an input node.

When the input signal IN is input to the first inverter INV1, the first signal SG1 may be output from the first inverter INV1 (S120). The first signal SG1 may be output to the first node ND1, and the input signal IN may include a signal converted by the first inverter INV1. The first signal SG1 may be used as an intermediate signal for performing an offset compensation operation. For example, the first signal SG1 may be used as an input of the second inverter INV2, and the second inverter INV2 may adjust the first signal SG1 as feedback by generating the second signal SG 2. In other words, the first signal SG1 may be used as an intermediate signal for a complete offset compensation operation, as a final object of the offset compensation operation, and the bit line sense amplifier 150 according to an embodiment may continuously provide the first signal SG1 as feedback.

When the first signal SG1 is output, the first signal SG1 may be regulated by the first and second current sources 151 and 152 (S130). In this case, the first current source 151 may generate a pull-up current, and the second current source 152 may generate a pull-down current. In addition, the first and second current sources 151 and 152 may include independent current sources or independent current sources, respectively. A process of processing the first signal SG1 in the case where the first and second current sources 151 and 152 are independent and dependent current sources, respectively, is described in detail with reference to fig. 11 and 12.

As described above, the first signal SG1 may include an input of the second inverter INV2, and when the first signal SG1 is input to the second inverter INV2, the second signal SG2 may be output from the second inverter INV2 (S140). The second signal SG2 may have a value obtained by converting the first signal SG1 by the second inverter INV2, and may be in a state higher than that of the first signal SG 1. However, the state of the second signal SG2 is not limited thereto.

When the second signal SG2 is output, the input signal IN and the second signal SG2 may be input to the differential amplifier 153 (S150). In this case, the second signal SG2 may be used as a negative input signal of the differential amplifier 153.

When the input signal IN and the second signal SG2 are input to the differential amplifier 153, the differential amplifier 153 may output the output signal OUT (S160). The output signal OUT may be used as a voltage control signal of the first current source 151 or the second current source 152. When the output signal OUT controls the voltage with respect to the first current source 151 or the second current source 152, the first current source 151 or the second current source 152 may generate a current for adjusting the first signal SG1, and as a result, the first signal SG1 may be provided as feedback.

Fig. 11 and 12 are flowcharts of an offset compensation operation according to an embodiment. Fig. 11 is a flowchart of an offset compensation operation when the differential amplifier 153 is connected to the second current source 152, and fig. 12 is a flowchart of an offset compensation operation when the differential amplifier 153 is connected to the first current source 151.

Referring to fig. 11, an output signal OUT may be output from the differential amplifier 153 of the bit line sense amplifier 150 according to an embodiment (S210).

The output signal OUT generated by the differential amplifier 153 may adjust the output of the second current source 152 (S220). When the second current source 152 is a non-independent current source and is connected to the output terminal of the differential amplifier 153, the second current source 152 may perform an offset compensation operation on the first signal SG1 based on the output of the differential amplifier 153 for the second signal SG2 and the input signal IN. For example, when the amplitude of the second signal SG2 is insufficient to perform the bit line sensing operation, the second current source 152 may increase the pull-down current to adjust the value of the first signal SG1 to be smaller. However, when the amplitude of the second signal SG2 exceeds the amplitude for performing the bit line sensing operation, the second current source 152 may decrease the pull-down current to adjust the value of the first signal SG1 to be greater.

The first signal SG1 may be adjusted by using the feedback process of the first signal SG1 described above (S230).

Referring to fig. 12, an output signal OUT may be output from the differential amplifier 153 of the bit line sense amplifier 150 according to an embodiment (S310).

The output signal OUT generated by the differential amplifier 153 may adjust the output of the first current source 151 (S320). When the first current source 151 is a non-independent current source and is connected to the output terminal of the differential amplifier 153, the first current source 151 may perform an offset compensation operation on the first signal SG1 based on the output of the differential amplifier 153 for the second signal SG2 and the input signal IN. For example, when the amplitude of the second signal SG2 is insufficient to perform the bit line sensing operation, the first current source 151 may adjust (e.g., decrease) the pull-up current to adjust the value of the first signal SG1 to be smaller. However, when the amplitude of the second signal SG2 exceeds the amplitude for performing the bit line sensing operation, the first current source 151 may increase the pull-up current to adjust the value of the first signal SG1 to be greater.

The first signal SG1 may be adjusted by using the feedback process of the first signal SG1 described above (S330).

As a result of adjusting the first signal SG1 according to the offset compensation operation of fig. 11 and 12 described above, the bit line sense amplifier 150 may perform the offset compensation operation on the first signal SG 1. IN this case, since the capacitive load of the first signal SG1 has a value smaller than that of the input signal IN, relatively fast offset compensation can be performed and can be unaffected by the distribution.

Fig. 13 and 14 show examples of blocks to which the memory device 100 according to the embodiment is applied.

Referring to fig. 13, the blocks of the memory device 100 may include a plurality of memory cell array blocks 110-1, 110-2, 110-3, and 110-4 and a plurality of bit line sense amplifier blocks 210, 220, 230, and 240, and may further include capacitor blocks 310 and 320. Each of the plurality of bit line sense amplifier blocks 210, 220, 230, and 240 may include the plurality of bit line sense amplifiers 150, and further, each of the plurality of memory cell array blocks 110-1, 110-2, 110-3, and 110-4 may include an array of a plurality of memory cells. The capacitor blocks 310 and 320 may include a plurality of capacitors. The capacitor may be arranged to prevent a capacitive imbalance between the bit line BL and the complementary bit line BLB, and may be referred to as a balancing capacitor.

The second and third sense amplifier blocks 220 and 230 are arranged between the plurality of memory cell array blocks 110-1, 110-2, 110-3, and 110-4. The memory cell array blocks 110-2 and 110-3 may be connected to one bit line BL of the memory cell array block arranged in each of two directions. The bit line sense amplifier 150 included in the first and fourth sense amplifier blocks 210 and 240, which are disposed on edges of the first and fourth sense amplifier blocks 210 and 240, may be connected to one bit line BL disposed in one direction of the memory cell array blocks 110-1 and 110-4, respectively, and may be connected to a capacitor for preventing a capacitive imbalance in the other direction. Alternatively, the bit line sense amplifier 150 may be connected to the bit line BL including dummy cells for preventing the capacitance imbalance. In this way, when one bit line BL is connected in each of two directions of the bit line sense amplifier 150 and one of the bit lines becomes a complementary bit line (i.e., a reference bit line), the structure of the bit line sense amplifier 150 may be referred to as an open bit line sense amplifier structure.

In this case, which of the first switch SW1, the second switch SW2 and the third switch SW3 of the bit line sense amplifier is to be closed may be determined according to whether the memory cell array block to be sensed is an odd memory cell array block or an even memory cell array block. However, the above-described method is merely an example and is not limited thereto, and those skilled in the art will understand that various modifications are possible.

Fig. 14 illustrates the above-described structure of the memory device, the bit line sense amplifier 150 according to the inventive concept is connected in the form of a single-ended sense amplifier. Referring to fig. 14, each of the first and second sense amplifier blocks 210 and 220 may include a plurality of bit line sense amplifiers 150. In this case, the first sense amplifier block 210 may be connected to the plurality of memory cell array blocks 110-1 and 110-2, and the second sense amplifier block 220 may be connected to the single memory cell array block 110-2. In other words, the bit line sense amplifier 150 according to the embodiment may be configured in the form of a single-ended sense amplifier, and may also perform a sensing operation on the dummy lines of the edge memory cell array block. A structure in which the bit line sense amplifier 150 is connected to the memory cell array block according to an embodiment is described in detail with reference to fig. 15 and 16. The dummy lines herein may represent lines or patterns of the memory cell array block that do not have the electrical function of other lines or patterns of the memory cell array block but have a similar structural form to those other lines and patterns.

Fig. 15 is a block diagram of an example of a sense amplifier 250 to which the bit line sense amplifier 150 according to the embodiment is applied, and fig. 16 is a circuit diagram of an example of a sense amplifier 250 to which the bit line sense amplifier 150 according to the embodiment is applied.

Referring to fig. 15, the sense amplifier 250 according to an embodiment may include a bit line sense amplifier 150 and a switching unit, and in this case, the switching unit may include a first switching block SB1 and a second switching block SB2.

The sense amplifier 250 according to an embodiment may include the bit line sense amplifier 150 (e.g., 150a, 150b, and 150 c) described with reference to fig. 1-14.

Referring to fig. 15 and 16, the first and second switch blocks SB1 and SB2 may be connected to input terminals of the bit line sense amplifier 150 and select an input signal IN input to the bit line sense amplifier 150.

Referring again to fig. 14 through 16, the first and second switch blocks SB1 and SB2 may be connected to input terminals of the bit line sense amplifier 150 and determine whether to receive a bit line signal from one of the first and second memory cell array blocks 110-1 and 110-2. For convenience, when the first switch block SB1 is used as a switch unit connected to the first memory cell array block 110-1 and the second switch block SB2 is used as a switch unit connected to the second memory cell array block 110-2, the first switch block SB1 may be closed so that the bit line sense amplifier 150 may receive a signal from the first memory cell array block 110-1. Similarly, the second switch block SB2 may be closed so that the bit line sense amplifier 150 may receive a signal from the second memory cell array block 110-2. In other words, since the sense amplifier 250 according to an embodiment may be configured in the form of a single-ended sense amplifier, an input signal input to the bit line sense amplifier 150 may be selected by a switching unit (e.g., SB1 or SB 2).

On the other hand, the sense amplifier 250 according to an embodiment may be connected to one memory cell array block. For example, the bit line sense amplifier 150 may be connected to a dummy line of memory cells in the edge region. When the bit line sense amplifier 150 is connected to the memory cell array block of the edge region, the switch of the second switch block SB2 may be closed.

Because the sense amplifier 250 according to an embodiment may be configured in the form of a single-ended sense amplifier, the bit line sense amplifier 150 may be connected to a dummy line of memory cells in an edge region and may also be connected to a plurality of memory cells via the first and second switch blocks SB1 and SB 2.

Fig. 17 is a block diagram of an implementation example of a semiconductor memory device 3000 according to an embodiment.

As shown in fig. 17, the semiconductor memory device 3000 may include a plurality of semiconductor layers LA1 to LAn (for example, n may be an integer greater than 1). Each of the plurality of semiconductor layers LA1 to LAn may include a memory chip including a DRAM cell, or some of the semiconductor layers LA1 to LAn may include a master chip performing an interface connection (interface) with an external controller, and the remaining semiconductor layers may include slave chips storing data. In the example of fig. 17, it is assumed that the lowest semiconductor layer LA1 is the master chip, and the remaining semiconductor layers (i.e., LA2 to LAn) are the slave chips.

The plurality of semiconductor layers LA1 to LAn may transmit and receive signals to and from each other through the through-silicon vias TSV, and the main chip or the semiconductor layer LA1 may communicate with an external memory controller (not shown) through a conductive means (not shown) formed on an outer surface of the main chip. The configuration and operation of the semiconductor memory device 3000 are described below based on the first semiconductor layer 3100 (e.g., LA 1) as a master chip and the n-th semiconductor layer 3200 (e.g., LAn) as a slave chip.

The first semiconductor layer 3100 may include various circuits for driving the cell array 3210 provided in the slave chip (e.g., the nth semiconductor layer 3200). For example, the first semiconductor layer 3100 may include a row decoder (X-Dec) 3110 for driving word lines of the cell array 3210, a column decoder (Y-Dec) 3120 for driving bit lines BL, a data input/output unit (Din/Dout) 3130 for controlling input/output of data, a command buffer (CMDB) 3140 for receiving a command CMD from the outside, an address buffer (ADD) 3150 for buffering an address after receiving an address from the outside, and the like.

In addition, the first semiconductor layer 3100 may further include a DRAM management unit 3160 for managing memory operations of the slave chip. In one embodiment, DRAM management unit 3160 may include a refresh (Ref) counter 3161 and an address (Add) converter 3162. On the other hand, the n-th semiconductor layer 3200 may include a cell array 3210 and a peripheral circuit region 3220 in which other peripheral circuits for driving the cell array 3210 are arranged. For example, row/column selection units (not shown) for selecting rows and columns of the cell array 3210, bit line sense amplifiers, and the like may be arranged in the peripheral circuit region 3220. In this case, the bit line sense amplifier may include the bit line sense amplifiers 150, 150a, 150b, and 150c according to the above-described embodiments. Accordingly, the sensing sensitivity of the bit line can be improved by compensating for the offset of the inverter of the bit line sense amplifier.

Fig. 18 is a block diagram of an example of a server system 4000 including a semiconductor memory device according to an embodiment.

In fig. 18, the server system 4000 may include a memory controller 4100 and a plurality of Memory Modules (MMs) 4200_1 through 4200—n (e.g., n may be an integer greater than 1). Each of the plurality of MMs 4200_1 through 4200—n may include memory blocks 4220a and 4220b including a plurality of memory chips. For example, the memory chips constituting the memory blocks 4220a and 4220b may include DRAM chips.

The plurality of MMs 4200_1 through 4200—n may include memory modules to which the bit line sense amplifiers 150, 150a, 150b, and 150c according to the above-described embodiments or the memory device 100 and the semiconductor memory device 3000 according to the above-described embodiments are applied. Accordingly, the sensing sensitivity of the bit line can be improved by compensating for the offset of the inverter of the bit line sense amplifier.

In fig. 18, a server system 4000 having a single channel structure in which a memory controller 4100 and a plurality of MMs 4200_1 to 4200—n are mounted on the same circuit substrate 4300 is shown. However, this is merely an example and embodiments are not limited in this respect. The server system 4000 may be designed in various structures such as a multi-channel structure in which sub-substrates each including a plurality of MMs are coupled to a socket of a main substrate including the memory controller 4100 mounted thereon.

On the other hand, signal transmission of the plurality of MMs 4200_1 through 4200—n may be performed by using an optical input/output (I/O) connection. The server system 4000 may further include an electro-optical conversion unit 4400, and each of the plurality of MMs 4200_1 to 4200—n may further include a photoelectric conversion unit 4210. In addition, according to another embodiment, the electro-optical conversion unit 4400 may be embedded in the memory controller 4100.

The memory controller 4100 may be connected to the electro-optical conversion unit 4400 via an electrical path 4410. Accordingly, the memory controller 4100 can exchange signals with the electro-optical conversion unit 4400 via the electrical path 4410.

The electro-optical conversion unit 4400 may convert an electrical signal received from the memory controller 4100 into an optical signal and transmit the optical signal to the optical channel 4420, and may convert an optical signal received via the optical channel 4420 into an electrical signal and transmit the electrical signal to the electrical channel 4410.

The plurality of MMs 4200_1 to 4200—n may be connected to the electro-optical conversion unit 4400 via the optical channel 4420. The optical signal transmitted via the optical channel 4420 may be applied to the photoelectric conversion unit 4210 included in each of the plurality of MMs 4200_1 to 4200—n. The photoelectric conversion unit 4210 may convert the optical signal into an electrical signal and transmit the electrical signal to each of the memory blocks 4220a and 4220 b. In addition, the electric signal generated in each of the memory blocks 4220a and 4220b may be converted into an optical signal by the photoelectric conversion unit 4210 and may be output.

As described above, in the server system 4000, signal transmission between the memory controller 4100 and the plurality of memory blocks 4220a and 4220b can be performed in an optical input/output manner via the optical channel 4420.

Fig. 19 is a block diagram of a computing system 5000 including a memory device according to an embodiment.

The semiconductor memory device of the inventive concept may be installed in an information processing system (e.g., a computing system 5000) such as a mobile device and a desktop computer as a RAM 5200. RAM 5200 can comprise a semiconductor memory device or can have the form of a memory module. In addition, the RAM 5200 in fig. 19 may have a concept in which a memory, a memory device, and a memory controller are included.

The computing system 5000 according to embodiments may include a Central Processing Unit (CPU) 5100, RAM 5200, user interface 5300, and nonvolatile memory 5400, and each of these components may be electrically connected to the bus 5500. The nonvolatile memory 5400 can be used in mass storage devices such as Solid State Devices (SSDs) and Hard Disk Drives (HDDs).

In the computing system 5000, the RAM 5200 may include DRAM chips (not shown) including DRAM cells for storing data, and in each DRAM chip, one of the bit line sense amplifiers 150, 150a, 150b, and 150c according to an embodiment may be set. Accordingly, sensing efficiency of data stored in the DRAM chip can be improved.

The above description is merely an example description of the technical idea of the inventive concept, and a person skilled in the art to which the disclosed embodiments belong should be able to make various changes and modifications to the embodiments without departing from the essential features of the inventive concept. The embodiments are not intended to limit the scope of the inventive concept, but are intended to describe technical aspects of the inventive concept, and the scope of the technical aspects of the inventive concept is not limited by the embodiments. The scope of protection of the inventive concept should be construed according to the appended claims, and all technical ideas within the scope of the inventive concept should be construed as being included in the scope of the inventive concept.

While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the appended claims.

Claims

1. A bit line sense amplifier, comprising:

a first inverter configured to receive an input signal from a bit line via an input terminal and configured to output a first signal to a first node;

a second inverter configured to receive the first signal and configured to output a second signal to a second node;

A differential amplifier configured to receive an input signal as a positive input and a second signal as a negative input;

a first switch configured to electrically connect the input terminal to a positive terminal of the differential amplifier that receives a positive input; and

a second switch configured to electrically connect the second node to a negative terminal of the differential amplifier that receives the negative input,

wherein the first inverter is electrically connected to the second inverter by a first current source configured to provide a pull-up current to the first signal and a second current source configured to provide a pull-down current to the first signal.

2. The bit line sense amplifier of claim 1, wherein the first and second current sources each comprise a non-independent current source, and

the first current source is configured to adjust the first signal based on the input signal and the second current source is configured to adjust the first signal based on the output signal of the differential amplifier.

3. The bit line sense amplifier of claim 1, wherein the first and second current sources each comprise a non-independent current source, and

the first current source is configured to adjust the first signal based on the output signal of the differential amplifier, and the second current source is configured to adjust the first signal based on the input signal.

4. The bit line sense amplifier of claim 1, wherein the first current source comprises an independent current source and the second current source comprises a non-independent current source, and

the second current source is configured to regulate the first signal based on the output signal of the differential amplifier.

5. The bit line sense amplifier of claim 1, wherein the first current source comprises a non-independent current source and the second current source comprises an independent current source, and

the first current source is configured to regulate the first signal based on an output signal of the differential amplifier.

6. The bit line sense amplifier of claim 1, wherein when the first switch and the second switch are closed, the output signal of the second current source is configured to be adjusted based on the output signal of the differential amplifier, and the second signal is configured to be adjusted based on the output signal of the second current source.

7. The bit line sense amplifier of any of claims 1 to 6, further comprising: and a third switch electrically connecting the second node and the input terminal.

8. The bit line sense amplifier of claim 7, wherein the bit line sense operation is performed based on the input signal when the first switch, the second switch, and the third switch are open.

9. The bit line sense amplifier of claim 7, wherein the restore operation of the memory cell is performed when the first switch and the second switch are open and the third switch is closed.

10. A bit line sensing method performed by a bit line sense amplifier, the bit line sensing method comprising:

inputting an input signal via an input terminal of the bit line sense amplifier;

when an input signal is input to the first inverter, outputting the first signal to the first node using the first inverter;

outputting the second signal to the second node using the second inverter after the first signal is input to the second inverter; and

the input signal is input as a positive input and the second signal is input as a negative input to the differential amplifier,

wherein the first signal is regulated by a first current source configured to provide a pull-up current to the first signal and a second current source configured to provide a pull-down current to the first signal.

11. The bit line sensing method of claim 10, wherein the first and second current sources each comprise a non-independent current source, and

12. The bit line sensing method of claim 10, wherein the first and second current sources each comprise a non-independent current source, and

13. The bit line sensing method of claim 10, wherein the first current source comprises an independent current source and the second current source comprises a non-independent current source, and

14. The bit line sensing method of claim 10, wherein the first current source comprises a non-independent current source and the second current source comprises an independent current source, and

15. The bit line sensing method of claim 10, wherein the bit line sense amplifier further comprises a first switch electrically connecting the input terminal and the differential amplifier, and a second switch electrically connecting the second node and the differential amplifier, and

wherein when the first switch and the second switch are closed, the output of the second current source is adjusted based on the output of the differential amplifier, and the second signal is adjusted based on the output of the second current source.

16. The bit line sensing method of any one of claims 10 to 15, wherein the bit line sense amplifier further comprises a first switch electrically connecting the input terminal and the differential amplifier, a second switch electrically connecting the second node and the differential amplifier, and a third switch electrically connecting the input terminal and the second node, and

wherein, when the first switch, the second switch, and the third switch are turned off, a bit line sensing operation is performed based on the input signal.

17. The bit line sensing method of any one of claims 10 to 15, wherein the bit line sense amplifier further comprises a first switch electrically connecting the input terminal and the differential amplifier, a second switch electrically connecting the second node and the differential amplifier, and a third switch electrically connecting the input terminal and the second node, and

wherein when the first switch and the second switch are turned off and the third switch is turned on, a recovery operation of the memory cell is performed.

18. A sense amplifier configured to perform a bit line sense operation, the sense amplifier comprising:

a first inverter configured to receive an input signal via an input terminal and configured to output a first signal;

A differential amplifier configured to receive an input signal as a positive input and configured to receive a second signal as a negative input;

a first switch configured to electrically connect the input terminal and a positive terminal of the differential amplifier that receives a positive input;

a second switch configured to electrically connect the second node and a negative terminal of the differential amplifier that receives the negative input;

a first current source configured to regulate a first signal by providing a pull-up current;

a second current source configured to regulate the first signal by providing a pull-down current; and

and a switching unit configured to electrically connect the input terminal and one of the plurality of bit lines.

19. The sense amplifier of claim 18, wherein the switching unit includes a first switching block electrically connected to the first memory block excluding the dummy line and a second switching block electrically connected to the second memory block including the dummy line.

20. The sense amplifier of claim 19, wherein the switching unit is configured to: the second switch block is closed when the input terminal is electrically connected to the second memory block.