CN116593869A

CN116593869A - Ultra-high speed measuring method and system for high-density test chip

Info

Publication number: CN116593869A
Application number: CN202310622198.6A
Authority: CN
Inventors: 成家柏; 陈巍; 杨璐丹; 蓝帆
Original assignee: Hangzhou Guangli Microelectronics Co ltd
Current assignee: Hangzhou Guangli Microelectronics Co ltd
Priority date: 2023-05-29
Filing date: 2023-05-29
Publication date: 2023-08-15

Abstract

The application provides an ultra-high speed measurement method of a high-density test chip, which is characterized in that signals required by the test are preset and correspondingly written into a function generator and a source measurement unit; the control function generator and the source measuring unit respectively generate a CLK signal and a DF signal which are triggered synchronously, an address register connected with the function generator switches addresses according to the waveform conversion in the CLK signal, the trigger source measuring unit continuously samples different addresses according to DF signal frequency, each address corresponds to a plurality of sampling data, and the effective measured value corresponding to each signal address of the function generator is determined from the plurality of sampling data and aligned. The ultra-high-speed test is realized by means of synchronous triggering of hardware and continuous sampling of SMU, each address is measured for a plurality of times, and alignment of the test address and effective data is realized by means of data analysis, so that the problem of dislocation of the test data can be avoided, and the stability of the test data is effectively improved. There is also provided a testing system having corresponding advantages.

Description

Ultra-high speed measuring method and system for high-density test chip

Technical Field

The application belongs to the technical field of semiconductor design and production, and particularly relates to an ultra-high speed measuring method and an ultra-high speed measuring system for a high-density test chip.

Background

Conventional semiconductor manufacturing is generally tested by short-range test chips to obtain the defect rate and yield of the production process, and can be divided into two types according to the placement positions in the wafer: a stand-alone test chip (MPW) and a test chip (Scribe line) placed in the Scribe line. The larger area of the individual test chips requires to occupy one chip site, which corresponds to the cost of manufacturing such a partial area mask for semiconductor manufacturers. The dicing grooves are reserved when chips are cut on the wafer, and the test chips are placed in the dicing grooves, so that the positions of the chips can be not occupied, the semiconductor manufacturer does not need to bear expensive mask cost, and a large amount of cost is saved.

Among them, especially, ultra-high density test chips are also required to be compatible with ultra-high speed test. The traditional test method needs to take a lot of time to complete the test, which cannot meet the actual requirement at all. In the prior art, tens of thousands to hundreds of thousands of test keys (test structures/test units) are placed in each module (test unit), as shown in fig. 1, address switching is performed by switching the level of a clock signal (CLK) port (from a low potential to a high potential), so that the switching of the tested test keys is realized, and measurement is performed at ports such as DF, so as to obtain the electrical parameters of the tested test-keys.

The existing test mode is realized by a conventional test algorithm, namely: CLK is pulsed on, DF is measured using SMU and so on and is cycled until all test keys are measured. The method is realized completely through algorithm command control, wherein each step involves the steps of software and hardware communication, hardware initialization and the like, so that the whole test process is quite long, for example, a piece of denseArray module containing 327K test-keys, and if the method is used for measuring full-map, the time is about 5 days; and also easily causes problems such as test data dislocation.

Disclosure of Invention

In order to achieve one or a part or all of the above purposes or other purposes, the present application provides a method for measuring ultra-high speed of a high density test chip, which can realize ultra-high speed test by means of hardware triggering and continuous sampling of SMU, and only performs the steps of software and hardware communication, hardware initialization, etc. at the initial stage of test, and is completely controlled by hardware itself during the test process, thereby realizing the substantial improvement of test efficiency, realizing the alignment of test data by means of data analysis, avoiding the problems of dislocation of test data, etc., effectively improving the stability of test data, and optimizing the reliability of test results. The application also provides a test system which can support synchronous triggering of the function generator and the SMU and continuous sampling of the SMU.

Other objects and advantages of the present application will be further appreciated from the technical features disclosed in the present application.

The application provides a super-high speed measuring method of a high-density test chip, wherein test equipment is provided with a function generator, an address register and a source measuring unit, wherein the address register and the source measuring unit are connected with the function generator; the ultra-high speed measurement method comprises the following steps:

presetting signals required by testing and correspondingly writing the signals into memories of the function generator and the source measurement unit;

controlling the function generator and the source measurement unit to respectively generate a CLK signal and a DF signal which are triggered synchronously; the address register triggers the source measuring unit to continuously sample different addresses according to the frequency of the DF signal according to the switching address of the waveform in the CLK signal;

sampling data are acquired, and effective measured values corresponding to each address are determined from the sampling data.

The sampling frequency of the source measurement unit for continuous sampling is set to be in a multiple relation with the address switching frequency; and each address corresponds to one or more sampling data, and a valid measured value corresponding to each address is obtained from the sampling data through analysis.

The ultra-high speed measurement method is executed based on a preset test algorithm, the configuration information of signals is preset in the test algorithm, and the trigger signals are controlled and sent through the test algorithm; the test device receives and transmits a trigger signal, and synchronously triggers the function generator and the source measurement unit.

The trigger signal comprises a frequency parameter of the CLK signal, a sampling duration of the source-measurement unit.

The test equipment is provided with a programmable logic device, a synchronous trigger module and a clock module, wherein the programmable logic device acquires a trigger signal of a test algorithm and transmits the trigger signal to the synchronous trigger module; the synchronous triggering module controls the function generator and the clock module to synchronously generate a CLK signal and a clock signal; the clock signal of the clock module is transmitted to the source measuring unit to generate a DF signal triggered synchronously.

The programmable logic device includes: the Field Programmable Gate Array (FPGA).

The sampling data comprises SO voltage and DF current, and the method for determining the effective measured value corresponding to each address from the plurality of sampling data corresponding to each address comprises the following steps:

determining a stable interval in each address according to the SO voltage switching condition;

analytically determining from a plurality of said DF currents valid measured values located within a stability interval for each address;

each address is assigned a valid measurement after analysis.

The determining the stable interval in each address through the SO voltage switching condition comprises:

arranging the measured SO voltages according to a measurement sequence;

sequentially determining the voltage level of (each) SO voltage according to the numerical relation between the SO voltage and the working voltage VDD;

determining the voltage level change of (each) said SO voltage from the difference from the voltage level of the previous SO voltage;

and determining effective measurement points belonging to a stable interval according to the voltage level change conditions of the adjacent SO voltages.

The effective measurement points belonging to the stable interval are determined specifically by:

and selecting an effective measurement point according to that one SO voltage and the front and back adjacent SO voltages have no voltage change.

The selecting method for the effective measured value comprises the following steps:

taking a first current measurement in the stable interval;

taking the current average value of a plurality of DF currents in the stable interval;

the median of the plurality of DF currents in the stable interval is taken.

The application also provides a test system, which comprises a function generator, a source measurement unit and a programmable logic device, wherein the programmable logic device acquires a trigger signal of a test algorithm and transmits the trigger signal to the function generator and the source measurement unit, the synchronous trigger function generator and the source measurement unit respectively generate a CLK signal and a DF signal, an address register connected with the function generator switches addresses according to the CLK signal, and the source measurement unit continuously samples according to the DF signal triggered synchronously, wherein each address corresponds to a plurality of sampling data.

The application also provides a test system, which comprises a function generator, a source measurement unit, a programmable logic device, a synchronous trigger module and a clock module, wherein the programmable logic device acquires a trigger signal of a test algorithm and transmits the trigger signal to the synchronous trigger module, the synchronous trigger module controls the function generator and the clock module to synchronously generate clock signals with different frequencies, an address register connected with the function generator switches addresses according to waveform conversion in the clock signals, the clock signal of the clock module is transmitted to the source measurement unit to generate a DF signal triggered synchronously and continuously samples, and each address corresponds to one or more sampling data.

The test system comprises a data processing software unit for determining a valid measurement value corresponding to each address from the sampled data.

Compared with the prior art, the application has the beneficial effects that:

the application realizes parallel triggering operation by synchronously triggering hardware, and de-associating address switching with testing of the source measuring unit, and only performs the steps of software and hardware communication, hardware initialization and the like at the initial stage of testing, so that the reading and setting of a testing algorithm are not required before one device to be tested is measured after the other device to be tested is measured, the links of original communication and the like are omitted, and the testing speed can be effectively provided, and the error rate is reduced. Specifically, the ultra-high speed test realized by the method can be increased to 2K/sec, even 40K/sec, and the test efficiency is increased by 100-4000 times compared with the traditional test method.

According to the application, the internal measurement unit is continuously sampled for a plurality of times in one address switching period, so that a large amount of data can be acquired, and the later data processing is used for ensuring that the test key is hardly missed and a stable measured value is obtained.

The foregoing and other objects, features and advantages of the application will be apparent from the following more particular description of preferred embodiments, as illustrated in the accompanying drawings.

Drawings

In order to more clearly illustrate the technical solutions of specific embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.

FIG. 1 is a schematic diagram showing a process of obtaining an electrical parameter of a test-key to be tested in the prior art.

Fig. 2 shows a schematic diagram of an ultra-high speed measurement according to an embodiment of the present application.

Fig. 3 shows a schematic diagram of ultra-high speed measurement of another integrated test algorithm provided by an embodiment of the present application.

Fig. 4 shows a schematic diagram of signal timing triggering of CLK/DF terminals according to an embodiment of the application.

Fig. 5 shows a schematic diagram of hardware configuration according to an embodiment of the present application.

Fig. 6 shows a schematic diagram of relevant signal input and hardware measurement behavior provided by an embodiment of the present application.

Fig. 7 is a schematic diagram showing the frequency and sampling condition of each signal provided by the embodiment of the application.

Fig. 8 shows a schematic diagram of a data processing result provided by an embodiment of the present application.

Fig. 9 shows a schematic diagram of a test system according to an embodiment of the present application.

Detailed Description

The foregoing and other features, aspects, and advantages of the present application will become more apparent from the following detailed description of a preferred embodiment, which proceeds with reference to the accompanying drawings. The directional terms mentioned in the following embodiments are, for example: upper, lower, left, right, front or rear, etc., are merely references to the directions of the attached drawings. Thus, the directional terminology is used for purposes of illustration and is not intended to be limiting of the application.

It should be noted that the address register contains a scan data output Signal (SO) output port that outputs the least significant bits of the address signal to confirm whether the DUT under test is correct. The devices under test may form a DUT array (DUT array), and DUTs within the same DUT array are sequentially selected by address and tested sequentially at the time of testing, so that one DUT array contains all addresses for the total duration of the test.

The embodiment provides an ultra-high-speed measurement method of a high-density test chip, which comprises a function generator and a source measurement unit, wherein the function generator and the source measurement unit are positioned in test equipment, the function generator is connected to a CLK (CLK) pad of an address register in the test chip through a probe card, the source measurement unit SMU is a measurement SMU, and the measurement SMU is connected to DF (digital) and DL (digital) pads (namely a switching circuit end) of the test chip through the probe card, so that voltage and data test is provided for the test chip; as shown in fig. 2, the method comprises the following steps:

step S1, presetting signals required by testing and correspondingly writing the signals into memories of a function generator and a source measurement unit; the preset signals may be PGU signal (CLK/clock signal) and SMU signal (DF signal/test signal), i.e. the frequency of what time length the function generator performs waveform transformation, and the sampling speed of what time length the source measurement unit performs continuous sampling.

And S2, the control function generator and the source measurement unit respectively generate a CLK signal and a DF signal which are synchronously triggered, namely, the signals at the CLK/DF end are synchronously triggered in time sequence, the address register switches addresses according to the waveform conversion in the CLK signal received by the CLK bonding pad, and the source measurement unit is triggered to continuously sample different addresses according to the frequency of the DF signal.

And S3, acquiring sampling data, and determining a valid measured value corresponding to each address from the sampling data.

In some embodiments, the function generator is illustratively configured as a pulse generator PGU and the source measurement unit is configured as a measurement SMU.

In some embodiments, as shown in fig. 3, a test algorithm is also provided in this embodiment.

By presetting configuration information of signals required for testing the device under test in a testing algorithm, the configuration information may include related information of a pulse generator PGU (CLK) signal and a source measurement unit SMU (DF) signal, for example: the operating Voltage (VDD) of the pulse generator PGU and the source measurement unit SMU, the frequency (freq) of the PGU, the power line period/sampling power Period (PLC) of the source measurement unit SMU, sampling continuous time (seqtime) and other parameters, wherein the sampling continuous time (seqtime) determines the test duration.

After finishing setting PGU/SMU signals in a test algorithm, storing the corresponding write pulse generator PGU and source measurement unit SMU in a memory; if the test needs to be started, a trigger signal is sent through a test algorithm, and the test equipment receives and transmits the trigger signal to realize the synchronous trigger of the pulse generator PGU and the source measurement unit SMU, specifically to generate a CLK signal and a DF signal which are synchronously triggered. The timing of signals at the CLK and DF terminals is shown in FIG. 4.

In some embodiments, the trigger signal may include a frequency parameter of the CLK signal, a sampling duration of the source-measurement unit. In addition, in order to ensure that the problem of missing measurement or incorrect address corresponding data of the device to be measured does not exist, the sampling speed of the source measurement unit SMU may be several times that of the pulse generator PGU, and if the frequency of the PGU (CLK) signal is set to f, the source measurement unit SMU will measure at the frequency of nxf, where N is a positive integer greater than or equal to 1.

In some embodiments, N is 1, and each address may be assigned to each test data by data alignment analysis, so as to avoid the test data misalignment in the prior art. In other embodiments, if the clock N is greater than 1, the stability interval can be determined from a plurality of test points corresponding to each address through data analysis, then the most accurate effective measurement value is determined from the test points in the stability interval, and finally each address is given, so that the problems of test data dislocation and missed test of test keys in the prior art can be better and more comprehensively avoided.

In some embodiments, in order to achieve the technical purpose of synchronous triggering, as shown in fig. 5, the test device is further provided with a programmable logic device, an output end of the programmable logic device is electrically connected with the function generator and the source measurement unit, the programmable logic device obtains a trigger signal of a test algorithm and transmits the trigger signal to the function generator and the source measurement unit, the function generator is controlled to generate a CLK signal, the programmable logic device generates a clock signal, the clock signal is transmitted to the source measurement unit to generate a DF signal for synchronous triggering and continuously sampling, the synchronous triggering function generator and the source measurement unit respectively generate the CLK signal and the DF signal, an address register connected with the function generator switches addresses according to the CLK signal, and the source measurement unit continuously samples according to the DF signal for synchronous triggering, wherein each address corresponds to a plurality of sampling data.

In some embodiments, to achieve the technical purpose of synchronous triggering, in the hardware setting layer, as shown in fig. 5, the test device further includes a programmable logic device, a synchronous triggering module, and a clock module, where an output end of the programmable logic device is electrically connected to an input end of the synchronous triggering module and an input end of the clock module, the synchronous triggering module includes two synchronous output ports, one of which is electrically connected to a function generator (FGen), the other of which is electrically connected to an input end of the clock module, and an output end of the clock module is electrically connected to the source measurement unit SMU.

The programmable logic device acquires a trigger signal of a test algorithm and transmits the trigger signal to a synchronous trigger module, the synchronous trigger module controls a function generator and a clock module to synchronously generate a CLK signal and a clock signal, the clock signal of the clock module is transmitted to a source measurement unit, the source measurement unit determines a DF signal (measurement signal) according to the clock signal so as to carry out continuous sampling, and the function generator (pulse generator PGU) inputs the clock signal (CLK) into an address register through a CLK bonding pad to carry out address switching; each device in the test chip is provided with different address bits, the address bits correspond to each address bit device in the test chip through a CLK signal, and the test equipment realizes continuous sampling on each address bit device through a source measurement unit SMU; the test result is temporarily stored in the source measurement unit SMU or externally connected with a memory; after the test is finished, the tester extracts and stores all test data into a Database (Database) through a test algorithm, and analyzes the test result through an online analysis engine.

In some embodiments, the programmable logic device may be a field programmable gate array (FPGA, field programmable gate Array), but may also be other programmable logic devices, such as programmable array logic (PAL, programmable array logic), generic array logic (GAL, generic array logic), etc., in which the programmable logic device is an FPGA.

In some embodiments, the sampled data may include SO voltage (output signal voltage) and DF current, and determining the effective measurement value corresponding to each address from the plurality of sampled data specifically includes:

determining a stable interval in each address through SO voltage switching conditions;

analyzing and determining effective measured values located in a stable interval of each address from a plurality of DF currents;

each address is assigned a valid measurement after analysis.

In some embodiments, determining the stability interval in each address by the SO voltage switching case further comprises:

arranging the measured SO voltages in a measurement order by arranging the SO voltages at all measurement points in one DUT array in the measurement order;

and determining the voltage level of each SO voltage in turn according to the numerical relation between the SO voltage and the working voltage VDD.

Determining a voltage level change condition of each SO voltage according to a difference value between the voltage level of the SO voltage and a voltage level of a previous SO voltage; and determining effective measurement points belonging to the stable interval according to the voltage level change condition of the adjacent SO voltages. Referring to fig. 7, a measurement context such as V12 and V13 is shown, where V12 is the previous SO voltage of V13.

In some embodiments, to more clearly illustrate the data processing procedure, a specific case will be described, in which the waveform of the CLK pad input frequency f is set, the source measurement unit SMU performs measurement at a frequency of 5×f, and in the case of synchronous triggering, as shown in fig. 6, the CLK pad triggers the switching address, and the source measurement unit SMU triggers the port voltage/current signal synchronous measurement.

According to the corresponding frequency setting, the SO voltage of each address will be measured 5 times, and each address analog signal port (DFx) will be measured 5 times, specifically, the signal frequency and sampling situation as shown in fig. 7 will be formed.

The most accurate current value In the corresponding address stability interval is selected from the 5 current measurement values (In 1-In 5, n epsilon [1, last address sequence number ] and being an integer) of DFx, and ADDR0 is measured before signal triggering and is not In the periodic measurement cycle.

Specifically, the stable interval in each address is determined by the SO voltage switching condition, including the steps of:

arranging the measured SO voltages in a measurement order, and optionally arranging all measurement points V (SO) passing through one DUT array in the measurement order;

and adding a parameter level for calculating the SO output voltage level, wherein the parameter level is calculated by the following formula: level=if { V (SO) < Vdd/2,0:1} (Vdd is the operating voltage, vdd=0.9 in the real column), i.e. when the SO voltage is less than half the operating voltage, its parameter level is 0, otherwise it is 1;

the parameter transition is added to indicate that the voltage level of the level is changed, and is calculated by the following formula: the transition=if { abs (level_ (n+1) -level_n) >0,1:0}, i.e. whether the absolute value of the difference between the parameters level of the two SO voltages before and after calculation is greater than 0, if greater than 0, the parameter transition is 1, otherwise is 0;

and adding a parameter validmeasure which indicates whether the measuring point belongs to an effective measuring point of a stable interval or not, wherein the parameter validmeasure is calculated by the following formula:

validmeasure=if { OR (transition_ (n-1) =1, transition_n=1, transition_ (n+1) =1), 0:1}, i.e. whether the effective measurement point belongs to the stable section is determined by whether the parameter transitions to the front and back two adjacent SO voltages are both 1, and if all three parameter transitions are 0, the effective measurement point belongs to the stable section.

When a stable interval contains a plurality of effective measurement points, the selecting a value mode of one effective measurement value comprises the following steps:

taking a first current measurement in the stable interval;

the median of the plurality of DF currents in the stable interval is taken.

As shown in fig. 8, the left side is a specific case of calculating parameters level, parameter transition, and parameter validmeasurement after data processing, and then selecting a first current measurement value from the parameters validmeasurement as 1 as an effective measurement point to assign each address.

In this embodiment, a Test system is further provided, and referring to fig. 5 and 9, the Test system includes a Database (Database), an on-line analysis engine (Online Analysis Engine), a function generator (FGen), a switch matrix module (SWM), at least six Source Measurement Units (SMU), and an addressable Test Chip (Test Chip) combined with a multi-purpose Address Register (Address Register), and a probe card to form a complete Test system.

In the test system, a first source measurement unit in a test instrument is connected with a probe card, and the probe card is connected with an addressable test chip through power pads VDD and VSS; the second source measuring unit is connected with a switch matrix (SWM), the switch matrix (SWM) is connected with a multipurpose Address Register (Address Register) through an input pad SE (shift enable signal end) and an SI (shift input signal end), and the multipurpose Address Register (Address Register) is connected with a signal input end of an addressing circuit (Addressing Circuit) in an addressable Test Chip (Test Chip); the third source measuring unit is connected with a multipurpose Address Register (Address Register) through an input pad RST (reset signal end), and the function generator (FGen) is connected with the multipurpose Address Register (Address Register) through an input pad CLK (clock signal end); the fourth, fifth and sixth source measuring units are connected with a probe card, and the probe card is connected with a switch circuit (Switching Circuit) through a bonding pad DF, DL, GF, GL, SF, SL, BF (signal line end of a device to be tested); the Address Register (Address Register) is connected with the addressing circuit (Addressing Circuit) through a bonding pad; the online analysis engine (Online Analysis Engine) is connected to a Database (Database), a function generator (FGen) and a measurement source measurement unit.

On the basis, the test system of the embodiment further comprises a programmable logic device (FPGA), wherein the output end of the programmable logic device is electrically connected with the function generator and the source measurement unit, the programmable logic device acquires a trigger signal of the test algorithm and transmits the trigger signal to the function generator and the source measurement unit, the function generator is controlled to generate a CLK signal, meanwhile, the programmable logic device generates a clock signal, the clock signal is transmitted to the source measurement unit to generate a synchronous trigger DF signal and continuously samples, the synchronous trigger function generator and the source measurement unit respectively generate the CLK signal and the DF signal, an address register connected with the function generator switches addresses according to the CLK signal, the source measurement unit continuously samples according to the synchronous trigger DF signal, and each address corresponds to one or more sampling data.

On the basis, the test system preferably comprises a programmable logic device (FPGA), a synchronous trigger module and a clock module, wherein the programmable logic device acquires trigger signals of a test algorithm and transmits the trigger signals to the synchronous trigger module, the synchronous trigger module controls the function generator and the clock module to synchronously generate clock signals with different frequencies, a multipurpose Address Register (Address Register) connected with the function generator (FGen) switches addresses according to waveform transformation in the clock signals, and the clock signals of the clock module are transmitted to the source measurement unit to be continuously sampled according to the frequency of the clock signals, and each Address corresponds to a plurality of sampling data.

The output end of the programmable logic device is electrically connected with the input ends of the synchronous triggering module and the clock module, the synchronous triggering module comprises two synchronous output ports, one synchronous output port is electrically connected with the function generator (FGen), and the output end of the clock module is electrically connected with the fourth source measuring unit SMU.

The programmable logic device acquires a trigger signal of a test algorithm and transmits the trigger signal to a synchronous trigger module, the synchronous trigger module controls a function generator and a clock module to synchronously generate a CLK signal and a clock signal, the clock signal of the clock module is transmitted to a fourth source measurement unit, the fourth source measurement unit determines a DF signal (measurement signal) according to the clock signal so as to carry out continuous sampling, and the function generator (which can be a pulse generator PGU) inputs the clock signal (CLK) into an address register through a CLK bonding pad for address switching; each device in the test chip is provided with different address bits, the address bits correspond to each address bit device in the test chip through a CLK signal, and the test equipment realizes continuous sampling on each address bit device through a fourth source measurement unit SMU; the test result is temporarily stored in a fourth source measurement unit SMU or externally connected with a memory; after the test is finished, the tester extracts and stores all test data into a Database (Database) through a test algorithm, analyzes the test result through an online analysis engine/data processing software (the data processing software can be located in the online analysis engine), and determines a valid measurement value corresponding to each address from a plurality of sampling data.

The ultra-high-speed test is realized by means of synchronous triggering of hardware and continuous sampling of SMU, and only the steps of software and hardware communication, hardware initialization and the like are needed at the initial stage of the test, and the hardware is completely controlled in the test process, so that the test efficiency can be greatly improved, and the stability of test data can be effectively improved.

The foregoing description is only illustrative of the preferred embodiments of the present application and is not intended to limit the scope of the application, i.e., all simple and equivalent changes and modifications that may be made in accordance with the claims and specification are intended to be included within the scope of the application as defined by the appended claims. Furthermore, not all of the objects, advantages, or features of the present disclosure are required to be achieved by any one embodiment or claim of the present disclosure. Furthermore, the abstract sections and the application names are used solely to assist patent document retrieval and are not intended to limit the scope of the claims. Furthermore, references to "first," "second," etc. in this specification or in the claims are only intended to name an element or distinguish between different embodiments or ranges, and are not intended to limit the upper or lower limit on the number of elements.

Claims

1. The ultra-high speed measurement method of a high-density test chip, the test equipment has function generator, address register and source measurement unit connected with function generator; the method is characterized by comprising the following steps of:

presetting a CLK signal and a DF signal required by a test, and correspondingly writing the CLK signal and the DF signal into memories of a function generator and a source measurement unit;

2. The ultra-high-speed measurement method according to claim 1, wherein a sampling frequency at which the source measurement unit performs continuous sampling is set in a multiple relationship with an address switching frequency; and each address corresponds to one or more sampling data, and a valid measured value corresponding to each address is obtained from the sampling data through analysis.

3. The ultra-high-speed measurement method according to claim 2, wherein the sampling frequency at which the source measurement unit performs continuous sampling is twice or more the address switching frequency.

4. The ultra-high speed measurement method according to claim 1, wherein the ultra-high speed measurement method is performed based on a preset test algorithm in which configuration information of a signal is preset and a trigger signal is controlled to be transmitted by the test algorithm; the test device receives and transmits a trigger signal, and synchronously triggers the function generator and the source measurement unit.

5. The ultra-high speed measurement method according to claim 4, wherein the trigger signal comprises a frequency parameter of CLK signal, sampling duration of the source measurement unit.

6. The ultra-high-speed measurement method according to claim 4, wherein the test equipment is provided with a programmable logic device, a synchronous trigger module and a clock module; the programmable logic device acquires a trigger signal of a test algorithm and transmits the trigger signal to the synchronous trigger module; the synchronous triggering module controls the function generator and the clock module to synchronously generate a CLK signal and a clock signal; the clock signal of the clock module is transmitted to the source measuring unit to generate a DF signal triggered synchronously.

7. The ultra-high-speed measurement method according to claim 2, wherein the sampling data includes SO voltage and DF current, and the method of determining the effective measurement value corresponding to each address from the plurality of sampling data corresponding to each address includes:

each address is assigned a valid measurement after analysis.

8. The ultra-high speed measurement method according to claim 7, wherein the determining the stability interval in each address by the SO voltage switching condition comprises:

arranging the measured SO voltages according to a measurement sequence;

9. The ultra-high speed measurement method according to claim 8, wherein determining the effective measurement points belonging to the stable interval is specifically performed by:

10. The ultra-high speed measurement method according to claim 7, wherein selecting a value of the effective measurement value includes:

taking a first current measurement in the stable interval;

the median of the plurality of DF currents in the stable interval is taken.

11. The test system is characterized by comprising a function generator, a source measurement unit, a programmable logic device, a synchronous trigger module and a clock module, wherein the programmable logic device acquires trigger signals of a test algorithm and transmits the trigger signals to the synchronous trigger module, the synchronous trigger module controls the function generator and the clock module to synchronously generate clock signals with different frequencies, an address register connected with the function generator switches addresses according to waveform conversion in the clock signals, the clock signal of the clock module is transmitted to the source measurement unit to generate DF signals triggered synchronously and continuously sample, and each address corresponds to one or more sampling data.

12. The test system of claim 11, comprising a data processing software unit for determining a valid measurement value for each address from the sampled data.