CN116583007A - MCP chip - Google Patents

Abstract

The invention discloses an MCP chip, which comprises a PCB substrate, SPI NAND FLASH and SPI DDR3SDRAM which are packaged on the front surface of the PCB substrate, and 24 bonding pads which are arranged on the back surface of the PCB substrate; SPI NAND FLASH is provided with 8 at least pins, SPI DDR3SDRAM is provided with 16 pins, SPI NAND FLASH's 8 pins respectively with 8 wherein the pad electricity is connected, SPI DDR3 SDRAM's 16 pins respectively with 16 other pads electricity is connected. The MCP chip integrates SLCNAND and DDR3, improves erasing times, and realizes miniaturization of products.

Description

MCP chip

Technical Field

The invention relates to the technical field of chips, in particular to an MCP chip.

Background

In order to meet the requirement of miniaturization of equipment, some existing memory chips adopt an MCP (Multi-Chip Package) structure form of NOR+PSRAM (nonvolatile Flash memory) to store codes and data, and the PSRAM (pseudo static random access memory) is used for storing cache data operated by MCU and DSP, but the Chip is not stable enough in design, insufficient in erasing times, not good in heat dissipation design and not good in space utilization. There is a need to provide a multi-chip package that increases the number of erasures and saves space.

Disclosure of Invention

The invention mainly aims to provide an MCP chip, which aims to realize multi-chip packaging and save space.

In order to achieve the above purpose, the MCP chip provided by the invention comprises a PCB substrate, SPI NAND FLASH and SPI DDR3SDRAM which are packaged on the front surface of the PCB substrate, and 24 bonding pads which are arranged on the back surface of the PCB substrate; SPI NAND FLASH is provided with 8 at least pins, SPI DDR3SDRAM is provided with 16 pins, SPI NAND FLASH's 8 pins respectively with 8 wherein the pad electricity is connected, SPI DDR3 SDRAM's 16 pins respectively with 16 other pads electricity is connected.

Optionally, the SPI NAND FLASH and SPI DDR3SDRAM are packaged side-by-side;

optionally, the PCB substrate is rectangular, four side edges of the PCB substrate are respectively provided with 6 bonding pads, the 6 bonding pads on each edge are arranged at equal intervals, bonding pads on the upper and lower edges are symmetrically arranged, and bonding pads on the left and right edges are symmetrically arranged;

optionally, the 6 pads on the right are respectively connected with the NAF_ALE pin, NAF_CE# pin, NAF_CLE pin, NAF_DQ pin, NAF_R/B# pin and NAF RE# pin of SPI NAND FLASH, and the 6 pads on the left are respectively connected with the DR3_ADR pin, the DR3_BA pin, the DR3_WE pin, the DR3_RAS pin and the DR3_CAS pin of the SPI DDR3 SDRAM;

optionally, the 6 pads on the top side are respectively connected with the NAF_WE pin, NAF_WP# pin, NAF_VCC pin and NAF_VSS pin of SPI NAND FLASH, and the 6 pads on the bottom side are respectively connected with the DR3_RESET pin, the DR3_DQ pin, the DR3_CKE pin, the DR3_CLK pin, the DR3_CS pin, the DR3_ODT pin, the DR3_DQS00 pin and the DR3_DM00 pin of the SPI DDR3 SDRAM;

optionally, the front surface of the PCB substrate is coated with plastic packaging glue.

According to the technical scheme, the MCP chip is adopted, the pads with the number equal to the total number of pins of SPI NAND FLASH and SPI DDR3SDRAM are arranged on the back surface of the PCB substrate, each pin of SPI NAND FLASH and SPI DDR3SDRAM is connected with each pad, pins are not multiplexed between SPI NAND FLASH and SPI DDR3SDRAM, erasing times are improved, and miniaturization of products is achieved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of an MCP chip according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of wiring of an embodiment of an MCP chip of the present invention;

FIG. 3 is a schematic diagram of wiring of an embodiment of an MCP chip of the present invention;

fig. 4 is a schematic diagram of electrical specifications of an embodiment of an MCP chip of the present invention.

The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that, if directional indications (such as up, down, left, right, front, and rear … …) are included in the embodiments of the present invention, the directional indications are merely used to explain the relative positional relationship, movement conditions, etc. between the components in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indications are correspondingly changed.

In addition, if there is a description of "first", "second", etc. in the embodiments of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.

The invention provides an MCP chip.

In an embodiment of the present invention, referring to fig. 1 to 4, the MCP chip includes a PCB substrate, SPI NAND FLASH and SPI DDR3SDRAM packaged on the front side of the PCB substrate, and 24 pads disposed on the back side of the PCB substrate; SPI NAND FLASH is provided with 8 at least pins, SPI DDR3SDRAM is provided with 16 pins, SPI NAND FLASH's 8 pins respectively with 8 wherein the pad electricity is connected, SPI DDR3 SDRAM's 16 pins respectively with 16 other pads electricity is connected.

Description of the functionality of the MCP chip: DDR3 (L) SDRAM uses a double data rate architecture to achieve high speed operation. Double data rate this architecture is an 8n prefetch architecture whose interface is designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation of a DDR3 (L) SDRAM actually consists of a single 8 n-bit wide, four clock cycle data transfer at the internal DRAM core and eight corresponding n-bit wide, half clock cycle data transfers at the I/O pins. A differential data strobe (DQS, dqs#) is transmitted externally with the data for data capture at DDR3 (L) SDRAM input to the receiver. DQS is aligned with the data center of WRITE. The read data is transferred by DDR3 (L) SDRAM and edge aligned data strobes. DDR3 (L) SDRAM operates according to differential clocks (CK and CK#). The intersection where CK goes high and ck# goes low is referred to as the positive edge of CK. Control, command and address signals are registered at each positive edge of CK. The input data is registered on a first rising edge of DQS after the write preamble and the output data is referenced on the rising edge of DQS after the READ preamble. Read and write accesses to DDR3 (L) SDRAM are burst oriented. The access starts from the selected location and then continues for the programmed number of locations in the programming sequence. The access starts with the registration of an ACTIVATE command, followed by a READ or WRITE command. The address bit command registered in correspondence with the ACTIVATE is used to select the bank and row to be accessed. And READ or WRITE commands are used to select the bank and starting column locations for burst access. The device uses read and write BL8 and BC4. An auto-precharge function may be enabled to provide self-timed row precharge initiated at the end of a burst access. As with standard DDR SDRAM, the pipelined multi-block architecture of DDR3 (L) SDRAM allows parallel operation, providing high bandwidth by hiding row precharge and activation times. A self-refresh mode is provided as well as a power saving, power down mode.

General description: the functional and timing specifications discussed in this data table are applicable to DLL enabled modes of operation (normal operation). In the present data table, various graphics and text refer to DQ as "DQ". DQ should be construed as any and all DQ collectively unless specifically indicated otherwise. The terms "DQS" and "CK" in this data table should be interpreted as DQS, DQS# and CK, CK# unless otherwise specifically indicated. The complete functionality may be described throughout the document; any page or diagram may be reduced to conveying a topic, and may not include all requirements. Any particular claim takes precedence over a generic claim. Any functionality not explicitly stated is regarded as undefined, illegal and unsupported and may result in unknown operations. Dynamic ODT has a special use case: ODT balls may be routed HIGH when DDR3 (L) devices are designed for single rank memory arrays, instead of being routed. Please refer to the section of dynamic ODT special use case.

Optionally, the SPI NAND FLASH and SPI DDR3SDRAM are packaged side-by-side.

Optionally, the PCB substrate is rectangular, four side edges of the PCB substrate are respectively provided with 6 bonding pads, the 6 bonding pads on each edge are arranged at equal intervals, bonding pads on the upper and lower edges are symmetrically arranged, and bonding pads on the left and right edges are symmetrically arranged.

Optionally, the 6 pads on the right are respectively connected with the NAF_ALE pin, NAF_CE# pin, NAF_CLE pin, NAF_DQ pin, NAF_R/B# pin and NAF RE# pin of SPI NAND FLASH, and the 6 pads on the left are respectively connected with the DR3_ADR pin, the DR3_BA pin, the DR3_WE pin, the DR3_RAS pin and the DR3_CAS pin of the SPI DDR3 SDRAM.

Optionally, the 6 pads on the top side are respectively connected with the naf_we pin, naf_wp# pin, naf_vcc pin, naf_vss pin of SPT NAND FLASH, and the 6 pads on the bottom side are respectively connected with the DR3_reset pin, the DR3_dq pin, the DR3_cke pin, the DR3_clk pin, the DR3_cs pin, the DR3_odt pin, the DR3 DQs00 pin, and the DR3_dm00 pin of the SPI DDR3 SDRAM.

Specifically, referring to fig. 2 and 3, it can be known that the specific pins of the MCP chip have the following specific meanings:

optionally, the front surface of the PCB substrate is coated with plastic packaging glue. Therefore, the PCB substrate, the SPI NAND FLASH and the SPI DDR3SDRAM can be effectively packaged into a whole, and sealing waterproof performance is effectively guaranteed.

Optionally, referring to fig. 4, the electrical specifications to which the MCP is adapted to: absolute rating: stresses greater than those listed may cause permanent damage to the equipment. This is just a pressure level and is not implied by the operation of the functional device under any other conditions than those shown in the operational section of the specification. Long-term exposure to absolute maximum rated conditions may adversely affect reliability.

The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the invention, and all equivalent structural changes made by the description of the present invention and the accompanying drawings or direct/indirect application in other related technical fields are included in the scope of the invention.

Claims (6)

1. The MCP chip is characterized by comprising a PCB substrate, SPI NAND FLASH and SPI DDR3SDRAM packaged on the front surface of the PCB substrate, and 24 bonding pads arranged on the back surface of the PCB substrate; the SPI NAND FLASH is provided with at least 8 pins, the SPIDDR3SDRAM is provided with 16 pins, 8 pins of the SPI NAND FLASH are respectively and electrically connected with 8 bonding pads, and 16 pins of the SPI DDR3SDRAM are respectively and electrically connected with other 16 bonding pads.

2. The MCP chip of claim 1, wherein the SPI NAND FLASH and SPI DDR3SDRAM are packaged side-by-side.

3. The MCP chip of claim 1, wherein the PCB substrate is rectangular, four side edges of the PCB substrate are respectively provided with 6 pads, the 6 pads on each edge are arranged at equal intervals, pads on the upper and lower edges are symmetrically arranged, and pads on the left and right edges are symmetrically arranged.

4. The MCP chip of claim 3, wherein the 6 pads on the right are connected to the naf_ale pin, naf_ce# pin, naf_cle pin, naf_dq pin, naf_r/b# pin, naf_re# pin of SPI NAND FLASH, respectively, and the 6 pads on the left are connected to the DR3 ADR pin, the DR3 BA pin, the DR3WE pin, the DR3 RAS pin, the DR3 CAS pin, respectively.

5. The MCP chip of claim 4, wherein 6 pads on a top side are respectively connected to a NAF WE pin, a NAF wp# pin, a NAF VCC pin, a NAF VSS pin of SPI NAND FLASH, and 6 pads on a bottom side are respectively connected to a DR3RESET pin, a DR3 DQ pin, a DR3 CKE pin, a DR3 CLK pin, a DR3 CS pin, a DR3 ODT pin, a DR3 DQs00 pin, a DR3 DM00 pin of the SPIDDR3 SDRAM.

6. The MCP chip of claim 1, wherein the front side of the PCB substrate is coated with a plastic encapsulant.