CN116582973A - Control method and realization circuit for wide output current range - Google Patents

Control method and realization circuit for wide output current range Download PDF

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Publication number
CN116582973A
CN116582973A CN202310580050.0A CN202310580050A CN116582973A CN 116582973 A CN116582973 A CN 116582973A CN 202310580050 A CN202310580050 A CN 202310580050A CN 116582973 A CN116582973 A CN 116582973A
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down counter
bit digital
zero
reversible
output
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翁大丰
孙建中
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Hangzhou Oupeijie Technology Co ltd
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Hangzhou Oupeijie Technology Co ltd
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/37—Converter circuits
    • H05B45/3725—Switched mode power supply [SMPS]

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Abstract

The invention relates to the technical field of LED driving power supplies, and discloses a control method of a wide output current range, which adopts two sections to control the peak current IL of an output inductor PEAK : regulating the current reference level V REF From maximum to zero, while the blanking time during this period is a fixed maximum; when the current is at reference level V REF After zero, the current reference level V is maintained REF At zero, the blanking time is adjusted from a fixed maximum value to a minimum value to cause the output inductor peak current IL to PEAK The value is further reduced. The method also provides an implementation circuit, wherein the N-bit digital reversible up-down counter and the connected output current reference level VREF of the N-bit analog-to-digital converter DAC, the M-bit digital reversible up-down counter and the connected output analog voltage of the M-bit analog-to-digital converter DAC are used for controlling blanking time. The invention adjusts the output inductance peak current IL through two sections PEAK The values enable a wide range of current output of the drive power supply.

Description

Control method and realization circuit for wide output current range
Technical Field
The invention relates to the technical field of LED driving power supplies, in particular to a control method and an implementation circuit of a wide output current range.
Background
In LED dimming lighting applications, it is desirable that the output current Io of the LED driving power supply can vary widely to ensure a wide range of LED output light variation. Typically, for an LED driven switching power supply, its output current is determined by the time average of the output inductor current in the LED driven switching power supply. For minimum output powerFlow Io MIN When the output inductor current IL (t) in the LED driven switching power supply has entered the discontinuous mode. When outputting the minimum output current Io MIN The time average of the output inductance current IL (t) in the LED driving switch power supply is formed by the output inductance peak current IL PEAK And the output inductance repetition switching period Ts. Peak current IL for minimum output inductance PEAK Minimum output current Io MIN Inversely proportional to the output inductor repetition switching period Ts. To extend the range of variation of the output current, i.e. to reduce the output current Io MIN So that the repetition switching period Ts is further increased. In order to avoid audio noise of the LED driving power supply, the repetitive switching period Ts of the LED driving switching power supply must be less than 50us, i.e. the switching frequency must be greater than 20KHz. Obviously, to ensure that the repetitive switching period Ts of the LED driving switching power supply must be less than 50us, i.e. the switching frequency must be greater than 20KHz, and the output current Io MIN The direction of further reduction is to further reduce the minimum output inductor peak current IL PEAK The method comprises the steps of carrying out a first treatment on the surface of the But this causes problems that the minimum resolution of the current comparator, the delay response time of the current comparator and the limitation of the blanking circuit cannot be further reduced PEAK . It is therefore desirable to provide a further reduction of the output inductor peak current IL PEAK Is a viable approach to (a) is provided.
Disclosure of Invention
The invention aims to provide a control method and an implementation circuit for a wide output current range, which are used for reducing the output minimum inductance peak current IL of an LED driving power supply PEAK So that the output current Io can be varied over a wide range and so that the switching frequency can always be higher than the audio frequency.
In order to solve the above-mentioned problems, the present invention provides a wide output current range control method, which specifically includes that the time average of the output inductor current of the LED driving power supply is obtained by the peak output inductor current IL PEAK And the output inductance repeated switching period Ts is determined, and the peak current IL of the output inductance is output PEAK By adjusting the current reference level V REF In such a way that the peak inductor current IL is output PEAK Value scoreFor two-stage control: one is to adjust the current reference level V REF From maximum to zero, during which the blanking time is a fixed maximum; second, when the current is at reference level V REF After zero, the current reference level V is maintained REF At zero, the blanking time is adjusted from its fixed maximum value to its minimum value to cause the output inductor peak current IL to PEAK The value is further reduced.
As an improvement of the control method of the wide output current range of the present invention:
the current reference level V REF And the blanking time is regulated according to the output dimming current and whether the switching frequency is greater than the audio frequency or not; when the output dimming current is greater than the predetermined current, if the current reference level V REF Greater than zero, the current reference level V is reduced REF The method comprises the steps of carrying out a first treatment on the surface of the Or if the current is at reference level V REF Having been zero, then the blanking time is reduced to reduce the actual output dimming current; when the corresponding switching frequency is smaller than the audio frequency, if the current reference level V REF Greater than zero, the current reference level V is further reduced REF The method comprises the steps of carrying out a first treatment on the surface of the Or if the current is at reference level V REF Having been zero, the blanking time is further reduced to ensure that the switching frequency is greater than the audio frequency.
The invention also provides a circuit for realizing the control method of the wide output current range, which comprises the following steps:
the N-bit digital reversible up-down counter is used for outputting N-bit digital quantity and is connected with an N-bit digital quantity input end signal of the N-bit analog-to-digital converter DAC, and the M-bit digital reversible up-down counter is used for outputting M-bit digital quantity and is connected with an M-bit digital quantity input end signal of the M-bit analog-to-digital converter DAC; the DAC of the N-bit analog-to-digital converter outputs the current reference level V REF The DAC outputs analog voltage for controlling the blanking time;
the logic level UPDN is respectively connected with an up-down logic control end UPDN of the N-bit digital up-down counter and an up-down logic control end UPDN signal of the M-bit digital up-down counter; the clock signal Ck is respectively connected with the clock Ck input end of the N-bit digital reversible up-down counter and one input end of the logic AND gate, the all-zero output logic end of the N-bit digital reversible up-down counter is connected with the other input end of the logic AND gate, and the output end Ck1 of the logic AND gate is connected with the clock Ck input end of the M-bit digital reversible up-down counter; the all '1' output logic end of the M-bit digital reversible up-down counter is connected with the zero clearing setting end of the N-bit digital reversible up-down counter through a logic inverter.
As an improvement of the implementation circuit of the invention:
when the logic level UPDN is high, the current reference level V is increased along with the increase of the number of corresponding clocks Ck REF Analog quantity and blanking time analog quantity are increased; when the logic level UPDN is zero, the current reference level V increases with the number of corresponding clocks Ck REF The analog quantity and blanking time analog quantity are reduced.
As a further improvement of the implementation circuit of the invention:
when the zero clearing set end of the N-bit digital reversible up-down counter outputs high level, the current reference level V is ensured REF Reaching zero;
the N-bit digital reversible up-down counter is all zero, the all-zero output logic end outputs high level, the logic AND gate is conducted, and the clock signal Ck enters the M-bit digital reversible up-down counter through the logic AND gate.
As a further improvement of the implementation circuit of the invention:
when the M-bit digital reversible up-down counter is all 1, the all 1 output logic end is high level, and the blanking time reaches a fixed maximum value; when the M-bit digital reversible up-down counter is not all '1', the output logic end of all '1' is zero level, the output logic end is changed into high level after passing through a logic inverter, and the zero clearing setting end of the N-bit digital reversible up-down counter is input, even if a clock Ck exists, the N-bit digital reversible up-down counter is in a zero clearing state, and the N-bit reversible up-down counter carries out reversible up-down counting according to the UPDN logic level until the M-bit reversible up-down counter is all '1'.
As a further improvement of the implementation circuit of the invention:
the logic level UPDN is zero level, if N-bit digit is added reversiblyThe initial state of the down counter or the M-bit digital reversible up-down counter is all '1', the blanking time is kept at a fixed maximum time, and the current reference level V REF The self-maximum value decreases as the number of clocks Ck increases; when the number of the N-bit digital reversible up-down counter is reduced from all '1' to zero, the current reference level V REF The analog quantity is zero, and as the all-zero output logic end of the N-bit digital reversible up-down counter outputs high level, the M-bit digital reversible up-down counter has an input clock Ck1;
the corresponding logic level UPDN is still zero level, the number of the M-bit digital reversible up-down counter is reduced from all 1's to zero when the number of the Ck1 is increased, and the blanking time analog quantity reaches the minimum value; when the number of the M-bit digital reversible up-down counter is reduced from all '1', the all '1' output logic end of the M-bit reversible up-down counter outputs zero level, and the N-bit digital reversible up-down counter is continuously cleared through the logic inverter, corresponding to the output current reference level V REF The analog remains zero.
As a further improvement of the implementation circuit of the invention:
the logic level UPDN is high level, if the initial state of the N-bit digital reversible up-down counter or the M-bit digital reversible up-down counter is all '0', the blanking time is the minimum blanking time, the current reference level V REF Is also zero; the all-zero output logic end of the N-bit digital reversible up-down counter outputs high level, and the M-bit digital reversible up-down counter is provided with an input clock Ck1; increasing with the number of clocks Ck1, when the number of the M-bit digital reversible up-down counter increases from all '0' to all '1', the blanking time analog increases from the minimum value to the fixed maximum value; during the period that the analog quantity of blanking time increases from the minimum value to the fixed maximum value, the all 1 output logic end of the M-bit reversible up-down counter outputs high level, the zero clearing setting end of the N-bit digital reversible up-down counter is input to be zero level through the logic inverter, the zero clearing of the N-bit digital reversible up-down counter is finished, and the corresponding output current reference level V is output REF The analog remains zero;
the corresponding logic level UPDN remains high, for example, with a clockCk number increases, the number of N-bit digital reversible up-down counter increases from all '0' to all '1', current reference level V REF Increasing the analog quantity from zero to a maximum value; when the digital quantity of the N-bit digital reversible up-down counter is not all 0, the all-zero output logic end of the N-bit digital reversible up-down counter outputs zero level to enable the clock Ck1 of the M-bit digital reversible up-down counter to disappear, and the corresponding blanking time analog quantity is kept to be a fixed maximum time.
The beneficial effects of the invention are mainly as follows:
1. the invention adjusts the output inductance peak current IL through two sections PEAK The values enable a wide range of current output of the drive power supply so that the switching frequency can always be higher than the audio frequency.
2. The invention adjusts the output inductance peak current IL through two sections PEAK The value method, namely, the reference current level and the blanking time are controlled respectively, so that the resolution and the delay time of the current comparator can be greatly reduced; in blanking time control, the current comparator is not already involved in the peak output inductor current IL PEAK The value is controlled but entirely by the blanking time control circuit.
Drawings
The following describes the embodiments of the present invention in further detail with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of an implementation circuit of the wide output current range control method of the present invention.
Detailed Description
The invention will be further described with reference to the following specific examples, but the scope of the invention is not limited thereto:
example 1,
Typically output peak inductor current IL PEAK Is controlled by the voltage V across the current sense resistor Rs connected in series to ground through the source of the main power MOS SENSE And corresponding current reference level V REF The output inductance peak current IL is controlled by the output pulse of the current comparator when the grid voltage of the main power MOS drops to zero PEAK A kind of electronic device. When the grid voltage of the main power MOS jumps from zero voltage to high levelA burr voltage V tends to be generated in the sense resistor Rs SENSE The current comparator is triggered by mistake, and the output pulse turns off the main power MOS by mistake to output the peak inductance current IL PEAK And cannot be established. To overcome this problem, the control chip is provided with a blanking circuit with a blanking time of several hundred ns, i.e. when the gate voltage of the main power MOS jumps from zero to high, the voltage V generated on the resistor Rs is detected SENSE Adding the blanking circuit with the blanking time of hundreds of ns to the current comparator; that is, the voltage V generated on the resistor Rs is detected from when the gate voltage of the main power MOS jumps from zero voltage to high level SENSE No current comparator is added for a blanking time of hundreds of ns; until the blanking time of hundreds of ns is over, the voltage V generated on the resistor Rs is detected SENSE Is applied to the current comparator. This produces a glitch voltage V across the sense resistor Rs SENSE The current comparator will not be triggered by mistake, and the output pulse will turn off the main power MOS by mistake to make the peak current IL of the output inductance PEAK The building cannot be performed; in other words, the output inductor current is out of control in the period from the time when the gate voltage of the main power MOS jumps from zero voltage to high level to the time when the blanking time is hundreds of ns; the output inductor current at the end of the blanking time of hundreds of ns increases as the input voltage increases, and vice versa.
Typically controlling the output inductor peak current IL PEAK By adjusting the corresponding current reference level V REF To achieve this. But due to the presence of blanking circuits with blanking times of hundreds of ns, even the current reference level V REF Zero, output peak inductance current IL PEAK The value is always greater than zero and this minimum output inductor peak current IL due to the fixed blanking time of hundreds of ns PEAK The value changes with the input-output voltage.
The invention proposes to further extend the minimum output inductance peak current IL PEAK Value method, i.e. can be applied at current reference level V REF After zero, the blanking time is controlled to be reached; i.e. wide range regulation of the output inductor peak current IL PEAK The value method is divided into two sectionsControl, one is to adjust the current reference level V REF From maximum to zero, during which the blanking time is a fixed maximum; second, when the current is at reference level V REF After zero, the current reference level V is maintained REF At zero, the blanking time is adjusted from its fixed maximum value to its minimum value to cause the output inductor peak current IL to PEAK The value is further reduced.
In particular to regulate the output inductance peak current IL PEAK The values range from maximum to minimum: first by adjusting the current reference level V REF Decreasing from maximum to zero, during which the blanking time is kept at a fixed maximum; when the current is at reference level V REF After decreasing to zero, the current reference level V REF And keeping zero, and changing and adjusting the blanking time, wherein the blanking time is reduced from a fixed maximum value to a minimum value.
In particular to regulate the output inductance peak current IL PEAK Values range from minimum to maximum: first adjusting the blanking time, i.e. increasing the blanking time from its minimum value to a fixed maximum value, while the current reference level V REF Keep zero; after the blanking time reaches a fixed maximum value, the current reference level V is adjusted REF From zero to a maximum value, while the blanking time is kept at a fixed maximum value.
Current reference level V REF The blanking time can be adjusted according to the output dimming current and whether the switching frequency is larger than the audio frequency or not; when the output dimming current is greater than the predetermined current, if the current reference level V REF When the current reference level V is greater than zero, the current reference level V can be reduced REF The method comprises the steps of carrying out a first treatment on the surface of the Or if the current is at reference level V REF Having been zero, the blanking time can be reduced to reduce the actual output dimming current; when the corresponding switching frequency is smaller than the audio frequency, if the current reference level V REF When the current reference level V is greater than zero, the current reference level V can be further reduced REF The method comprises the steps of carrying out a first treatment on the surface of the Or if the current is at reference level V REF Having been zero, the blanking time can be further reduced to ensure that the switching frequency is greater than the audio frequency
Further extending the minimum output inductance peak current according to the present inventionIL PEAK The value method, i.e. the two-stage control method, can have a variety of circuit configurations. In this embodiment, a two-stage control method of an N-bit digital reversible up-down counter and an N-bit analog-to-digital converter DAC, an M-bit digital reversible up-down counter and an M-bit analog-to-digital converter DAC is adopted, and a wide output current range control circuit is shown in fig. 1.
The N-bit digital reversible up-down counter outputs N-bit digital quantity and is connected with an N-bit digital quantity input end of the N-bit analog-to-digital converter DAC, and the M-bit digital reversible up-down counter outputs M-bit digital quantity and is connected with an M-bit digital quantity input end of the M-bit analog-to-digital converter DAC; n-bit analog-to-digital converter DAC and M-bit analog-to-digital converter DAC output current reference level V REF And an analog voltage for controlling the blanking time.
The N-bit digital reversible up-down counter and the M-bit digital reversible up-down counter are respectively provided with an up-down logic control end UPDN; namely, when the UPDN is at a high level, the N-bit digital reversible up-down counter and the M-bit digital reversible up-down counter count up corresponding to the clock ck; when the UPDN is at a low level, the N-bit digital up-down counter and the M-bit digital up-down counter count down in correspondence with the clock ck.
The N-bit digital reversible up-down counter and the M-bit digital reversible up-down counter are respectively provided with respective zero clearing setting ends and are used for setting the initial states of the N-bit digital reversible up-down counter and the M-bit digital reversible up-down counter; the N-bit digital reversible up-down counter and the M-bit digital reversible up-down counter also have output logic ends of all zeros or all '1' to represent that the current counting states of the N-bit digital reversible up-down counter and the M-bit digital reversible up-down counter are all zeros or all '1'. The N-bit digital reversible up-down counter and the M-bit digital reversible up-down counter are common existing products in the market. Also N-bit analog-to-digital converter DACs and M-bit analog-to-digital converter DACs are common existing products in the market.
As shown in fig. 1, the logic level UPDN is respectively connected with an up-down logic control end UPDN of an N-bit digital up-down counter and an up-down logic control end UPDN of an M-bit digital up-down counter; the clock signal Ck is respectively connected with the clock Ck input end of the N-bit reversible up-down counter and one input end of the logic AND gate, the all-zero output logic end of the N-bit reversible up-down counter is connected with the other input end of the logic AND gate, and the output end Ck1 of the logic AND gate is connected with the clock Ck input end of the M-bit reversible up-down counter; the all '1' output logic end of the M-bit digital reversible up-down counter is connected with the zero clearing setting end of the N-bit reversible up-down counter through the output of the logic inverter.
The N-bit digital reversible up-down counter outputs analog voltage through the DAC of the N-bit analog-to-digital converter for generating current reference level V REF The method comprises the steps of carrying out a first treatment on the surface of the The M-bit digital reversible up-down counter outputs analog voltage through the DAC of the M-bit analog-to-digital converter for adjusting blanking time.
Since the N-bit digital up-down counter or the M-bit digital up-down counter requires an appropriate frequency clock Ck to perform the digital up-down; the N-bit digital reversible up-down counter or the M-bit digital reversible up-down counter is respectively provided with an up-down logic control end UPDN for respectively controlling the number quantity of the N-bit digital reversible up-down counter or the M-bit digital reversible up-down counter to be increased or decreased. The corresponding DAC is used for converting the output digital quantity of the N-bit digital reversible up-down counter into the current reference level V REF Analog quantity of (3); the corresponding M-bit analog-to-digital converter DAC is used to convert the M-bit digital up-down counter output digital quantity into an analog quantity of blanking time. Obviously, when the logic level UPDN is high, the current reference level V increases with time, i.e. the number of corresponding clocks Ck increases REF Analog quantity and blanking time analog quantity are increased; also when the logic level UPDN is zero, the current reference level V increases with time, i.e. the number of corresponding clocks Ck increases REF The analog quantity and blanking time analog quantity are reduced.
The zero clearing setting end of the N-bit digital reversible up-down counter is used for zero clearing the N-bit digital reversible up-down counter, and when the zero clearing setting end is at a high level, the current reference level V is ensured REF Reaching zero; the N-bit digital reversible up-down counter also has an all-zero output logic end, and the all-zero output logic end is high level when the N-bit digital reversible up-down counter is all-zero. All-zero output logic end control logic of N-bit digital reversible up-down counterAnd the AND gate, that is, when the N-bit digital reversible up-down counter is all zero and the all-zero output logic terminal is high level, the M-bit digital reversible up-down counter has a corresponding clock Ck1 entering the clock Ck input terminal of the M-bit digital reversible up-down counter, and the M-bit digital reversible up-down counter can perform corresponding reversible up-down counting according to the logic level UPDN.
For the M-bit digital reversible up-down counter, when the M-bit digital reversible up-down counter is all '1', the all '1' output logic end of the M-bit digital reversible up-down counter is high level, and the blanking time reaches a fixed maximum value; when the M-bit digital reversible up-down counter is not all '1', the all '1' output logic end is zero level; the all '1' output logic end of the M-bit digital reversible up-down counter is connected with the zero clearing setting end of the N-bit digital reversible up-down counter through a logic phase inverter, namely, when the M-bit digital reversible up-down counter is not all '1', the N-bit digital reversible up-down counter is in a zero clearing state even if a clock Ck exists; until the M-bit reversible up-down counter is all "1", the N-bit reversible up-down counter is not likely to perform corresponding reversible up-down counting according to the UPDN logic level.
In the circuit shown in FIG. 1, the corresponding logic level UPDN is zero, if the initial state of the N-bit digital up-down counter or the M-bit digital up-down counter is all "1", the blanking time is kept at a fixed maximum time, and the current reference level V REF From its maximum value decreases with time, i.e. with increasing number of clocks Ck. When the digital quantity of the N-bit digital reversible up-down counter is reduced from all '1's to zero, namely, the current reference level V REF The analog quantity is zero, and the M-bit digital reversible up-down counter has a corresponding clock Ck1 because the output all-zero logic level is high; the corresponding logic level UPDN remains at zero level, and the digital quantity of the M-bit digital reversible up-down counter is reduced from all ' 1's to zero over time, namely, the number of Ck 1's is increased, namely, the blanking time analog quantity reaches the minimum value. When the number of the M-bit digital reversible up-down counter is reduced from all '1', the M-bit reversible up-down counter outputs all '1' logic level to be zero level, and the N-bit digital is enabled to be available through the logic inverterContinuously clearing the up-down counter corresponding to the output current reference level V REF The analog remains zero. Likewise, the logic level UPDN is a "1" level, if the initial state of the N-bit digital up-down counter or the M-bit digital up-down counter is all "0", i.e. the blanking time is the minimum blanking time, the current reference level V REF Is also zero; the N-bit digital reversible up-down counter outputs all zero logic level as high level, and the M-bit digital reversible up-down counter has a corresponding clock Ck1; over time, i.e., as the number of clocks Ck1 increases. When the digital quantity of the M-bit digital reversible up-down counter is increased from all '0' to all '1', namely, the blanking time analog quantity is increased from the minimum value to the fixed maximum value; during the period that the analog quantity increases from the minimum value to the fixed maximum value in the blanking time, as the output all 1 logic level is high level, the zero clearing setting end of the N-bit digital reversible up-down counter is zero level through the logic inverter, the zero clearing of the N-bit digital reversible up-down counter is finished, and the output current reference level V is corresponding to the output current reference level REF The analog remains zero. The corresponding logic level UPDN remains high, i.e. the number of N-bit digital up-down counters increases from all "0" to all "1" over time, i.e. the current reference level V REF The analog quantity increases from zero to a maximum value. When the digital quantity of the N-bit digital reversible up-down counter is not all 0, the N-bit digital reversible up-down counter outputs all zero logic level to be zero level, so that the clock Ck1 of the M-bit digital reversible up-down counter disappears, and the corresponding blanking time analog quantity is kept to be a fixed maximum time.
It is apparent that the circuit shown in fig. 1 is capable of implementing the control requirements of the present invention: the logic control signal UPDN can control the current reference level V REF And increases and decreases in blanking time analog. The level of the clock Ck frequency only affects the current reference level V REF And the slope of the change in the blanking time analog. The number of bits of the N-bit digital up-down counter or the M-bit digital up-down counter only affects the reference level V REF And the varying step size of the blanking time analog. The logic control signal UPDN may be generated by loop closed-loop regulation; this closed loop tuningThe node may generate the corresponding logic control signal UPDN according to a difference between the output dimming current and the predetermined output dimming current and whether the switching frequency is greater than the audio frequency. How the logic control signal UPDN is generated is not discussed in the present invention.
Finally, it should also be noted that the above list is merely a few specific embodiments of the present invention. Obviously, the invention is not limited to the above embodiments, but many variations are possible. All modifications directly derived or suggested to one skilled in the art from the present disclosure should be considered as being within the scope of the present invention.

Claims (8)

1. Control method of wide output current range, wherein the time average of the output inductance current of the LED driving power supply is represented by the output inductance peak current IL PEAK And the output inductance repeated switching period Ts is determined, and the peak current IL of the output inductance is output PEAK By adjusting the current reference level V REF The method is characterized in that: the output inductance peak current IL PEAK The values are divided into two sections of control: one is to adjust the current reference level V REF From maximum to zero, during which the blanking time is a fixed maximum; second, when the current is at reference level V REF After zero, the current reference level V is maintained REF At zero, the blanking time is adjusted from its fixed maximum value to its minimum value to cause the output inductor peak current IL to PEAK The value is further reduced.
2. The wide output current range control method according to claim 1, characterized in that:
the current reference level V REF And the blanking time is regulated according to the output dimming current and whether the switching frequency is greater than the audio frequency or not; when the output dimming current is greater than the predetermined current, if the current reference level V REF Greater than zero, the current reference level V is reduced REF The method comprises the steps of carrying out a first treatment on the surface of the Or if the current is at reference level V REF Having been zero, then the blanking time is reduced to reduce the actual output dimming current; when the corresponding switching frequency is smaller than the audio frequency, if the currentReference level V REF Greater than zero, the current reference level V is further reduced REF The method comprises the steps of carrying out a first treatment on the surface of the Or if the current is at reference level V REF Having been zero, the blanking time is further reduced to ensure that the switching frequency is greater than the audio frequency.
3. A circuit for implementing a control method for a wide output current range according to any one of claims 1-2, characterized in that:
the N-bit digital reversible up-down counter is used for outputting N-bit digital quantity and is connected with an N-bit digital quantity input end signal of the N-bit analog-to-digital converter DAC, and the M-bit digital reversible up-down counter is used for outputting M-bit digital quantity and is connected with an M-bit digital quantity input end signal of the M-bit analog-to-digital converter DAC; the DAC of the N-bit analog-to-digital converter outputs the current reference level V REF The DAC outputs analog voltage for controlling the blanking time;
the logic level UPDN is respectively connected with an up-down logic control end UPDN of the N-bit digital up-down counter and an up-down logic control end UPDN signal of the M-bit digital up-down counter; the clock signal Ck is respectively connected with the clock Ck input end of the N-bit digital reversible up-down counter and one input end of the logic AND gate, the all-zero output logic end of the N-bit digital reversible up-down counter is connected with the other input end of the logic AND gate, and the output end Ck1 of the logic AND gate is connected with the clock Ck input end of the M-bit digital reversible up-down counter; the all '1' output logic end of the M-bit digital reversible up-down counter is connected with the zero clearing setting end of the N-bit digital reversible up-down counter through a logic inverter.
4. A circuit as claimed in claim 3, wherein:
when the logic level UPDN is high, the current reference level V is increased along with the increase of the number of corresponding clocks Ck REF Analog quantity and blanking time analog quantity are increased; when the logic level UPDN is zero, the current reference level V increases with the number of corresponding clocks Ck REF The analog quantity and blanking time analog quantity are reduced.
5. The implementation circuit of claim 4, wherein:
when the zero clearing set end of the N-bit digital reversible up-down counter outputs high level, the current reference level V is ensured REF Reaching zero;
the N-bit digital reversible up-down counter is all zero, the all-zero output logic end outputs high level, the logic AND gate is conducted, and the clock signal Ck enters the M-bit digital reversible up-down counter through the logic AND gate.
6. The implementation circuit according to claim 5, wherein:
when the M-bit digital reversible up-down counter is all 1, the all 1 output logic end is high level, and the blanking time reaches a fixed maximum value; when the M-bit digital reversible up-down counter is not all '1', the output logic end of all '1' is zero level, the output logic end is changed into high level after passing through a logic inverter, and the zero clearing setting end of the N-bit digital reversible up-down counter is input, even if a clock Ck exists, the N-bit digital reversible up-down counter is in a zero clearing state, and the N-bit reversible up-down counter carries out reversible up-down counting according to the UPDN logic level until the M-bit reversible up-down counter is all '1'.
7. The implementation circuit of claim 6, wherein:
the logic level UPDN is zero level, if the initial state of the N-bit digital reversible up-down counter or the M-bit digital reversible up-down counter is all '1', the blanking time is kept to be a fixed maximum time, and the current reference level V REF The self-maximum value decreases as the number of clocks Ck increases; when the number of the N-bit digital reversible up-down counter is reduced from all '1' to zero, the current reference level V REF The analog quantity is zero, and as the all-zero output logic end of the N-bit digital reversible up-down counter outputs high level, the M-bit digital reversible up-down counter has an input clock Ck1;
the corresponding logic level UPDN is still zero level, the number of the M-bit digital reversible up-down counter is reduced from full 1 to zero when the number of the Ck1 is increased, and the blanking time analog quantity is reachedTo a minimum value; when the number of the M-bit digital reversible up-down counter is reduced from all '1', the all '1' output logic end of the M-bit reversible up-down counter outputs zero level, and the N-bit digital reversible up-down counter is continuously cleared through the logic inverter, corresponding to the output current reference level V REF The analog remains zero.
8. The implementation circuit of claim 7, wherein:
the logic level UPDN is high level, if the initial state of the N-bit digital reversible up-down counter or the M-bit digital reversible up-down counter is all '0', the blanking time is the minimum blanking time, the current reference level V REF Is also zero; the all-zero output logic end of the N-bit digital reversible up-down counter outputs high level, and the M-bit digital reversible up-down counter is provided with an input clock Ck1; increasing with the number of clocks Ck1, when the number of the M-bit digital reversible up-down counter increases from all '0' to all '1', the blanking time analog increases from the minimum value to the fixed maximum value; during the period that the analog quantity of blanking time increases from the minimum value to the fixed maximum value, the all 1 output logic end of the M-bit reversible up-down counter outputs high level, the zero clearing setting end of the N-bit digital reversible up-down counter is input to be zero level through the logic inverter, the zero clearing of the N-bit digital reversible up-down counter is finished, and the corresponding output current reference level V is output REF The analog remains zero;
the corresponding logic level UPDN is still high level, the number of Ck is increased along with the increase of the number of the clocks, the number of the N-bit digital reversible up-down counter is increased from all '0' to all '1', and the current reference level V REF Increasing the analog quantity from zero to a maximum value; when the digital quantity of the N-bit digital reversible up-down counter is not all 0, the all-zero output logic end of the N-bit digital reversible up-down counter outputs zero level to enable the clock Ck1 of the M-bit digital reversible up-down counter to disappear, and the corresponding blanking time analog quantity is kept to be a fixed maximum time.
CN202310580050.0A 2023-05-22 2023-05-22 Control method and realization circuit for wide output current range Pending CN116582973A (en)

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