CN116579294B - Door size optimization method based on critical path - Google Patents
Door size optimization method based on critical path Download PDFInfo
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Abstract
The application relates to the technical field of electronic design automation, in particular to a gate size optimization method based on a critical path. The critical path-based gate size optimization method comprises the following steps: performing multiple rounds of iterative optimization on the design circuit to a convergence state, wherein the iterative optimization comprises the following steps: selecting a path with the longest delay of a signal in a design circuit from an input end to an output end as a key path for iterative optimization of a current round; and optimizing the size of each stage of gate on the critical path along the signal propagation direction of the critical path. The gate size optimization method based on the critical path can accurately and rapidly finish the gate size optimization of the whole circuit.
Description
Technical Field
The application relates to the technical field of electronic design automation, in particular to a gate size optimization method based on a critical path.
Background
Electronic automation design, EDA (Electronic Design Automation), refers to the design process of electronic systems such as integrated circuits, etc. by means of an electronic computer and using a series of software tools, and the main objective of the electronic automation design is to convert a high-level hardware description language into a realizable circuit design, so as to satisfy a series of constraints such as time sequence, power consumption, area, etc. on the premise of correct functions.
In the EDA process, in order to balance the performance and the power consumption of a circuit, the constraints of design such as time sequence, power consumption and area of the circuit need to be met by selecting a combination of different units, and the process of selecting the combination of different units is the process of optimizing the gate size of the circuit.
In the prior art, the size optimization problem is converted into a geometric programming (geometric programing) or convex programming (convex programing) problem through mathematical modeling and analysis to solve, but as the scale of an integrated circuit grows, the efficiency of a method for directly solving the geometric programming or convex programming also becomes lower and lower. The other method for optimizing the gate size of the circuit by using the numerical solution framework is characterized in that the number of parameters in the solution process is large, the values are greatly dependent on manual experience, the solution result and the running time are random, and the solution time is long.
Disclosure of Invention
In order to solve the defects in the prior art, the purpose of the application is to provide a critical path-based gate size optimization method for precisely optimizing a critical path of a circuit, so that the time sequence performance of the circuit is rapidly improved, and a corresponding gate size optimization result is obtained.
To achieve the above object, the present application provides a critical path-based gate size optimization method, including: performing multiple rounds of iterative optimization on the design circuit to a convergence state, wherein the iterative optimization comprises the following steps:
selecting a path with the longest delay of a signal in a design circuit from an input end to an output end as a key path for iterative optimization of a current round;
and optimizing the size of each stage of gate on the critical path along the signal propagation direction of the critical path.
Further, the step of optimizing the size of each stage of gate on the critical path along the signal propagation direction of the critical path includes:
determining the optimal size of each stage of gate from the selectable sizes of each stage of gate from top to bottom along the signal propagation direction of the critical path;
evaluating the global influence of the optimal size of the gates of each stage on the design circuit one by one from bottom to top along the signal propagation direction of the critical path, and if the optimal size of the gate of the current stage has an optimal effect on the global influence of the design circuit, applying the optimal size as the final size of the gate of the current stage; and if the optimal size of the current stage gate does not have an optimal effect on the global influence of the design circuit, applying the original size of the current stage gate.
Further, the convergence state includes:
the state of the time sequence of the critical path after the previous iteration meets the design requirement of the circuit;
the time sequence of the critical path is not lifted compared with the previous iteration;
and the state when the number of the iterative optimization turns reaches the preset maximum number of the turns.
Further, the step of determining the optimal size of each stage gate from the selectable sizes of each stage gate includes:
and respectively calculating the required time of the input end of the upper stage gate of the current stage gate when the current stage gate is under the optional size, and selecting the optional size with the largest required time as the optimal size of the current stage gate.
Further, the step of calculating the required time of the input end of the previous stage gate of the current stage gate when the current stage gate is in the selectable size includes:
selecting an optional size as the size of the current stage gate, and determining the signal inversion time of the input end of the current stage gate based on the signal inversion time of the output end of the previous stage gate;
determining the required time of the input end of the current stage gate based on the signal inversion time of the input end of the current stage gate, the required time of the output end of the current stage gate and the gate device delay of the current stage gate;
Based on the required time of the input end of the current stage gate, the required time of the output end of the previous stage gate and the load capacitance of the previous stage gate are determined through time sequence propagation in a network;
and determining the required time of the input end of the upper stage gate when the current stage gate is under the optional size based on the required time of the output end of the upper stage gate, the load capacitance of the upper stage gate and the self delay of the upper stage gate.
Further, the step of evaluating the global effect of the optimal size of the gates of each stage on the design circuit one by one includes:
and determining the total violation time change of the design circuit in response to the application of the optimal size of the current stage gate, and if the value of the total violation time becomes larger, considering that the optimal size has an optimization effect on the global influence of the design circuit, otherwise, not having the optimization effect.
Further, the step of determining a total violating time variation of the design circuit in response to the current stage gate applying the optimal size comprises:
and adding the relaxation time of each path which is negative in the design circuit to be used as the total violation time of the design circuit.
Further, the step of determining a total violating time variation of the design circuit in response to the current stage gate applying the optimal size comprises: determining a slack time of the critical path; the step of determining the slack time of the critical path comprises:
And responding to the application of the optimal size of the current stage gate, determining the required time of each stage of network step by step from the current stage gate according to the required time of the current stage gate until the critical path starts, wherein the necessary time for starting the critical path is the relaxation time of the critical path after the application of the optimal size of the current stage gate.
To achieve the above object, an electronic device provided in the present application includes:
a processor;
a memory having stored thereon one or more computer program instructions that run on the processor;
wherein the processor, when executing the computer instructions, performs a critical path based gate size optimization method as described above.
To achieve the above object, the present application provides a computer-readable storage medium having stored thereon computer instructions which, when executed by a processor, perform the steps of the critical path based gate size optimization method as described above.
According to the gate size optimization method based on the critical path, unlike a traditional solving method based on a geometric planning or convex planning form, the critical path is directly optimized, and two basic processes, namely top-down local optimization and bottom-up global evaluation, are iterated rapidly and efficiently, so that a gate size optimization scheme of an overall circuit is obtained, the problem of directly solving the geometric planning or convex planning is avoided, the solving result is not required to be rounded, and the gate size optimization of the overall circuit can be accurately and rapidly completed.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
Drawings
The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate and explain the application and do not limit it. In the drawings:
FIG. 1 is a flow chart of a critical path based gate size optimization method of the present application;
FIG. 2 is a schematic flow chart of the size optimization of the gates of the stages on the critical path;
FIG. 3 is a flow chart of calculating the required time of the input end of the upper stage gate of the current stage gate;
FIG. 4 is a schematic diagram of a timing propagation network;
FIG. 5 is a flow chart of a critical path based gate size optimization method of the present application;
FIG. 6 is a schematic diagram of an exemplary circuit;
FIG. 7 is a flow chart diagram of single gate size optimization;
FIG. 8 is a flow chart of a bottom-up global evaluation.
Detailed Description
Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present application are shown in the drawings, it is to be understood that the present application may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided to provide a more thorough and complete understanding of the present application. It should be understood that the drawings and examples of the present application are for illustrative purposes only and are not intended to limit the scope of the present application.
It should be understood that the various steps recited in the method embodiments of the present application may be performed in a different order and/or performed in parallel. Furthermore, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the present application is not limited in this respect.
The term "including" and variations thereof as used herein are intended to be open-ended, i.e., including, but not limited to. The term "based on" is based at least in part on. The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments. Related definitions of other terms will be given in the description below.
It should be noted that references to "one" or "a plurality" in this application are intended to be illustrative rather than limiting, and those of ordinary skill in the art will appreciate that "one or more" is intended to be interpreted as "one or more" unless the context clearly indicates otherwise. "plurality" is understood to mean two or more.
Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.
Example 1
An embodiment of the present application provides a critical path-based gate size optimization method, fig. 1 is a schematic flow diagram of the critical path-based gate size optimization method of the present application, and the critical path-based gate size optimization method of the present application will be described in detail below with reference to fig. 1, including:
Performing multiple rounds of iterative optimization on the design circuit to a convergence state, wherein each round of iterative optimization comprises the following steps:
step S101: selecting a path with the longest delay of a signal in a design circuit from an input end to an output end as a key path for iterative optimization of a current round;
it should be noted that, strictly speaking, the critical path is the path with the largest timing violation, and in this embodiment, since the gate size optimization method is performed after the Static Timing Analysis (STA) process in the whole EDA process, the path with the worst timing is selected as the critical path according to the analysis result of the analysis tool of the STA during each iteration optimization. Static timing analysis (static timing analysis, STA) is a relatively thorough method of analyzing, debugging and validating the timing performance of a gate level system design.
It will be appreciated that after the size of the gate device is changed, the timing of each path of the design circuit is changed, so that the critical path of the design circuit may also be changed, so that during each iteration of optimization, the critical path needs to be selected again, and the optimization of the entire design circuit is completed.
It can be understood that the convergence state is a sign of stopping the iterative optimization method, and if the design circuit is already in the convergence state, the whole critical path-based gate size optimization method is ended.
The convergence state in this embodiment includes:
the state when the time sequence of the critical path meets the design requirement of the circuit after the previous iteration;
the timing of the critical path is not lifted compared to the previous iteration;
and iterating the optimized number of rounds to reach the state when the preset maximum number of rounds is reached.
Whether the design circuit is in a convergence state can be judged after one round of iterative optimization or when a new round of iterative optimization starts.
Step S102: and optimizing the size of each stage of gate on the critical path along the signal propagation direction of the critical path.
Specifically, in one round of iterative optimization, after the critical path is determined, the critical paths are optimized in size one by one for each stage of gates along the signal propagation direction of the critical paths.
Referring to fig. 2, fig. 2 is a schematic flow chart of performing size optimization on each stage of gates on a critical path, and in this embodiment, the step of performing size optimization on each stage of gates on the critical path along a signal propagation direction of the critical path includes:
s201: determining the optimal size of each stage of gate from the selectable sizes of each stage of gate from top to bottom along the signal propagation direction of the critical path;
in this embodiment, the step of determining the optimal size of each stage gate from the selectable sizes of each stage gate includes:
And respectively calculating the required time of the input end of the upper stage gate of the current stage gate when the current stage gate is under the optional size, and selecting the optional size with the largest required time as the optimal size of the current stage gate.
I.e. the optimal size is selected by calculating the required time of the upper stage gate at the selectable size of the current stage gate.
Exemplary, e.gIn optimizing gate device G i In the time, the gate G of the preceding stage 1 ，G 2 …G i-1 Has been optimally determined so that its upper stage gate G i-1 The arrival time at the input of (a) is determined. Thus, to optimize the timing of the path, G is to be made i-1 The slack time at the input is as large as possible, and the arrival time is a fixed value at this time, and the arrival time is obtained by subtracting the arrival time from the required time, so the required time is used to select the optimal size.
Referring to fig. 3, fig. 3 is a schematic flow chart of calculating a required time of an input end of a gate of a previous stage of a current stage gate, and the specific steps include:
s2011: selecting an optional size as the size of the current stage gate, and determining the signal inversion time of the input end of the current stage gate based on the signal inversion time of the output end of the previous stage gate;
it should be noted that, before the iterative optimization starts, each gate device of the design circuit is configured with an initialized size, and the STA analysis tool is used to analyze and obtain initial circuit information, where the circuit information includes but is not limited to: slew, capacitance, resistance, delay, required time, and slice, etc. When the circuit size is changed, some circuit information is changed, and then needs to be recalculated and updated.
After the size of the previous stage gate is applied with the optional size, the size is changed relative to the original size, so that the capacitance attribute corresponding to the device itself is also changed, and the previous stage gate G is also changed i-1 In other words, its output capacitive load c i-1 And then changes, resulting in the upper stage gate G i-1 Is provided with an output end slew i-1 output Change to thereby cause G i Slew of input terminal i input And (3) a change.
Specifically, the following formula is used:
slew output of ＝Tran(slew Input device ，c)；
It can be seen that the signal slew rate (slew) of the output of the gate device is determined by the slew of the input and the load capacitance c, and the size of the gate of the previous stage is selected according to the selected sizeStage gate G i-1 For example, the slew of the input end thereof i-1 input The load capacitance c is unchanged, and the slew is recalculated according to the changed load capacitance i-1 output 。
It should be noted that, the Tran function is a table look-up process, and the characteristics of the device are recorded in the timing library file liberty.
Note that, slew i input And slew(s) i-1 output The two are complex relations in practical application, and in the earlier process, the line resistance is almost negligible, and the slew is i input Is directly equal to slew i-1 output A kind of electronic device. When the process node is further reduced, the line resistance is gradually increased, the influence of the line resistance is not negligible (the line delay is considered after the general process enters 130 nm), the relationship between the two is calculated by an equivalent model, and the models adopted under different conditions are different. In the present embodiment, the change ratio of both is approximately considered to be the same, and the slew values before and after the change are updated quickly.
S2012: determining the required time of the input end of the current stage gate based on the signal inversion time of the input end of the current stage gate, the required time of the output end of the current stage gate and the gate device delay of the current stage gate;
specifically, the following formula is adopted:
rt i input ＝rt i output -D(C ij ,slew i input ,c i )；
Wherein rt is i output When the required time of the output end of the current stage gate is the required time, the size of the subsequent stage gate is not changed after the optional size is applied to the size of the current stage gate, so that the value of the current stage gate is unchanged; d (C) ij ,slew i input ,c i ) Is the delay from the input end to the output end of the current stage gate, and is matched with the slew of the current stage gate i input And a load c i Related to the following.
S2013: based on the required time of the input end of the current stage gate, the required time of the output end of the previous stage gate and the load capacitance of the previous stage gate are determined through time sequence propagation in a network;
specifically, by timing propagation, rt is calculated i input Subtracting all line delays passing to driver from sink (receiving) end, i.e. input end of current stage gate, along the network where it is located, and finally calculating out rt of network driver (driving) end, i.e. last stage gate i-1 output 。
Referring to fig. 4, fig. 4 is a schematic structural diagram of a time-series propagation network, and as shown in fig. 4 (a), a network may be abstracted into n sink ends and a driver end. One sink end is the current stage gate G i Is the timing of rt i input Changes occur while the rt of the other sink ends remain the original timing. The specific propagation process is divided into two cases, one of which propagates along a line, and as shown in fig. 4 (b), the parameter set at node a is (ti, ci), t is the required time at a, and c is the load capacitance of a. The line model can be equivalently an RC model, a resistance value R and a capacitance value C, and when the line Delay reaches the node B, parameters (ti ', ci') at the B can be simply estimated according to an Elmore Delay model: ti' =ti-RC/2-Rci; ci' =ci+c. Second, as shown in fig. 4 (c), if the parameters set at the branch 1 are (t 1, c 1) and the parameters at the branch 2 are (t 2, c 2), the solution after merging can be expressed as t=min (t 1, t 2), and c=c1+c2. I.e. the addition of the capacitances, the time takes a more stringent branch. By the above method, the required time of the sink end can be transmitted to the driver along the network, and G can be completed i-1 And updating the required time at the output end.
S2014: and determining the required time of the input end of the upper stage gate when the current stage gate is under the optional size based on the required time of the output end of the upper stage gate, the load capacitance of the upper stage gate and the self delay of the upper stage gate.
Specifically, the required time of the input end of the upper stage gate is equal to the required time of the output end of the upper stage gate minus the delay of the upper stage gate, and the formula is as follows:
rt i-1 input ＝rt i-1 output -D(C i-1 ,slew i-1 input ,c i-1 )；
Wherein rt is i-1 output To get up toThe required time of the output end of the first-stage gate; d (C) i-1 ,slew i-1 input ,c i-1 ) For the delay of the upper stage gate, the slew is the slew of the upper stage gate i-1 input Unchanged, c calculated from propagation within the network i-1 The delay of the upper stage gate is obtained, and then the required time of the input end of the upper stage gate is determined.
S202: evaluating the global influence of the optimal size of the gates of each stage on the design circuit one by one from bottom to top along the signal propagation direction of the critical path, and if the optimal size of the gate of the current stage has an optimal effect on the global influence of the design circuit, applying the optimal size as the final size of the gate of the current stage; and if the optimal size of the current stage gate does not have an optimal effect on the global influence of the design circuit, applying the original size of the current stage gate.
In this embodiment, the step of evaluating the global effect of the optimal size of the gates of each stage on the design circuit one by one includes:
and determining the total violation time change of the design circuit in response to the application of the optimal size of the current stage gate, and if the value of the total violation time becomes larger, considering that the optimal size has an optimization effect on the global influence of the design circuit, otherwise, not having the optimization effect.
In this embodiment, considering that the optimization process is itself an optimal size obtained by solving for the critical path, the optimal size is first to ensure the local optimal characteristic, if the optimal size can increase the total violation time TNS value, it is explained that it also optimizes the global of the circuit, the optimal size is applied, and the slew and required time changes calculated by the evaluation process are updated into the circuit to ensure G i Correctness of circuit time sequence after size change; if this dimensional change would result in a deterioration of the global characteristics of the circuit, then the dimensional change is not applied.
In this embodiment, the relaxation time of each path that is negative in the design circuit is added as the total violation time of the design circuit.
In this embodiment, the step of determining the total violating time variation of the design circuit in response to the current stage gate applying the optimal size comprises:
determining a slack time of the critical path;
the step of determining the slack time of the critical path comprises:
and responding to the application of the optimal size of the current stage gate, determining the required time of each stage of network step by step from the current stage gate according to the required time of the current stage gate until the critical path starts, wherein the necessary time for starting the critical path is the relaxation time of the critical path after the application of the optimal size of the current stage gate.
Specifically, the current stage gate G is first collected i The network where the input end and the output end are located calculates the slew changes of the driver end and the sink end in the network, and the slew changes can be rapidly attenuated along with the increase of the series, so that the summary in the embodiment only needs to calculate G i The effect of the network in which the input and output are located.
Then calculate the required time change of each network step by step forward: from the current stage gate G i And (3) transmitting the required time of the input end to the driver end along the network, subtracting the delay of the gate device of the driver end to obtain the required time of the input end of the gate of the upper stage, and repeating the process until the start of the path. Thereby obtaining G i The dimensional change at this point has an effect on the circuit as a whole, i.e. the required time at the beginning of the path is equal in value to the slot time of the path.
It should be noted that, whether the size change is applied or not, the next step of optimization is performed, that is, if the optimal size is not applied, the next stage gate device on the current critical path is directly inspected, and the size optimization and evaluation are performed; and if the end of the path is reached, re-selecting the critical path to perform a new round of iterative optimization.
Example 2
An embodiment of the present application provides a critical path-based gate size optimization method, and fig. 5 is a schematic flow chart of the critical path-based gate size optimization method of the present application, and the critical path-based gate size optimization method of the present application will be described in detail below with reference to fig. 5:
in this embodiment, an iterative optimization method is used, a critical path of a current design circuit is selected in each iteration, the gate size is locally optimized from top to bottom (along the signal propagation direction) along the critical path, then the optimized gate size is globally evaluated from bottom to top (against the signal propagation direction), and finally the optimization of the whole design circuit is completed, as shown in fig. 5, the whole method comprises the following procedures:
a critical path of the entire design circuit is selected (S11).
In this embodiment, the critical path refers to a path (strictly speaking, a path with the largest timing violation) through which a signal passes from an input to an output with the longest delay.
In this embodiment, since the gate size optimization method is performed after a Static Timing Analysis (STA) process in the whole EDA process, only the path with the worst timing is selected according to the analysis result of the STA analysis tool during each iteration optimization.
Static timing analysis (static timing analysis, STA) is a relatively thorough method of analyzing, debugging and validating the timing performance of a gate level system design.
It will be appreciated that the timing of the paths of the design circuit will change as the gate device size changes, and thus the critical path of the design circuit may also change, so that it will need to be re-selected during each iteration.
After determining the critical path, it may be determined whether the current circuit has converged according to its timing indicator relaxation time (slot time) (S12).
Specifically, there are three general cases in which it can be judged that the circuit has converged: 1) The timing of the critical path has met the design requirements of the design circuit; 2) The time sequence of the current critical path is hardly improved compared with the time sequence of the last iterative optimization; 3) The number of iterative optimisation reaches a preset maximum number. If the circuit has converged, the whole critical path-based gate size optimization method ends.
After determining the critical path, if the timing sequence of the critical path has not converged, gate size optimization is needed to be implemented on the path, namely, the gate sizes are optimized one by one from top to bottom along the signal propagation direction (S13), and then the global influence of the optimization scheme on the circuit is evaluated from bottom to top (S14), so that a practical and feasible optimization scheme is determined until the whole path is optimized (S15).
For example, referring to fig. 6, fig. 6 is a schematic diagram of an exemplary circuit, such as the design circuit of fig. 6 (a), where the critical path starts with W1 and ends with G4 (the thickened portion in the figure). W1-W4 on the path are connecting lines, and G1-G4 are gate devices to be optimized. The gate size optimization process starts from G1, steps (S13) and (S14) are performed on the gate devices one by one until G4, and the optimization of the current round critical path of the circuit is completed.
It can be understood that the main parts of the whole iterative optimization method are steps (S13) and (S14), and are two core sub-processes of the method. The details of (S13) and (S14) will be highlighted below.
In the present embodiment, (S13) and (S14) relate to the following basic principles and theoretical basis:
slack_time＝required_time-arrival_time (1)
in the formula (1), the slack time (short for slack) is equal to the difference between the required time and the arrival time (arrival time). The index is used for measuring the time sequence quality of the path, and when the slot is more than or equal to 0, the index indicates that the circuit meets the time sequence requirement; while a slot less than 0 indicates a timing violation.
slew Output of ＝Tran(slew Input device ，c) (2)
In equation (2), the signal slew rate (slew) at the output of the device is determined by the slew at the input and the load capacitance c.
The Tran function here is a look-up procedure, and the characteristics of the device are recorded in the timing library file liberty.
delay(pin Input device ，pin Output of )＝D(C，slew Input device ，c) (3)
In the formula (3), the delay between the input pin and the output pin corresponding to a certain gate device type C is determined by the slew of the input terminal and the load capacitance C of the output terminal.
In contrast to the basic principle described above, step S13 is described with reference to fig. 7, and fig. 7 is a schematic flow chart of single gate size optimization.
The gate devices on the critical path can be arranged to be G from top to bottom in sequence 1 ,G 2 …G n . The direction of the door size optimization is from G 1 Starting to G n And (5) ending.
Without loss of generality, assume that the gate device currently being optimized is G i G is then 1 ，G 2 …G i-1 G after the size optimization is completed i+1 …G n To be sized (refer to fig. 6 (b), for example, the devices being optimized in the figure are G3, G1 and G2 have been optimized and sized, G4 to be sized).
If G i The optional gate size set is { C i1 ,C i2 …C im And (S21), only one attempt is needed to try the different gate sizes one by one, and the optimal gate size is selected.
For a certain selected dimension C ij (S22) our goal is to calculate the previous level G i-1 The required time (i.e., the required time) of the input is evaluated for the merits of the size scheme. Because the gate device G is optimized i When G 1 ，G 2 …G i-1 Has been determined, G i-1 The arrival time (i.e., arrival time) at the input is determined. To optimize the timing of the path, G is to be made according to equation (1) i-1 The slot time at the input is as large as possible, while the arrival time is a fixed value, so only the required time needs to be maximized.
Calculation G i Signal inversion time slew of input terminal i input (S23): when G i When the size of the device changes, the capacitance attribute corresponding to the device changes. For the upper stage G i-1 In other words, its output capacitive load c i-1 And also changes, resulting in G i-1 Is provided with an output end slew i-1 output The change (which can be calculated from equation (2)) in turn causes G i Slew of input terminal i input Variation (see fig. 6 (c)), the G3 different gate size devices have differentWhen the size of the capacitor value changes, the load capacitor value corresponding to the output end Pin2_O1 of the previous stage G2 also changes, and finally, the slew value of the input end Pin3_I1 of the G3 changes;
it should be noted that slew i input And slew(s) i-1 output The two are complex relations in practical application, and in the earlier process, the line resistance is almost negligible, and the slew is i input Is directly equal to slew i-1 output A kind of electronic device. When the process node is further reduced, the line resistance is gradually increased, the influence of the line resistance is not negligible (the line delay is considered after the general process enters 130 nm), the relationship between the two is calculated by an equivalent model, and the models adopted under different conditions are different. There are two ways in the actual processing, one is obtained from the STA, and the value obtained in this way is more accurate but the speed is slower; another approach approximates the agreement of the ratio of changes between them, thereby rapidly updating the slew values before and after the change.
In this embodiment, the basic information of the design circuit is obtained from STA, and STA needs to have the basic data including the resistance R, equivalent constant c and slew on the input/output pins of each device in the process of completing the timing analysis. At circuit initiation, the values of R, c and slew for all nodes of the circuit are from STA and gate size optimization requires recalculation of changes in R, c and slew for the relevant node and updating of the values after changing device sizes.
Calculation G i The required time of the input is denoted as rt i input (S24): by G i Load capacitance c of output terminal i And the updated slew of the previous step i input Substituting the value into formula (3) to obtain the gate device delay D (C) under the size ij ,slew i input ,c i ). Due to G i The dimensions of the gate devices have not changed, so G i The required time at the output (denoted as rt i output ) And a load capacitance c i All have no change and can be directly obtained from the time sequence analysis result of the STA, G i The required time of the input may be updated to rt i input ＝rt i output -D(C ij ,slew i input ,c i ) As shown in G3 in fig. 6 (d);
calculation G i-1 The required time at the output is denoted as rt i-1 output (S25)：G i The input terminal pin is one of the network (net) receiving terminals (sink) where the input terminal pin is located, and the driving terminal (driver) of the network is G i-1 And an output terminal. The required time of the sink end is transmitted to the driver along the network, thus completing the G i-1 And updating the required time at the output end.
The propagation here refers to the propagation of time sequences, more precisely, to the propagation of rt i input Starting from a sink end along a network, subtracting all line delays passing to a driver end, and finally calculating the rt of the driver end i-1 output For example, as shown in FIG. 4 (a), a network can be abstracted into n sink ends and a driver end, wherein one sink end is G i An input terminal with a timing of rt i input Changed, and the rt of other sink ends is still the original time sequence, we need to calculate rt i input The effect of the change in (c) on driver side).
The specific propagation process is divided into two cases, one of which propagates along a line, as shown in fig. 4 (b). The parameter set at node A is (ti, ci), t is the required time at A, and c is the load capacitance of A. The line model can be equivalently an RC model, a resistance value R and a capacitance value C, and when the line Delay reaches the node B, parameters (ti ', ci') at the B can be simply estimated according to an Elmore Delay model: ti' =ti-RC/2-Rci; ci' =ci+c. And two, branch merging, as shown in fig. 4 (c). Let the parameter at branch 1 be (t 1, c 1) and the parameter at branch 2 be (t 2, c 2), the combined solution can be expressed as t=min (t 1, t 2), c=c1+c2. I.e. the addition of the capacitances, the time takes a more stringent branch. In this way, the required time of the sink end can be transmitted to the driver along the network, and G can be completed i-1 And updating the required time at the output end.
Calculation G i-1 The required time of the input is denoted as rt i-1 input (S26): after the propagation in the network of the last step, G is calculated i-1 Output end updated rt i-1 output And a load capacitance c i-1 (propagation within the network calculates these two values), the delay of the gate device itself can be obtained according to equation (3), and rt can be obtained i-1 input ＝rt i-1 output -D(C i-1 ,slew i-1 input ,c i-1 )。
As above, the rt corresponding to different sizes is calculated one by one i-1 input Value (S27), select rt i-1 input Maximum corresponding device dimension C ij Namely G i The corresponding optimal size (S28).
Next for the optimal dimension C ij A bottom-up global evaluation is made (S14). If the size has a time sequence optimizing effect on the global circuit, determining to apply the size and updating the time sequence of the circuit; otherwise, the original size is kept unchanged.
In this embodiment, to evaluate whether the selected size has an optimal effect on the timing of the global circuit, a global evaluation index total violation time (Total Negative Slack, TNS) is used. The timing result of each path can be characterized by a slot time throughout the design circuit. The negative slack indicates that this path timing violations. The sum of the timings of all negative slack paths is TNS, so TNS is a negative value, preferably tns=0, indicating that all paths of the overall design meet timing requirements. To calculate the value of TNS, the corresponding slack for each path needs to be known. By back propagation, the required time at the start of the path is determined, and the delay of the path is subtracted step by step to the start of the path to obtain the slot value (the required time at the start of the path calculated by the method is equal to the slot time in value).
The delay of the path depends on the change in slew (see equation (3)), so the main step of global evaluation is spread around the updates of slew and required time.
Global evaluation process referring to fig. 8, fig. 8 is a schematic flow diagram of a bottom-up global evaluation, as shown in fig. 8, and the specific flow includes:
collection G i Calculating the slew changes of a driver end and a sink end in a network where the input and output pins are located (S31), wherein the slew changes are calculatedThe rapid decay with increasing number of stages, so that only G needs to be calculated i Before and after-the network in which the inputs and outputs reside. Illustratively, taking the design circuit of fig. 6 (e) as an example, the input Pin of G3 has two pins Pin1 and Pin2, and the corresponding networks are net1 and net2. Net1 is composed of a net W6, a driver end Pin4 and a sink end Pin1, and net2 is composed of nets W3 and W5, a driver end Pin5 and sink ends Pin2 and Pin 6. The input Pin of G3 has a Pin3, and the corresponding network is net3. Wherein net3 is composed of net W4 and driver end Pin3 and sink end Pin 7. Only the slew changes of all pins involved in these previous and subsequent level networks need to be calculated. The basic principle of the calculation is formula (2), and the calculation method is the same as the step 1) of the flow S13 (namely S23);
progressively calculating the required time change of each network (S32-S38): from G i At first, the required time of the input pin is propagated to the driver end along the network (S34), and the delay of the gate device is subtracted to obtain the required time at the input pin of the previous stage (S35), and the calculation method is the same as steps 3) and 4) of the process S13 (i.e. S25 and S26). This process is repeated until the start of the path. As shown in fig. 6 (f), after the optimal size of G3 is obtained, two pins are provided at the input end, and the two pins need to be propagated to the previous stage. Taking the propagation process of Pin2 as an example, firstly finding out the network Net2 where the Pin2 is located, and propagating the required time of the sink end (Pin 2, pin 6) of the net2 to the driver end (Pin 5) along the network to obtain rt2 Output of Subtracting the delay of the device G2 to obtain the required time (rt 2) of the input end of the G2 Input device ). The required time is transmitted from the input end of G3 to the input end of the previous stage G2, and the process is repeated until the path starts, thereby completing the calculation of the required time of each stage of network and further obtaining G i The dimensional change at this point has an effect on the circuit as a whole, i.e. the required time at the beginning of the path is equal in value to the slot time of the path.
Evaluate whether accept G i Dimension change of (C) ij (S39). In the last step, G is obtained i The effect of dimensional changes on the circuit as a whole, including capacitance, slew and required time, and on themThe values are updated.
In the present embodiment, the optimal size ensures locally optimal characteristics, considering that the optimization process itself is an optimal size obtained by solving for the critical path. If the optimal size causes the TNS value to also increase, indicating that it also has an optimization effect on the global of the circuit, the size is applied and the slew and required time changes calculated by the evaluation process are updated into the circuit to ensure G i Correctness of circuit time sequence after size change; if the dimensional change causes deterioration of the global characteristics of the circuit, the dimensional change is not applied (S39 to S3A).
As above, the optimum size C of a gate of a certain stage in the design circuit ij Sub-flow of bottom-up global evaluation.
It should be noted that whether or not the dimensional change is applied, the next optimization, i.e., steps S14 and S15, will be entered. If the optimal size is not applied, directly inspecting the next stage gate device on the current critical path, and performing size optimization and evaluation on the next stage gate device; and if the end of the path is reached, re-selecting the critical path to perform a new round of iterative optimization.
Example 3
In this embodiment, an electronic device is further provided, including a processor and a memory. The memory is used to store non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor is configured to execute non-transitory computer readable instructions that, when executed by the processor, may perform one or more steps of the method of testing a switch chip described above. The memory and processor may be interconnected by a bus system and/or other forms of connection mechanisms (not shown).
For example, the processor may be a Central Processing Unit (CPU), a Digital Signal Processor (DSP), or other form of processing unit having data processing and/or program execution capabilities, such as a Field Programmable Gate Array (FPGA), or the like; for example, the Central Processing Unit (CPU) may be an X86 or ARM architecture, or the like.
For example, the memory may comprise any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. Volatile memory can include, for example, random Access Memory (RAM) and/or cache memory (cache) and the like. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, and the like. One or more computer program modules may be stored on the computer readable storage medium and executed by the processor to perform various functions of the electronic device. Various applications and various data, as well as various data used and/or generated by the applications, etc., may also be stored in the computer readable storage medium.
It should be noted that, in the embodiments of the present application, specific functions and technical effects of the electronic device may refer to the description of the testing method of the switch chip, which is not repeated herein.
Example 4
In this embodiment, there is also provided a computer-readable storage medium for storing non-transitory computer-readable instructions. For example, non-transitory computer readable instructions, when executed by a computer, may perform one or more steps of a test method according to the switch chip described above.
For example, the storage medium may be applied to the above-described electronic device. For example, the storage medium may be a memory in an electronic device. For example, the relevant description of the storage medium may refer to a corresponding description of a memory in an electronic device, which is not repeated here.
The storage medium (computer readable medium) described above in the present application may be a computer readable signal medium or a non-transitory computer readable storage medium, or any combination of the two. The non-transitory computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the non-transitory computer readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
In the context of this application, a non-transitory computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present application, however, a computer-readable signal medium may include a data signal that propagates in baseband or as part of a carrier wave, with the computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a non-transitory computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, fiber optic cables, RF (radio frequency), or the like, or any suitable combination of the foregoing.
The computer readable medium may be contained in the electronic device; or may exist alone without being incorporated into the electronic device.
Computer program code for carrying out operations of the present application may be written in one or more programming languages, including, but not limited to, an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The units involved in the embodiments of the present application may be implemented by software, or may be implemented by hardware. Wherein the names of the units do not constitute a limitation of the units themselves in some cases.
The functions described above herein may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), an Application Specific Standard Product (ASSP), a system on a chip (SOC), a Complex Programmable Logic Device (CPLD), etc.
The above description is only illustrative of some of the embodiments of the present application and of the principles of the technology employed. It will be appreciated by persons skilled in the art that the scope of the disclosure referred to in this application is not limited to the specific combinations of features described above, but it is intended to cover other embodiments in which any combination of features described above or equivalents thereof is possible without departing from the spirit of the disclosure. Such as the above-described features and technical features having similar functions (but not limited to) disclosed in the present application are replaced with each other.
Moreover, although operations are depicted in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order. In certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the present application. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination.
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are example forms of implementing the claims.
Claims (8)
1. A critical path based gate size optimization method comprising:
performing multiple rounds of iterative optimization on the design circuit to a convergence state, wherein the iterative optimization comprises the following steps:
Selecting a path with the longest delay of a signal in a design circuit from an input end to an output end as a key path for iterative optimization of a current round;
performing size optimization on each stage of gate on the critical path along the signal propagation direction of the critical path;
the step of optimizing the size of each stage of gate on the critical path along the signal propagation direction of the critical path comprises the following steps:
determining the optimal size of each stage of gate from the selectable sizes of each stage of gate from top to bottom along the signal propagation direction of the critical path;
evaluating the global influence of the optimal size of the gates of each stage on the design circuit one by one from bottom to top along the signal propagation direction of the critical path, and if the optimal size of the gate of the current stage has an optimal effect on the global influence of the design circuit, applying the optimal size as the final size of the gate of the current stage;
if the optimal size of the current stage gate does not have an optimization effect on the global influence of the design circuit, the original size of the current stage gate is applied;
the step of determining the optimal size of each stage gate from the selectable sizes of each stage gate comprises:
and respectively calculating the required time of the input end of the upper stage gate of the current stage gate when the current stage gate is under the optional size, and selecting the optional size with the largest required time as the optimal size of the current stage gate.
2. The critical path based gate size optimization method of claim 1, wherein the convergence state comprises:
the state of the time sequence of the critical path after the previous iteration meets the design requirement of the circuit;
the time sequence of the critical path is not lifted compared with the previous iteration; and the state when the number of the iterative optimization turns reaches the preset maximum number of the turns.
3. The critical path based gate size optimization method as claimed in claim 1, wherein the step of calculating the required time of the input terminal of the previous stage gate of the current stage gate when the current stage gate is at the selectable size, respectively, comprises:
selecting an optional size as the size of the current stage gate, and determining the signal inversion time of the input end of the current stage gate based on the signal inversion time of the output end of the previous stage gate;
determining the required time of the input end of the current stage gate based on the signal inversion time of the input end of the current stage gate, the required time of the output end of the current stage gate and the gate device delay of the current stage gate;
based on the required time of the input end of the current stage gate, determining the required time of the output end of the previous stage gate and the load capacitance of the previous stage gate through time sequence propagation in a network;
And determining the required time of the input end of the upper stage gate when the current stage gate is under the optional size based on the required time of the output end of the upper stage gate, the load capacitance of the upper stage gate and the self delay of the upper stage gate.
4. The critical path based gate size optimization method of claim 1, wherein the step of evaluating the global impact of the optimal size of the gates of each stage on the design circuit one by one comprises:
and determining the total violation time change of the design circuit in response to the application of the optimal size of the current stage gate, and if the value of the total violation time becomes larger, considering that the optimal size has an optimization effect on the global influence of the design circuit, otherwise, not having the optimization effect.
5. The critical path based gate size optimization method as claimed in claim 4, wherein said step of determining a total violating time variation of a design circuit in response to a current stage gate applying said optimal size comprises:
and adding the relaxation time of each path which is negative in the design circuit to be used as the total violation time of the design circuit.
6. The critical path based gate size optimization method of claim 5 wherein said step of determining a total violating time variation of a design circuit in response to a current stage gate applying said optimal size comprises:
Determining a slack time of the critical path; the step of determining the slack time of the critical path comprises:
and responding to the application of the optimal size of the current stage gate, determining the required time of each stage of network step by step from the current stage gate according to the required time of the current stage gate until the critical path starts, wherein the required time of the start of the critical path is the relaxation time of the critical path after the application of the optimal size of the current stage gate.
7. An electronic device, comprising: a processor; a memory having stored thereon one or more computer program instructions that run on the processor; wherein the processor, when executing the computer program instructions, performs the critical path based gate size optimization method of any of claims 1-6.
8. A computer readable storage medium having stored thereon computer instructions which, when executed by a processor, perform the steps of the critical path based gate size optimization method of any of claims 1-6.
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| US5751593A (en) * | 1996-04-10 | 1998-05-12 | Motorola, Inc. | Accurate delay prediction based on multi-model analysis |
| CN113673195A (en) * | 2021-10-25 | 2021-11-19 | 南京集成电路设计服务产业创新中心有限公司 | Circuit gate size optimization method based on network topology sequence |
| CN114021515A (en) * | 2021-10-27 | 2022-02-08 | 中国科学院计算技术研究所 | Front-end process migration optimization method and system of digital integrated circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5751593A (en) * | 1996-04-10 | 1998-05-12 | Motorola, Inc. | Accurate delay prediction based on multi-model analysis |
| CN113673195A (en) * | 2021-10-25 | 2021-11-19 | 南京集成电路设计服务产业创新中心有限公司 | Circuit gate size optimization method based on network topology sequence |
| CN114021515A (en) * | 2021-10-27 | 2022-02-08 | 中国科学院计算技术研究所 | Front-end process migration optimization method and system of digital integrated circuit |
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