CN116578484A - Verification method, system, equipment and storage medium for design device to be verified - Google Patents
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Abstract
The application discloses a verification method, a system, equipment and a storage medium of a design device to be verified, which are applied to the technical field of testing and comprise the following steps: respectively configuring N verification tasks for N working modes of the DUT, wherein random delay is configured for each verification task; placing N verification tasks into a first queue; selecting 1 verification task from the first queue; determining the accumulated sub-value i of the currently selected verification task selected from the first queue, and transmitting the ith step of the accumulated sub-value i to the DUT; after the DUT finishes executing the step, after the random time delay of the verification task, the verification task is put back into the first queue, and the operation of selecting 1 verification task from the first queue is returned to be executed until each step of each verification task is executed by the DUT; and determining the verification result of the DUT. By applying the scheme of the application, the verification of the DUT can be effectively realized, the verification efficiency is improved, and errors can be avoided.
Description
Technical Field
The present application relates to the field of testing technologies, and in particular, to a method, a system, an apparatus, and a storage medium for verifying a design device to be verified.
Background
When the DUT (Design Under Test) supports multiple modes of operation, the DUT's processing and response to each mode of operation are independent of each other and operate in only one mode at a time, i.e., requiring no interference between the operating steps of the different modes.
Therefore, in order to perform functional verification of the DUT, external stimulus is required to randomly input steps of each mode to the DUT. Currently, in actual DUT function verification, the individual steps of the individual patterns are written by the staff and are randomly disturbed. Because the staff is required to randomly disturb each step of each mode, the code writing process is easy to make mistakes, and the time consumption of the code writing process is long. Taking 2 modes as examples, for example, when testing mode a of the DUT, the code content to be sent to the DUT includes step 1, step 2 and step 3, and when testing mode B of the DUT, the code content to be sent to the DUT includes step 4, step 5 and step 6, for example, in a case that a worker writes codes manually and randomly scrambles the steps, the written code content is: step 1-step 4-step 2-step 6-step 5, where a code writing error at 2 occurs, one is missing step 3 of pattern A, and the other is step 6 of pattern B prior to step 5. In addition, in practical application, because the manual code writing process takes longer time, the multi-pass DUT function verification is not facilitated, the multi-mode independent working test of the DUT is insufficient, the coverage rate of the manual random disturbing operation step is low, and the hidden problem in the DUT is difficult to find.
In summary, how to effectively implement the verification of the DUT, improve the verification efficiency and avoid the error is a technical problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a verification method, a verification system, verification equipment and a storage medium of a design device to be verified, so as to effectively realize verification of a DUT, improve verification efficiency and avoid errors.
In order to solve the technical problems, the invention provides the following technical scheme:
a verification method of a design device to be verified comprises the following steps:
respectively configuring corresponding N verification tasks for N working modes of a design device to be verified, and configuring 1 random delay for each verification task; n is a positive integer and N is more than or equal to 2;
placing N verification tasks into a preset first-in first-out first queue;
selecting 1 verification task from the first queue when at least 1 verification task exists in the first queue;
for the verification task currently selected, determining an accumulated sub-value i selected from the first queue by the verification task in the verification process, and sending an i-th step of the verification task to the design device to be verified so as to enable the design device to be verified to execute;
After the design device to be verified finishes executing the received steps, the verification task is put back into the first queue after the random delay of the verification task which is currently selected, and after the design device to be verified finishes executing the received steps, the operation of selecting 1 verification task from the first queue is returned to be executed until each step of each verification task is executed by the design device to be verified;
and determining the verification result of the design device to be verified.
In one embodiment, the placing the N verification tasks into a preset first-in-first-out first queue includes:
placing N verification tasks into a preset first-in first-out first queue;
the N verification tasks start timing of random time delay of the N verification tasks at the same time, and for any 1 verification task in the N verification tasks, after the random time delay configured for the verification task is passed, the verification task is placed into a preset first-in first-out first queue.
In one embodiment, the placing the N verification tasks into a preset first-in-first-out first queue includes:
And placing N verification tasks into a preset first-in first-out first queue in sequence according to the sequence of the task numbers from small to large or from large to small.
In one embodiment, the determining the verification result of the design device to be verified includes:
when the verification results of the N working modes of the design device to be verified are all passed, determining that the verification results of the design device to be verified are passed;
and when the verification result of at least 1 working mode in the N working modes of the design device to be verified fails, determining that the verification result of the design device to be verified fails.
In one embodiment, respectively configuring corresponding N verification tasks for N working modes of a design device to be verified, and configuring 1 random delay for each verification task, including:
respectively configuring corresponding N verification tasks for N working modes of a design device to be verified through a first language, and configuring 1 random delay for each verification task;
placing the N verification tasks into a preset first queue of first-in first-out, including:
initiating N threads through the first language to respectively schedule N verification tasks, and placing the N verification tasks into a preset first-in first-out first queue.
In one embodiment, selecting 1 of the validation tasks from the first queue includes:
establishing communication among N threads through the first language, and setting a first key;
and 1 verification task is selected from the head of the first queue, and the thread corresponding to the verification task acquires the first key so as to allow the thread to send the ith step of the verification task to the design device to be verified.
In one embodiment, the method further comprises:
when detecting that 2 or more verification tasks need to be put into the first queue at the same time, triggering a set conflict resolution mechanism to enable each verification task with conflict to be put into the first queue successively.
In one embodiment, when detecting that 2 or more verification tasks need to be placed in the first queue at the same time, triggering a set conflict resolution mechanism to enable each verification task with a conflict to be placed in the first queue successively, including:
when detecting that 2 or more verification tasks need to be put into the first queue at the same time, triggering a set conflict resolution mechanism, so that each verification task which generates conflict restarts the timing of the random delay of the verification task, and putting the verification task into the first queue after the random delay of the verification task.
In one embodiment, the method further comprises:
each time after determining that the verification result of the design device to be verified is passed, verifying the design device to be verified again until the turn of verifying the design device to be verified reaches a set turn threshold;
and each time the design device to be verified is verified again, randomly updating the random delay of each verification task.
A verification system for a design device to be verified, comprising:
the verification task random delay distribution module is used for respectively configuring N corresponding verification tasks for N working modes of the design device to be verified, and configuring 1 random delay for each verification task; n is a positive integer and N is more than or equal to 2;
the initial queue placement module is used for placing N verification tasks into a preset first-in first-out first queue;
the verification task selection module is used for selecting 1 verification task from the first queue when at least 1 verification task exists in the first queue;
the sending module is used for determining an accumulated sub-value i selected from the first queue by the verification task in the verification process, and sending an ith step of the verification task to the design device to be verified so as to enable the design device to be verified to execute;
The verification task replacement module is used for replacing the verification task into the first queue after the random delay of the verification task currently selected after the received step is executed by the design device to be verified, and returning to trigger the verification task selection module after the received step is executed by the design device to be verified until all the steps of the verification task are executed by the design device to be verified;
and the verification result determining module is used for determining the verification result of the design device to be verified.
A verification apparatus of a design device to be verified, comprising:
a memory for storing a computer program;
a processor for executing the computer program to implement the steps of the verification method of the design device to be verified as described above.
A computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the verification method of a design device to be verified as described above.
By applying the technical scheme provided by the embodiment of the application, the verification of the design device to be verified can be automatically performed, the execution efficiency is high, and errors are not easy to occur. In the scheme of the application, corresponding N verification tasks are respectively configured for N working modes of the design device to be verified, and it can be seen that the random crossing of the steps under different verification tasks is not performed at this time, namely the configured N verification tasks are independent and complete, so that errors are not easy to occur. In order to achieve random crossing of steps under different verification tasks, the scheme of the application is not disturbed by manpower as in the traditional scheme, but is configured with 1 random delay for each verification task, and the random crossing of the steps under different verification tasks is achieved through the random delay. After 1 random delay is configured for each verification task, N verification tasks may be placed in a first queue, where the first queue is a preset first-in-first-out queue. Because only 1 verification task is selected from the first queue at a time, the design device to be verified is ensured to only work in a certain working mode at the same time. After 1 verification task is selected from the first queue each time, for the verification task currently selected, determining an accumulated sub-value i selected from the first queue by the verification task in the verification process, and sending an ith step of the verification task to the design device to be verified so as to enable the design device to be verified to execute. It can be seen that i increases gradually from 1, i.e. for any one of the operation modes, each step of the verification task corresponding to the operation mode is sequentially sent to the design device to be verified from step 1, and no error occurs. After the design device to be verified finishes executing the received steps, the verification task is put back into the first queue after the random delay of the verification task selected currently, and each verification task is configured with 1 random delay, so that each step of N verification tasks is sent to the design device to be verified in a random and crossed mode through the random delay mechanism, and because the design device to be verified does not need to be disturbed manually, mistakes are not easy to happen, and the efficiency is high.
In summary, the scheme of the application can effectively realize verification of the design device to be verified, improves the verification efficiency and can avoid errors.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of an embodiment of a verification method for a design device to be verified
FIG. 2 is a schematic diagram of random interleaving of steps for implementing different verification tasks in one embodiment of the present application;
FIG. 3 is a schematic diagram of a verification system of a design device to be verified according to the present application;
FIG. 4 is a schematic structural diagram of a verification device of a design device to be verified in the present application;
fig. 5 is a schematic structural diagram of a computer readable storage medium according to the present application.
Detailed Description
The core of the application is to provide a verification method of the design device to be verified, which can effectively realize the verification of the design device to be verified, improve the verification efficiency and avoid errors.
In order to better understand the aspects of the present invention, the present invention will be described in further detail with reference to the accompanying drawings and detailed description. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, fig. 1 is a flowchart illustrating an implementation of a verification method of a design device to be verified in the present invention, the verification method of the design device to be verified may include the following steps:
step S101: and respectively configuring corresponding N verification tasks for N working modes of the design device to be verified, and configuring 1 random delay for each verification task. N is a positive integer and N is more than or equal to 2.
The design to be verified device may also be referred to as a DUT, a proxy design module. When simulation verification of the design device to be verified is carried out, excitation signals with certain functions are required to be generated outside and input into the DUT, whether output signals are correct or not is observed at the output end of the DUT, namely whether the output signals accord with expectations or not is observed, and therefore whether the functions of the DUT meet design requirements or not is judged.
The design device to be verified can comprise N working modes, wherein N is a positive integer not less than 2. For each working mode of the design device to be verified, in order to realize the test of the working mode, 1 corresponding verification task can be configured, and the configured verification task can comprise 1 or more steps.
Furthermore, it is understood that the specific content of the configured verification task may be different for different operation modes, and the number of steps included in the configured verification task may be different for different operation modes. For example, in one case, for the working mode a, the configured verification task corresponding to the working mode a is called a verification task a, for example, the verification task a includes 3 steps, called a step A1, a step A2 and a step A3, which are sequentially performed. For the working mode B, the configured verification task corresponding to the working mode B is called a verification task B, for example, the verification task B includes 5 steps sequentially performed, which are called a step B1, a step B2, a step B3, a step B4 and a step B5.
After the corresponding N verification tasks are respectively configured for the N working modes of the design device to be verified, in order to realize random crossing of the steps of different verification tasks, in the scheme of the application, 1 random delay needs to be configured for each verification task, namely, 1 delay needs to be configured for each verification task, and the delay of each verification task is randomly configured. Of course, in practical application, a delay range is generally set, so that the configured random delay needs to be within the delay range, and the situation that the scheme of the application takes too long to execute due to too large value of the random delay is avoided.
Step S102: n verification tasks are placed in a preset first-in first-out first queue.
In the scheme of the application, 1 queue needs to be preset, which is called a first queue. The first queue is a first-in first-out queue, i.e., for different validation tasks in the first queue, the validation task that was first placed in the first queue is first fetched.
In order to realize verification of N working modes, the configured N verification tasks are required to be placed in the first queue, and the specific placement mode can be set and adjusted according to actual needs, so long as the N verification tasks are placed in the first queue.
For example, in one embodiment of the present application, step S102 may include: placing N verification tasks into a preset first-in first-out first queue; the N verification tasks start timing of random time delay of the N verification tasks at the same time, and for any 1 verification task in the N verification tasks, after the random time delay configured for the verification task is passed, the verification task is placed into a preset first-in first-out first queue.
In this embodiment, since 1 random delay is configured for each verification task, when N verification tasks are placed in the first queue, the placement may be implemented based on the N random delays, that is, the N verification tasks start timing of their own random delays at the same time, and for any 1 verification task of the N verification tasks, after the random delay configured for the verification task is passed, the verification task may be placed in the preset first queue.
For example, in one scenario, N corresponding verification tasks are configured for N working modes of the design device to be verified, where the random delay configured for the verification task a is 2 seconds, and the random delay configured for the verification task B is 5 seconds, then after 2 seconds of triggering step S102, the verification task a is placed in the first queue, and after 3 seconds, the verification task B is placed in the first queue.
It can be seen that in this embodiment, N verification tasks are placed in the first queue based on N random delays, which is favorable to guaranteeing randomness of step intersection of subsequent different verification tasks.
As another example, in a specific embodiment of the present invention, the step S102 may include:
and placing the N verification tasks into a preset first-in first-out first queue in sequence according to the sequence of the task numbers from small to large or from large to small.
In this embodiment, N verification tasks may be sequentially placed in a preset first-in-first-out first queue according to the order of the task numbers from small to large or from large to small. For example, in one instance, validation task A, validation task B, validation task C, and validation task D are placed in the first queue sequentially.
It can be seen that, if this embodiment is adopted, when the verification task is selected from the first queue subsequently, during a period of time at the beginning, the selected verification task accords with the order of from small to large or from large to small in task number, for example, for the occasion described above, after the verification task a, the verification task B, the verification task C and the verification task D are sequentially put into the first queue, the step A1 of the task a, the step B1 of the task B, the step C1 of the task C and the step D1 of the task D are sequentially sent to the design device to be verified to be executed subsequently, and of course, after that, the steps to be executed subsequently to the design device to be verified are random due to the existence of random delay, that is, random intersection of the steps of different verification tasks is achieved.
As can be seen from the above description, in this embodiment, the effect is not as good as the former embodiment in terms of randomness of step crossing of implementing the subsequent different verification tasks, but this embodiment can put N verification tasks into the first queue directly without waiting when step S102 is triggered, which is beneficial to reducing the execution time of the scheme, although some sacrifice is made in terms of random crossing of steps of implementing the different verification tasks, but the effect is less. In practical applications, this embodiment or the former embodiment may be selected as desired.
Step S103: when at least 1 verification task exists in the first queue, 1 verification task is selected from the first queue.
In order to ensure that the design device to be verified can only work in a certain mode at the same time, only 1 verification task can be selected from the first queue at a time. And it will be appreciated that 1 validation task is selected from the first queue, at least when 1 validation task is present in the first queue.
After step S102 is triggered, the operation of step S103 may be performed for the first time as long as there are at least 1 verification tasks in the first queue. That is, after step S102 is triggered, it is not necessary to wait until N verification tasks have been placed in the preset first-in first-out first queue, but only if at least 1 verification task exists in the first queue, the operation of step S103 may be triggered for the first time, that is, 1 verification task may be selected from the first queue for the first time. In the subsequent implementation process, the operation of triggering the step S103 is returned every time a certain step of a certain verification task is performed by the design device to be verified.
Because the first queue is a first-in first-out queue, the verification task put into the first queue is taken out first, when 1 verification task is selected from the first queue, the verification task is selected from the head of the first queue, and if a certain verification task is needed to be put into the first queue, the verification task is put into the tail of the first queue.
Step S104: and determining the accumulated secondary value i selected from the first queue by the verification task in the verification process, and sending the ith step of the verification task to the design device to be verified so as to enable the design device to be verified to execute.
The 1 verification task may comprise 1 or more steps, e.g. verification task a comprises 3 steps, called step A1, step A2 and step A3. In performing verification of a designed device to be verified, although the intersection of steps of different verification tasks may be performed, the order of the different steps of the same verification task cannot be reversed. That is, in this example, step A2 and step A3 cannot be transmitted to the design apparatus to be verified before step A1, step A3 cannot be transmitted to the design apparatus to be verified before step A2, and should be performed in the order of step A1 to step A2 to step A3.
Therefore, in this embodiment, for the currently selected verification task, the cumulative secondary value i of the verification task selected from the first queue in the current verification process is determined, and then the i-th step of the verification task is sent to the design device to be verified, so that the design device to be verified executes the verification task.
It will be appreciated that for any 1 verification task, when the verification task is first selected from the first queue, the cumulative secondary value i=1, then step 1 of the verification task is sent to the design device to be verified to cause the design device to be verified to execute. When the verification task is selected from the first queue for the second time, the accumulated sub-value i=2, and the 2 nd step of the verification task is sent to the design device to be verified so as to enable the design device to be verified to execute. When the verification task is selected from the first queue for the third time, the accumulated sub-value i=3, and then the 3 rd step of the verification task is sent to the design device to be verified so as to enable the design device to be verified to execute. And so on until each step of the verification task has been sent to the design device to be verified for execution, at which point the verification task is no longer placed back in the first queue.
For any 1 verification task, the cumulative sub-value i selected from the first queue of the verification task is increased from 1, so that each step of the verification task is sent to the design device to be verified according to the step sequence, and the condition of step reversal or step omission caused by manual code writing is avoided, namely, the scheme accuracy is ensured.
Step S105: after the design device to be verified finishes executing the received steps, the verification task is put back into the first queue after the random delay of the verification task selected currently, and after the design device to be verified finishes executing the received steps, the operation of executing the step S103 is returned until each step of each verification task is executed by the design device to be verified.
After a step of a certain verification task is sent to the design device to be verified, the design device to be verified can execute the received step, and after the design device to be verified completes execution of the received step, the process can immediately return to step S103 to select 1 verification task from the first queue again. When each step of each verification task is performed by the design device to be verified, it is not necessary to return to step S103, but step S106 is triggered.
In order to achieve random crossing of steps of different verification tasks, after a certain step of a certain verification task is sent to a design device to be verified, the design device to be verified can execute the received step, and when the design device to be verified completes execution of the received step, the verification task is not immediately put back to a first queue, but waiting is needed, and the specific waiting time is random time delay configured for the verification task. The validation task is placed back in the first queue after a random delay of the validation task. And it should be noted that, for any 1 verification task, when each step of the verification task has been sent to the design device to be verified for execution, then the verification task does not need to be put back into the first queue. That is, if the cumulative number of times i the validation task was selected from the first queue reaches the total number of steps for the validation task, then the validation task need not be placed back in the first queue.
Referring to fig. 2, a schematic diagram of random crossing of steps for implementing different verification tasks in a specific embodiment, it can be seen that, at the same simulation time, only 1 step of the verification tasks is sent to the design device to be verified to be executed, and random crossing between steps of the different verification tasks is implemented. A certain step of a certain verification task, which is indicated by a hatched portion in fig. 2, is transmitted to the design device to be verified for execution.
Step S106: and determining the verification result of the design device to be verified.
When each step of each verification task is executed by the design device to be verified, the verification result of the design device to be verified can be determined based on the output data of the design device to be verified in the verification process.
For example, in one embodiment of the present invention, step S106 may include:
when the verification results of the N working modes of the design device to be verified are all passed, determining that the verification result of the design device to be verified is passed;
and when the verification results of at least 1 working modes in the N working modes of the design device to be verified are not passed, determining that the verification results of the design device to be verified are not passed.
In this embodiment, if the verification results of the N working modes of the design device to be verified are all passed, that is, the obtained verification results conform to the expectation for each working mode of the design device to be verified, it may be determined that the verification result of the design device to be verified is passed. Otherwise, if at least 1 of the verification results of the working modes are not passed, it can be determined that the verification result of the design device to be verified is not passed, and the implementation mode is a more common implementation mode in practical application.
In a specific embodiment of the present application, step S101 may include:
respectively configuring corresponding N verification tasks for N working modes of a design device to be verified through a first language, and configuring 1 random delay for each verification task;
step S102 may include:
and initiating N threads through a first language to respectively schedule N verification tasks, and placing the N verification tasks into a preset first-in first-out first queue.
In the scheme of the application, corresponding N verification tasks are required to be respectively configured for N working modes of the design device to be verified, 1 random delay is not configured for each verification task, and the design device can be realized through a first language in practical application. And, the first language can support a plurality of threads, and independent execution among the threads does not affect each other, so that N verification tasks of the application can be respectively scheduled based on N threads initiated by the first language.
The specific type of the first language can be set and adjusted as required, so long as the scheme of the present application can be implemented through the first language.
For example, in a specific occasion, the first language is the SystemVerilog language, so that randomized test excitation can be conveniently constructed, and a plurality of threads can be initiated and executed, and the independent execution of the threads does not affect each other. The system Verilog language has a specific communication mode, such as an event, among threads, so that the execution among the threads can be realized, such as a semaphore, conflict processing of resource sharing among the threads can be performed, such as a mailbox, and the synchronous transmission of data among the threads can be realized.
In a specific embodiment of the present application, step S103 may include:
establishing communication among N threads through a first language, and setting a first key;
1 verification task is selected from the first queue position, and a thread corresponding to the verification task acquires a first key so as to allow the thread to send the ith step of the verification task to the design device to be verified.
As described above, in the solution of the present application, it is necessary to ensure that the design device to be verified will only operate in a certain mode at the same time, so that only 1 verification task will be selected from the first queue at a time. In this embodiment, the implementation is based on the first key such that only 1 validation task is selected from the first queue at a time.
Still taking the first language as the SystemVerilog language as an example, a semaphore may be created at the task invocation level based on the SystemVerilog language, while assigning a key to the semaphore, i.e. the first key in this embodiment. When 1 verification task is selected from the first queue, only the thread corresponding to the verification task at the head of the queue can acquire the first key, and the ith step of the verification task can be sent to the design device to be verified after acquiring the first key. After the design to be verified performs this step, the first key needs to be returned so that the other threads can acquire the first key.
In one embodiment of the present invention, the method may further include:
each time after determining that the verification result of the design device to be verified is passed, verifying the design device to be verified again until the turn of verifying the design device to be verified reaches a set turn threshold;
and randomly updating the random delay of each verification task every time the design device to be verified is verified again.
In this embodiment, in order to improve the coverage rate of verification, that is, to improve the sufficiency of verification, multiple rounds of verification need to be performed on the design device to be verified, so in this embodiment, each time it is determined that the verification result of the design device to be verified is passed, the design device to be verified is again verified until the round of verification on the design device to be verified reaches the set round threshold.
In addition, in the embodiment, each time the design device to be verified is verified again, the random delay of each verification task is updated randomly, so that the steps of each verification task are crossed randomly again for verification of different rounds of the design device to be verified, and the sufficiency of verification is improved.
In one embodiment of the present invention, the method may further include:
when detecting that 2 or more verification tasks need to be placed in the first queue at the same time, triggering a set conflict resolution mechanism to enable each verification task with conflict to be placed in the first queue successively.
In the implementation of the scheme, there may be cases where 2 or more verification tasks need to be put back into the first queue at the same time. For example, in one case, when executing step S102, the foregoing scheme of simultaneously starting the timing of the random delays of the N verification tasks is adopted, and if the random delays of 2 or more verification tasks are exactly the same, the random delays of the verification tasks will end simultaneously, which means that the verification tasks need to be put into the first queue simultaneously, and at this time, the verification tasks collide.
For another example, when executing step S105, after the design device to be verified finishes executing the step of a certain verification task, after the random delay of the verification task, the verification task needs to be put back into the first queue, at this time, there may be just that other verification tasks are randomly delayed to finish, and the verification task needs to be put into the first queue, so that a conflict occurs.
In this way, the embodiment sets a conflict resolution mechanism, and through the conflict resolution mechanism, each verification task with conflict can be placed in the first queue successively. Of course, the specific manner of the conflict resolution mechanism may be set and selected according to actual needs, so long as the conflict can be resolved.
For example, in a specific embodiment of the present invention, when detecting that 2 or more verification tasks need to be placed in the first queue at the same time, triggering a set conflict resolution mechanism to enable each verification task that generates a conflict to be placed in the first queue sequentially may specifically include:
when detecting that 2 or more verification tasks need to be put into the first queue at the same time, triggering a set conflict resolution mechanism to ensure that each verification task with conflict restarts the timing of the random time delay of the verification task and puts into the first queue after the random time delay of the verification task
In this embodiment, if 2 or more verification tasks need to be put into the first queue at the same time, the adopted conflict resolution mechanism is to make the verification tasks restart the timing of the random delay of the verification tasks, and then put into the first queue after the random delay of the verification tasks. It will be appreciated that if a collision may still occur subsequently after restarting the timing of the random delay of itself, the collision resolution mechanism may continue to be triggered.
For another example, in one embodiment, when 2 or more verification tasks are detected and need to be placed in the first queue at the same time, the adopted conflict resolution mechanism is to randomly set the sequence of the verification tasks and place the verification tasks in the first queue.
By applying the technical scheme provided by the embodiment of the application, the verification of the design device to be verified can be automatically performed, the execution efficiency is high, and errors are not easy to occur. In the scheme of the application, corresponding N verification tasks are respectively configured for N working modes of the design device to be verified, and it can be seen that the random crossing of the steps under different verification tasks is not performed at this time, namely the configured N verification tasks are independent and complete, so that errors are not easy to occur. In order to achieve random crossing of steps under different verification tasks, the scheme of the application is not disturbed by manpower as in the traditional scheme, but is configured with 1 random delay for each verification task, and the random crossing of the steps under different verification tasks is achieved through the random delay. After 1 random delay is configured for each verification task, N verification tasks may be placed in a first queue, where the first queue is a preset first-in-first-out queue. Because only 1 verification task is selected from the first queue at a time, the design device to be verified is ensured to only work in a certain working mode at the same time. After 1 verification task is selected from the first queue each time, for the verification task currently selected, determining an accumulated sub-value i selected from the first queue by the verification task in the verification process, and sending an ith step of the verification task to the design device to be verified so as to enable the design device to be verified to execute. It can be seen that i increases gradually from 1, i.e. for any one of the operation modes, each step of the verification task corresponding to the operation mode is sequentially sent to the design device to be verified from step 1, and no error occurs. After the design device to be verified finishes executing the received steps, the verification task is put back into the first queue after the random delay of the verification task selected currently, and each verification task is configured with 1 random delay, so that each step of N verification tasks is sent to the design device to be verified in a random and crossed mode through the random delay mechanism, and because the design device to be verified does not need to be disturbed manually, mistakes are not easy to happen, and the efficiency is high.
In summary, the scheme of the application can effectively realize verification of the design device to be verified, improves the verification efficiency and can avoid errors.
Corresponding to the above method embodiment, the embodiment of the application also provides a verification system of the design device to be verified, which can be referred to above correspondingly.
Referring to fig. 3, a schematic structural diagram of a verification system of a design device to be verified according to the present application includes:
the verification task random delay distribution module 301 is configured to configure corresponding N verification tasks for N working modes of the design device to be verified, and configure 1 random delay for each verification task; n is a positive integer and N is more than or equal to 2;
an initial queue placement module 302, configured to place N verification tasks into a preset first-in-first-out first queue;
the verification task selection module 303 is configured to select 1 verification task from the first queue when at least 1 verification task exists in the first queue;
the sending module 304 is configured to determine, for a currently selected verification task, an accumulated secondary value i of the verification task selected from the first queue in the current verification process, and send an ith step of the verification task to a design device to be verified so that the design device to be verified executes the verification task;
The verification task placement module 305 is configured to place the verification task back into the first queue after the random delay of the verification task currently selected after the design device to be verified finishes executing the received step, and return to the trigger verification task selection module 303 after the design device to be verified finishes executing the received step until each step of each verification task is executed by the design device to be verified;
the verification result determining module 306 is configured to determine a verification result of the design device to be verified.
In one embodiment of the present invention, the initial queue placement module 302 is configured to:
placing N verification tasks into a preset first-in first-out first queue;
the N verification tasks start timing of random time delay of the N verification tasks at the same time, and for any 1 verification task in the N verification tasks, after the random time delay configured for the verification task is passed, the verification task is placed into a preset first-in first-out first queue.
In one embodiment of the present invention, the initial queue placement module 302 is configured to:
and placing the N verification tasks into a preset first-in first-out first queue in sequence according to the sequence of the task numbers from small to large or from large to small.
In one embodiment of the present invention, the verification result determining module 306 is configured to:
when the verification results of the N working modes of the design device to be verified are all passed, determining that the verification result of the design device to be verified is passed;
and when the verification results of at least 1 working modes in the N working modes of the design device to be verified are not passed, determining that the verification results of the design device to be verified are not passed.
In one embodiment of the present invention, the verification task random delay allocation module 301 is configured to:
respectively configuring corresponding N verification tasks for N working modes of a design device to be verified through a first language, and configuring 1 random delay for each verification task;
an initial queue placement module 302, configured to:
and initiating N threads through a first language to respectively schedule N verification tasks, and placing the N verification tasks into a preset first-in first-out first queue.
In one embodiment of the present invention, the verification task selection module 303 is configured to:
establishing communication among N threads through a first language, and setting a first key;
1 verification task is selected from the first queue position, and a thread corresponding to the verification task acquires a first key so as to allow the thread to send the ith step of the verification task to the design device to be verified.
In a specific embodiment of the present invention, the method further includes a repeat execution module for:
each time after determining that the verification result of the design device to be verified is passed, verifying the design device to be verified again until the turn of verifying the design device to be verified reaches a set turn threshold;
and randomly updating the random delay of each verification task every time the design device to be verified is verified again.
In a specific embodiment of the present invention, the system further includes a conflict resolution module configured to:
when detecting that 2 or more verification tasks need to be placed in the first queue at the same time, triggering a set conflict resolution mechanism to enable each verification task with conflict to be placed in the first queue successively.
In one embodiment of the present invention, the conflict resolution module is specifically configured to:
when detecting that 2 or more verification tasks need to be put into the first queue at the same time, triggering a set conflict resolution mechanism, so that each verification task with conflict restarts the timing of the random delay of the verification task, and putting the verification task into the first queue after the random delay of the verification task.
Corresponding to the above method and system embodiments, the embodiments of the present invention further provide a verification device for a design apparatus to be verified, and a computer readable storage medium, which can be referred to above in correspondence with each other.
Referring to fig. 4, the verification apparatus of the design device to be verified may include:
a memory 401 for storing a computer program;
a processor 402 for executing a computer program to implement the steps of the verification method of the design device to be verified as described above.
Referring to fig. 5, the computer readable storage medium 50 stores a computer program 51, and the computer program 51 implements the steps of the verification method of the design device to be verified when executed by a processor. The computer readable storage medium 50 as described herein includes Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
It is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The principles and embodiments of the present invention have been described herein with reference to specific examples, but the description of the examples above is only for aiding in understanding the technical solution of the present invention and its core ideas. It should be noted that it will be apparent to those skilled in the art that the present invention may be modified and practiced without departing from the spirit of the present invention.
Claims (12)
1. A verification method of a design device to be verified, comprising:
Respectively configuring corresponding N verification tasks for N working modes of a design device to be verified, and configuring 1 random delay for each verification task; n is a positive integer and N is more than or equal to 2;
placing N verification tasks into a preset first-in first-out first queue;
selecting 1 verification task from the first queue when at least 1 verification task exists in the first queue;
for the verification task currently selected, determining an accumulated sub-value i selected from the first queue by the verification task in the verification process, and sending an i-th step of the verification task to the design device to be verified so as to enable the design device to be verified to execute;
after the design device to be verified finishes executing the received steps, the verification task is put back into the first queue after the random delay of the verification task which is currently selected, and after the design device to be verified finishes executing the received steps, the operation of selecting 1 verification task from the first queue is returned to be executed until each step of each verification task is executed by the design device to be verified;
And determining the verification result of the design device to be verified.
2. The method for verifying a design device to be verified according to claim 1, wherein placing N verification tasks into a first queue of a predetermined first-in-first-out includes:
placing N verification tasks into a preset first-in first-out first queue;
the N verification tasks start timing of random time delay of the N verification tasks at the same time, and for any 1 verification task in the N verification tasks, after the random time delay configured for the verification task is passed, the verification task is placed into a preset first-in first-out first queue.
3. The method for verifying a design device to be verified according to claim 1, wherein placing N verification tasks into a first queue of a predetermined first-in-first-out includes:
and placing N verification tasks into a preset first-in first-out first queue in sequence according to the sequence of the task numbers from small to large or from large to small.
4. The method for verifying a design device to be verified according to claim 1, wherein the determining a verification result of the design device to be verified comprises:
When the verification results of the N working modes of the design device to be verified are all passed, determining that the verification results of the design device to be verified are passed;
and when the verification result of at least 1 working mode in the N working modes of the design device to be verified fails, determining that the verification result of the design device to be verified fails.
5. The method for verifying a design device to be verified according to claim 1, wherein the configuring of corresponding N verification tasks for N operation modes of the design device to be verified, and configuring 1 random delay for each of the verification tasks, respectively, comprises:
respectively configuring corresponding N verification tasks for N working modes of a design device to be verified through a first language, and configuring 1 random delay for each verification task;
placing the N verification tasks into a preset first queue of first-in first-out, including:
initiating N threads through the first language to respectively schedule N verification tasks, and placing the N verification tasks into a preset first-in first-out first queue.
6. The method of verifying a design device to be verified of claim 5, wherein selecting 1 of the verification tasks from the first queue comprises:
Establishing communication among N threads through the first language, and setting a first key;
and 1 verification task is selected from the head of the first queue, and the thread corresponding to the verification task acquires the first key so as to allow the thread to send the ith step of the verification task to the design device to be verified.
7. The verification method of a design device to be verified according to claim 1, further comprising:
when detecting that 2 or more verification tasks need to be put into the first queue at the same time, triggering a set conflict resolution mechanism to enable each verification task with conflict to be put into the first queue successively.
8. The verification method of a design device to be verified according to claim 7, wherein when 2 or more verification tasks are detected to be placed in the first queue at the same time, triggering a set conflict resolution mechanism so that each verification task that is in conflict is placed in the first queue in sequence, comprises:
when detecting that 2 or more verification tasks need to be put into the first queue at the same time, triggering a set conflict resolution mechanism, so that each verification task which generates conflict restarts the timing of the random delay of the verification task, and putting the verification task into the first queue after the random delay of the verification task.
9. The verification method of a design apparatus to be verified according to any one of claims 1 to 8, further comprising:
each time after determining that the verification result of the design device to be verified is passed, verifying the design device to be verified again until the turn of verifying the design device to be verified reaches a set turn threshold;
and each time the design device to be verified is verified again, randomly updating the random delay of each verification task.
10. A verification system for a design device to be verified, comprising:
the verification task random delay distribution module is used for respectively configuring N corresponding verification tasks for N working modes of the design device to be verified, and configuring 1 random delay for each verification task; n is a positive integer and N is more than or equal to 2;
the initial queue placement module is used for placing N verification tasks into a preset first-in first-out first queue;
the verification task selection module is used for selecting 1 verification task from the first queue when at least 1 verification task exists in the first queue;
the sending module is used for determining an accumulated sub-value i selected from the first queue by the verification task in the verification process, and sending an ith step of the verification task to the design device to be verified so as to enable the design device to be verified to execute;
The verification task replacement module is used for replacing the verification task into the first queue after the random delay of the verification task currently selected after the received step is executed by the design device to be verified, and returning to trigger the verification task selection module after the received step is executed by the design device to be verified until all the steps of the verification task are executed by the design device to be verified;
and the verification result determining module is used for determining the verification result of the design device to be verified.
11. A verification apparatus of a design device to be verified, characterized by comprising:
a memory for storing a computer program;
a processor for executing the computer program to implement the steps of the verification method of the design apparatus to be verified as claimed in any one of claims 1 to 9.
12. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored thereon a computer program which, when executed by a processor, implements the steps of the verification method of the design apparatus to be verified according to any one of claims 1 to 9.
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