CN116564978A

CN116564978A - Novel protection diode structure for stacked image sensor devices

Info

Publication number: CN116564978A
Application number: CN202210979151.0A
Authority: CN
Inventors: 高敏峰; 许慈轩
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-03-22
Filing date: 2022-08-16
Publication date: 2023-08-08

Abstract

The present disclosure relates to novel protective diode structures for stacked image sensor devices. The first side of the sensor wafer is bonded to the first side of the first logic wafer. The sensor wafer includes pixels configured to detect radiation entering the sensor wafer through a second side of the sensor wafer opposite the first side. The first logic wafer includes circuitry configured to operate the pixels. The sensor wafer or the first logic wafer includes a protection diode. The first logic wafer is thinned from a second side of the first logic wafer opposite the first side. Through Substrate Vias (TSVs) are formed in the first logic wafer. The protection diode protects the sensor wafer or the first logic wafer from damage during TSV formation. The second side of the first logic wafer is bonded to the second logic wafer. The sensor wafer is thinned from the second side of the sensor wafer.

Description

Novel protection diode structure for stacked image sensor devices

Technical Field

The present disclosure relates to novel protective diode structures for stacked image sensor devices.

Background

The semiconductor Integrated Circuit (IC) industry has experienced an exponential growth. Technological advances in IC materials and design have resulted in several generations of ICs, each having smaller and more complex circuitry than the previous generation. During the evolution of ICs, functional density (i.e., the number of interconnected devices per chip area) generally increases while geometry (i.e., the smallest component (or line) that can be created using a manufacturing process) decreases. Such scaled down processes generally provide benefits by improving production efficiency and reducing associated costs.

As semiconductor devices shrink in size and increase in complexity, they may be deployed in a wide variety of applications. These applications may include semiconductor image sensors for sensing radiation such as light. For example, complementary Metal Oxide Semiconductor (CMOS) image sensors (CIS) and Charge Coupled Device (CCD) sensors are widely used in various applications such as digital cameras, cell phones, medical devices, automotive sensors, and the like. These devices utilize an array of pixels in a substrate, including photodiodes and transistors, which can absorb radiation impinging on the substrate and convert the sensed radiation into electrical signals.

However, conventional image sensor device fabrication processes may expose the device to ambient plasma, which may damage elements of the image sensor device. In addition, conventional image sensor devices may also be susceptible to damage during actual operation. Conventional methods of protecting image sensor devices from these types of damage are not entirely satisfactory.

Disclosure of Invention

According to an embodiment of the present disclosure, there is provided an image sensor device including: a first substrate including a plurality of pixels and at least one transistor; a second substrate bonded to the first substrate, the second substrate including circuitry for interacting with the pixels; and a protection diode disposed within the first substrate or the second substrate, the protection diode including: a first doped region, a second doped region disposed within the first doped region, and a third doped region disposed within the second doped region; wherein: the first doped region and the third doped region have the same conductivity type; the second doped region has a different conductivity type than the first doped region and the third doped region; and the third doped region is electrically coupled to a transistor of the first substrate.

According to another embodiment of the present disclosure, there is provided an image sensor device including: a sensor substrate comprising a plurality of pixels and transfer gates, wherein the pixels are configured to detect radiation entering the sensor substrate through a backside of the sensor substrate; a first non-sensor substrate bonded to the sensor substrate through a front side of the sensor substrate, the first non-sensor substrate comprising circuitry configured to operate the pixels; a second non-sensor substrate bonded to the first non-sensor substrate such that the first non-sensor substrate is bonded between the sensor substrate and the second non-sensor substrate, the second non-sensor substrate including other circuitry configured to operate the pixel; one or more protection diodes implemented in the sensor substrate, the first non-sensor substrate, or the second non-sensor substrate; wherein: each of the one or more protection diodes includes: a first doped well, a second doped well located within the first doped well, and a third doped well located within the second doped well; the second doped well has a different conductivity type than the first doped well and the third doped well; the first doped well is electrically connected to a first reference voltage; the second doped well is electrically connected to a second reference voltage different from the first reference voltage; and the third doped well is electrically connected to the pass gate.

According to still another embodiment of the present disclosure, there is provided a method of manufacturing an image sensor device, including: bonding a first side of a sensor wafer to a first side of a first logic wafer, wherein the sensor wafer comprises pixels configured to detect radiation entering the sensor wafer through a second side of the sensor wafer opposite the first side, wherein the first logic wafer comprises circuitry configured to operate the pixels, and wherein the sensor wafer or the first logic wafer comprises protection diodes; thinning the first logic wafer from a second side of the first logic wafer opposite the first side; forming a Through Substrate Via (TSV) in the first logic wafer, wherein the protection diode protects the sensor wafer or the first logic wafer from damage during the TSV formation; bonding a second side of the first logic wafer to a second logic wafer; and thinning the sensor wafer from the second side of the sensor wafer.

Drawings

The disclosure may be best understood from the following detailed description when read in connection with the accompanying drawing. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale, but are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1-4 illustrate a series of cross-sectional side views of an image sensor device at various stages of manufacture corresponding to a process flow, in accordance with aspects of the present disclosure.

Fig. 5-10 illustrate cross-sectional side views of image sensor devices according to various aspects of the present disclosure.

Fig. 11 shows a flow chart illustrating a method in accordance with aspects of the present disclosure.

Fig. 12 illustrates a block diagram of an integrated circuit manufacturing system in accordance with various aspects of the disclosure.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Furthermore, in the present disclosure below, the formation of another feature on, connected to, and/or coupled to a feature may include embodiments in which the feature is formed in direct contact, and may also include embodiments in which additional features are formed in a manner that inserts the feature so that the feature is not in direct contact. Furthermore, spatially relative terms, such as "lower," "upper," "horizontal," "vertical," "above," "below," "beneath," "upper," "lower," "top," "bottom," and the like, and derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.), are used herein for ease of describing the relationship of one feature to another feature of the present disclosure. Spatially relative terms are intended to encompass different orientations of the device in which the features are included. Furthermore, when numbers or ranges of numbers are described using "about" and "approximately," etc., the term is intended to encompass numbers within a reasonable range including the recited numbers, such as numbers within +/-10% of the recited number or other values as understood by one of skill in the art. For example, the term "about 5nm" encompasses a size range from 4.5nm to 5 nm.

The present disclosure relates generally to semiconductor devices, and more particularly to image sensor devices. For example, the present disclosure describes methods and apparatus for protecting stacked CMOS Image Sensors (CIS) during their manufacture and operation, which in turn improves CIS yield and/or performance. In more detail, embodiments of the CIS 10 utilize a 3-wafer stack structure implementation. Referring to fig. 1-4, a simplified manufacturing process flow of the CIS 10 is shown, and fig. 1-4 are cross-sectional side views of the CIS 10 at different stages of manufacture. The cross-sectional view is taken along a plane defined by a horizontal X-direction (or X-axis) and a vertical Y-direction (or Y-axis).

Referring now to fig. 1, cis 10 includes a sensor wafer T1. The sensor wafer T1 may include a substrate, for example, a silicon substrate doped with a P-type dopant or an N-type dopant. The P-type dopant may be boron and the N-type dopant may be phosphorus or arsenic. The substrate of the sensor wafer T1 may also comprise other base semiconductors (e.g. germanium), and/or may optionally comprise compound semiconductors and/or alloy semiconductors. In addition, the substrate of sensor wafer T1 may include an epitaxial layer (epi layer), may be strained to improve performance, and may include a silicon-on-insulator (SOI) structure.

The substrate of the sensor wafer T1 comprises a plurality of radiation-or light-sensing elements (not specifically shown in fig. 1-4 for simplicity). The radiation-sensing element is a portion of a pixel operable to sense or detect a radiation wave (e.g., light) directed toward the sensor wafer T1 and entering the sensor wafer T1 through the backside 20 of the sensor wafer T1. In some embodiments, the radiation sensing element comprises a photodiode. In other embodiments, the radiation sensing element may include a pinned photodiode (pinned photodiode, PPD), a photogate, or other suitable photosensitive element. A photodiode or other type of radiation-sensing element may be formed by performing a plurality of ion implantation processes on the substrate of the sensor wafer T1. For example, an n+ implant, an array N-well implant, and a deep array N-well implant may be performed. The ion implantation process may include multiple implantation steps and may use different types of dopants, implant doses, and implant energies. The ion implantation process may also use different masks with different patterns and opening sizes. In some embodiments, the radiation-sensing element may also be formed in a doped well having a conductivity type opposite to the substrate of the sensor wafer T1.

The radiation sensing elements are physically and electrically isolated by isolation structures, such as by Shallow Trench Isolation (STI) or Deep Trench Isolation (DTI) structures. STI or DTI structures are formed by etching openings (or trenches) in the substrate and then filling the openings with a suitable material. The isolation structures are used to prevent or substantially reduce cross-talk between adjacent radiation sensing elements. The crosstalk may be electrical, or optical, or both. If not attenuated, crosstalk can degrade the performance of the CIS 10.

The sensor wafer T1 may also include other types of microelectronic components, such as reset transistors, source follower transistors, pass transistors (transfer transistor), or other suitable devices. As will be discussed in more detail below with reference to fig. 1-10, some of these microelectronic assemblies may be electrically coupled to a protection device, such as a protection diode. For example, the pass gate of sensor wafer T1 may be electrically coupled to a protection diode, the details of which will be discussed below.

With continued reference to FIG. 1, sensor wafer T1 is bonded to logic wafer T2. Specifically, front side 30 (opposite back side 20) of sensor wafer T1 is bonded to side 40 of logic wafer T2. The logic wafer T2 contains different microelectronic components than the sensor wafer T1. For example, the logic wafer T2 does not include radiation-sensing elements, such as photodiodes. Instead, the logic wafer T2 may include circuitry configured to operate the pixels of the sensor wafer T1. For example, logic wafer T2 may include decoders, registers, multiplexers/demultiplexers, amplifiers, read-out transistors, reference pixels, application Specific Integrated Circuits (ASICs), and so forth. These types of circuits are located at or near side 40, side 40 may be referred to as the active side of logic wafer T2.

The sensor wafer T1 and the logic wafer T2 each include an interconnect structure, respectively. The interconnect structure includes a plurality of patterned dielectric layers and conductive layers that provide interconnections (e.g., metal wiring) between the various doped features, circuits, and input/output of the CIS 10. In some embodiments, the interconnect structure may be a multi-layer interconnect (MLI) structure that includes multiple metal layers (e.g., metal 0, metal 1, metal 2, etc.) formed in a configuration such that an inter-layer dielectric (ILD) separates and isolates contacts, vias, and metal lines of the MLI structure. In one example, the MLI structure may include a conductive material, such as aluminum, aluminum/silicon/copper alloy, titanium nitride, tungsten, polysilicon, metal silicide, or combinations thereof, referred to as an aluminum interconnect. The aluminum interconnect may be formed by a process including Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), or combinations thereof. Other fabrication techniques for forming aluminum interconnects may include photolithographic processing and etching for patterning conductive material for vertical connections (vias and contacts) and horizontal connections (wires). Alternatively, copper multilayer interconnects may be used to form metal patterns. The copper interconnect structure may include copper, copper alloy, titanium nitride, tantalum nitride, tungsten, polysilicon, metal silicide, or combinations thereof. The copper interconnect may be formed by techniques including CVD, sputtering, electroplating, or other suitable processes. It should be appreciated that other conductive materials (e.g., cobalt, tungsten, or ruthenium) may also be used to form the various components of the MLI structure.

In the embodiment shown in fig. 1, the interconnect structure of sensor wafer T1 is located on front side 30 of sensor wafer T1 and the interconnect structure of logic wafer T2 is located on side 40 of logic wafer T2. Thus, the interconnect structure of sensor wafer T1 is bonded to the interconnect structure of logic wafer T2. In some embodiments, sensor wafer T1 includes a Hydrophobic Bonding Layer (HBL) on front side 30, logic wafer T2 includes an HBL on side 40, and bonding of sensor wafer T1 and logic wafer T2 is at least partially performed by their respective HBLs.

Referring now to fig. 2, a thinning process 50 is performed on a logic wafer T2 from a side 60 of the logic wafer T2 opposite the side 40. Side 60 may also be referred to as the back side of logic wafer T2, while side 40 may also be referred to as the front side of logic wafer T2. In some embodiments, the thinning process 50 may include a mechanical grinding process and/or a chemical thinning process. For example, during the mechanical lapping process, a large amount of material may first be removed from the side 60 of the logic wafer T2. Thereafter, a chemical thinning process may apply an etching chemistry to the logic wafer T2 to further thin the logic wafer T2. In some embodiments, the thinning process 50 may reduce the logic wafer T2 from an initial thickness of between about 700-800 microns to a thickness of between about 2-3 microns.

After the thinning process 50 is performed, through substrate vias (TSVs, also referred to as through silicon vias) are formed in the logic wafer T2. The formation of such TSVs includes one or more etching, deposition, or ashing processes, which may use a plasma. The charge from the plasma may cause unintended damage to metallization features (e.g., metal lines or vias/contacts) on the logic wafer T2, which is undesirable. To alleviate this problem, the present disclosure implements one or more protection diodes in logic wafer T2 and/or sensor wafer T1. As will be discussed in more detail below, the protection diode includes a plurality of doped regions that help to release or otherwise dissipate plasma charges associated with an etch or metal deposition process used to form the TSV, which is one of the benefits provided by the present disclosure. It should also be appreciated that after performing the thinning process 50, HBL may be formed on the side 60 of the logic wafer T2. For simplicity, the HBL, TSV, and protection diode are not specifically shown in fig. 2, although they will be shown and discussed in more detail in later figures, such as in fig. 5-6.

Referring now to fig. 3, fig. 3 provides another logic wafer T3. Similar to logic wafer 2, logic wafer T3 may contain different microelectronic components than sensor wafer T1. For example, the logic wafer T3 does not contain the radiation-sensing elements of the sensor wafer T1, but rather contains circuitry for operating the radiation-sensing elements of the sensor wafer T1, or otherwise electrically interacting with the radiation-sensing elements of the sensor wafer T1. The circuitry of the logic wafer T3 may be formed primarily at the side 70 of the logic wafer T3 or near the side 70, which side 70 may be referred to as the active side of the logic wafer T3. Logic wafer T3 also has a side 80 opposite side 70.

With continued reference to fig. 3, a bonding process 90 is performed on the CIS 10 to bond the side 70 of the logic wafer T3 to the side 60 of the logic wafer T2. In some embodiments, the HBL is formed on side 60 of logic wafer T2 and the HBL is formed on side 70 of logic wafer T3. The bonding may be performed at least in part by bonding the respective HBLs together.

Referring now to fig. 4, a thinning process 100 is performed on the CIS 10 to reduce the thickness of the sensor wafer T1. Again, the thinning process 100 may include a mechanical grinding process and/or a chemical thinning process. For example, during the mechanical lapping process, a large amount of material may first be removed from the side 20 of the sensor wafer T1. Thereafter, a chemical thinning process may apply an etching chemistry to the sensor wafer T1 to further thin the sensor wafer T1. After the thinning process 100 is performed, openings for sensor elements may be formed on the side 20 of the sensor wafer T1. These openings may be used for chip pads used to probe and/or test the CIS 10.

Fig. 5-6 are schematic partial cross-sectional side views of the CIS 10 according to one embodiment of the present disclosure. In more detail, fig. 5 shows details of the CIS 10 as a stacked structure of three wafers bonded together: sensor wafer T1, logic wafer T2, and logic wafer T3, and fig. 6 shows an enlarged view of a portion of CIS 10. In other words, the CIS 10 of FIGS. 5-6 has undergone the manufacturing steps discussed above in connection with FIGS. 1-4. For consistency and clarity reasons, similar components appearing in fig. 1-6 bear the same reference numerals.

Referring to fig. 5-6, sensor wafer T1 is bonded to logic wafer T2 through bonding interface 140, and logic wafer T2 is bonded to logic wafer T3 through bonding interface 150. For example, sensor wafer T1 includes one or more HBLs 160 formed on side 30, logic wafer T2 includes one or more HBLs 170 formed on side 40 and one or more HBLs 180 formed on side 60, and logic wafer T3 includes one or more HBLs 190 formed on side 70. One or more HBLs 160 of sensor wafer T1 are bonded to one or more HBLs 170 of logic wafer T2, and one or more HBLs 180 of logic wafer T2 are bonded to one or more HBLs 190 of logic wafer T3.

Sensor wafer T1 includes substrate 200, logic wafer T2 includes substrate 210, and logic wafer T3 includes substrate 220. As described above, the substrates 200-220 may each comprise a semiconductor substrate, such as a silicon substrate doped with a P-type dopant or an N-type dopant. Further, the substrates 200, 210, or 220 may each include an epitaxial layer (epi layer), or may be strained to improve performance.

Circuitry or other microelectronic components may be formed in the substrates 200-220. For example, a photosensitive element such as a photodiode may be formed as part of the pixel 225 in the substrate 200. The photodiodes may be configured to sense or detect light or radiation waves entering the substrate 200 from the side 20. Pixels 225 (comprising photodiodes) may collectively form a pixel grid array. Color filters and microlenses may be formed over each pixel to help filter out unwanted wavelengths of light (e.g., corresponding to various colors) and focus the desired colors of light. In this regard, the color filters may support filtering radiant waves having different wavelengths, which may correspond to different colors, such as primary colors including red, green, and blue, or complementary colors including cyan, yellow, and magenta. The color filters may also be positioned such that the desired incident optical radiation is directed onto and through the color filters. For example, the color filter may filter the incident radiation such that only red light reaches the photodiode or another suitable radiation sensing element. The color filter may include a dye-based (or pigment-based) polymer or resin to achieve filtering of a specific wavelength band.

After forming the color filter, microlenses are formed over the color filter. The microlenses help to direct radiation toward the photodiodes or other suitable radiation sensing elements. Depending on the refractive index of the material used for the microlenses and the distance from the surface of the substrate 200, the microlenses may be positioned in various arrangements and have various shapes. In an embodiment, each microlens comprises an organic material, such as a photoresist material or a polymer material. Microlenses are formed from one or more photolithographic processes.

In addition to the pixel, the transistor 230 may be formed at least partially in the substrate 200, the transistor 240 may be formed at least partially in the substrate 210, and the transistor 245 may be formed at least partially in the substrate 220. In some embodiments, transistor 230 may include a pass transistor. Each pass transistor 230 has a pass gate formed between a photosensitive element (e.g., a photodiode, not shown in fig. 5-6 for simplicity) and a floating diffusion region. The transfer gate may be used to transfer accumulated charge from the photosensitive element to the floating diffusion region. In some embodiments, transistor 230 may also be considered part of pixel 225.

Meanwhile, the transistors 240-245 may be part of circuitry configured to operate the pixels of the sensor wafer T1. For example, transistors 240-245 may be part of decoders, registers, multiplexers/demultiplexers, amplifiers, read-out transistors, reference pixels, application Specific Integrated Circuits (ASICs), etc. Transistors 240-245 may control or otherwise interact with the circuitry of pixel 225 and pass transistor 230.

According to aspects of the present disclosure, the protection diode 250 is also implemented in the CIS 10. In the embodiment shown in fig. 5-6, the protection diode 250 is implemented in the logic wafer T2, but it should be understood that in other embodiments, the protection diode 250 (or other examples of the protection diode 250) may be implemented in the sensor wafer T1 or the logic wafer T3. The protection diode 250 includes a plurality of differently doped regions. For example, as described in detail with reference to fig. 6, the protection diode 250 includes a doped region 260 disposed within the substrate 210, a doped region 270 disposed within the doped region 260, and a doped region 280 disposed within the doped region 270. Doped regions 260 and 280 may have the same conductivity type, while doped region 270 has a different conductivity type than doped regions 260 and 280. For example, in embodiments where substrate 210 is a P-type substrate, doped regions 260 and 280 may be N-type doped regions and doped region 270 may be a P-type doped region.

In some embodiments, doped region 260 includes a deep N-well (labeled herein as DNW) (which includes lightly doped N-type material), and N-well (labeled herein as NW) (which includes N-type material having a greater dopant concentration level than the deep N-well), and a heavily doped N-type region (labeled herein as n+) (which has an even greater dopant concentration level than both the deep N-well and the N-well). The heavily doped N-type region is shallower (e.g., has a shallower depth) within the doped region 260 than the N-well, which is shallower than the deep N-well. Thus, the N-type dopant concentration level within doped region 260 may increase as the depth of doped region 260 becomes shallower.

In some embodiments, doped region 270 includes a P-well (labeled PW herein) (which includes doped P-type material), and a heavily doped P-type region (labeled p+ herein) (which includes heavily doped P-type material that is more doped than the P-well). The heavily doped P-type region is shallower (e.g., has a shallower depth) within the doped region 270 than the P-well. Thus, the P-type dopant concentration level within doped region 270 may also increase as the depth of doped region 270 becomes shallower.

In some embodiments, doped region 280 comprises a heavily doped N-type region (again labeled n+ herein). Dopant concentration levels of doped region 280, the heavily doped P-type region (i.e., p+) of doped region 270, and the heavily doped N-type region (i.e., n+) of doped region 260 may be the same as one another. For example, these dopant concentration levels may be at about 10 ¹⁰ /cm ² About 10 ¹⁶ /cm ² Within a range between. Meanwhile, the dopant concentration levels of the P-well of doped region 270 and the N-well of doped region 260 may be about 10 ¹⁰ /cm ² About 10 ¹⁶ /cm ² Within a range between, and the dopant concentration level of the deep N-well of doped region 260 may be about 10 ¹⁰ /cm ² About 10 ¹³ /cm ² Within a range between. These ranges are not randomly selected, but are specifically configured so that the doped regions 260-280 will help protect the CIS from plasma damage and maintain an appropriate electrical bias to prevent damage to the microelectronic components of the CIS 10.

For example, as discussed above with reference to fig. 2, the formation of CIS 10 includes forming TSV 300 (labeled herein as BTSV) in logic wafer T2. TSVs 300 each extend vertically in the Z-direction through substrate 210 of logic wafer T2. To form such TSVs 300, one or more etching processes may be performed to etch openings in the substrate 210, and then a metal deposition process is performed to fill the openings with a conductive material (e.g., copper, aluminum, tungsten, cobalt, ruthenium, or a combination thereof). One or more etching or metal deposition processes may involve the use of a plasma. Unfortunately, the charge associated with the ambient plasma may adversely affect the various microelectronic components of the CIS 10. For example, sensor wafer T1 may include interconnect structure 310 formed over substrate 200, and logic wafer T2 may include interconnect structure 320 formed over substrate 210 and bonded to interconnect structure 310 (e.g., through HBLs 160 and 170). Each interconnect structure 310 and 320 may include multiple metal layers with metal lines that are electrically interconnected by conductive vias or contacts. These metallization features of interconnect structures 310 and 320 may be susceptible to damage from plasma charges (generated as a result of etching or deposition processes performed as part of the formation of TSV 300). If uncontrolled, the damaged metallization features may reduce the performance of the CIS 10 and/or reduce the yield of the CIS 10.

To overcome the above problems, the present disclosure uses a protection diode 250 to discharge or diffuse plasma charges. For example, the doped regions 260, 270, and 280 of the protection diode 250 are each electrically coupled to the interconnect structure 320 (and, by extension, to the interconnect structure 310) through respective vias and metal lines. Doped regions 260, 270, and/or 280 may help to release charges that would otherwise accumulate on metallization features (e.g., metal lines, vias, and contacts) of interconnect structures 320 and 310. Thus, the metallization features are less likely to be damaged by plasma charges generated during the formation of the TSV 300. Further, the performance and/or yield of the CIS 10 may be improved. This has the advantage of achieving the inherent result of protecting diode 250 on logic wafer T2 (or sensor wafer T1) prior to performing the plasma related process.

The protection diode 250 also protects various microelectronic components of the CIS 10 during electrical operation of the CIS 10. For example, pass transistor 230 may operate in a voltage range between about-M volts (V) and about N volts, where M and N are each positive numbers. For example, in an embodiment, m=1.2, n=3, which means that the voltage of the transfer transistor 230 may swing between about-1.2V and about 3V during the electrical operation of the CIS 10. Pass transistor 230 is electrically coupled to substrate 210, substrate 210 being considered to be electrically grounded. When pass transistor 230 swings to a sufficiently negative voltage, it may also pull substrate 210 down to a negative voltage. This would be undesirable because the appropriate electrical biasing of the various circuits on logic wafer T2 (for their intended electrical operation) assumes that substrate 210 is at electrical ground, rather than at a negative voltage. Thus, pulling the substrate 210 to a negative voltage may adversely interfere with proper electrical operation of the CIS 10.

Here, the present disclosure electrically couples the protection diode 250 to the pass transistor 230 to prevent the occurrence of the above-described problem (e.g., the substrate 210 is pulled to a negative voltage). For example, doped region 260 is electrically biased to a first reference voltage (e.g., through a conductive via and a metal line of interconnect structure 320), doped region 270 is electrically biased to a second reference voltage (e.g., through another conductive via and a metal line of interconnect structure 320), and doped region 280 of protection diode 250 is electrically coupled to the gate of pass transistor 230 through conductive vias and metal lines of interconnect structures 320 and 310.

In the illustrated embodiment, the first reference voltage is a positive voltage and the second reference voltage is a negative voltage that is more negative than the negative voltage of transistor 230. For example, the first reference voltage may be about 2.8V and the second reference voltage may be about-2V, which are common voltage references for other circuits in the logic wafer T2. Because transistor 230 can swing down to a negative voltage of at most-1.2V (where m=1.2) (e.g., to the lower end of its negative voltage range), the second reference voltage is even more negative than the most negative voltage value of pass transistor 230 (e.g., -2V is more negative than-1.2V). Such an electrical bias scheme may effectively prevent the substrate 210 from being pulled to an undesirable negative voltage. For example, because doped region 270 surrounds doped region 280 in a cross-sectional view, doped region 270 forms a P/N junction with doped region 280. When the pass transistor swings to-1.2V (i.e., its most negative voltage), the doped region 280 may be pulled to this negative voltage of-1.2V. However, doped region 270 is connected to-2V, which is a negative voltage that is more negative than-1.2V at doped region 280. This means that the P/N junction formed by doped regions 270 and 280 is still reverse biased, which results in very little, if any, current flow. Thus, the substrate 210 is substantially unaffected (i.e., is not pulled down to a negative voltage of-1.2V for the pass transistor 230) during the entire voltage swing of the pass transistor 230.

Note that if the doped region 270 is biased to a reference voltage that is greater than the voltage of the pass transistor (e.g., the second reference voltage is 0V instead of-2V), then the reverse bias condition may not be achieved, which would not prevent the negative voltage of the pass transistor from pulling the substrate 210 down to a negative voltage. Accordingly, the present disclosure utilizes not only unique device configurations, but also novel electrical bias schemes to achieve various operational benefits of the CIS 10. These operational benefits (e.g., isolating the substrate 210 from unwanted voltage variations) are inherent consequences of implementing the protection diode 250 (with the particular configuration of doped regions 260-280 and applying a particular reference voltage).

Another unique physical feature of the present disclosure is that the doped region 260 (as part of the protection diode 250) is formed to surround the doped region 270 in a cross-sectional view. If the doped region 260 is not formed, the doped region 270 would be physically connected directly to the substrate 210. This means that the substrate 210 may have been pulled to any voltage of the second reference voltage, in this case-2V. As described above, normal operation of many microelectronic components on CIS 10 requires that substrate 210 be placed at electrical ground. Therefore, a negative voltage of the substrate 210 due to the direct connection with the second reference voltage is also undesirable.

Here, the implementation of the doped region 260 surrounding the doped region 270 serves as an isolation barrier for the second reference voltage. Specifically, the P-doped region 270 forms another P/N junction with the N-doped region 260. Because the N-type doped region 260 is biased to a positive first reference voltage (e.g., 2.8V in this case) and the P-type doped region 270 is biased to a negative second reference voltage (e.g., 1.2V in this case), this P/N junction is still reverse biased, meaning that little current flows as a result. Thus, the substrate 210 is not affected by the negative second reference voltage to which the doped region 270 is biased. Further, the substrate 210 itself may be a P-type substrate, and because the substrate 210 surrounds the N-type doped region 260, the substrate 210 forms another P/N junction with the N-type doped region 260. Because the P-type substrate is at electrical ground (0 volts) and the N-type doped region 260 is biased to a positive voltage (e.g., 2.8V herein), the P/N junction itself is also reverse biased. This reverse biased P/N junction further shuts off any potential current flow between the substrate 210 and the second reference voltage source. Thus, the substrate 210 is further isolated from other potential electrical interference and still function properly as an electrical ground.

It should be understood that the particular values of the first reference voltage and/or the second reference voltage described above are not intended to be limiting unless explicitly stated otherwise. For example, instead of having 2.8V as its first reference voltage, other values of 2.5V, 3V or 3.3V may be used. As another example, instead of having-2V as its second reference voltage, other values of-2.5V, -3V, or-3.3V may be used.

Fig. 7-8 are schematic partial cross-sectional side views of a CIS 10 according to another embodiment of the present disclosure. In more detail, fig. 7 shows details of the CIS 10 as a stacked structure of three wafers bonded together: sensor wafer T1, logic wafer T2, and logic wafer T3, and fig. 8 shows an enlarged view of a portion of CIS 10. For reasons of consistency and clarity, similar components appearing in the embodiments of fig. 7-8 and similar components appearing in the embodiments of fig. 5-6 bear the same reference numerals.

Referring to fig. 7-8, sensor wafer T1 is bonded to logic wafer T2 through bonding interface 140 and logic wafer T2 is bonded to logic wafer T3 through bonding interface 150, such as through HBLs 160-190. As in the case of the embodiments of fig. 5-6, the light detecting pixel and one or more transistors 230 may be formed at least partially in the substrate 200, and the other transistors 240 and 245 may be formed at least partially in the substrate 210 and the substrate 220, respectively.

According to aspects of the present disclosure, the protection diode 250A is implemented in the CIS 10. In the embodiment shown in fig. 7-8, the protection diode 250A is implemented in the logic wafer T2, but it should be understood that in other embodiments, the protection diode 250A (or other examples of the protection diode 250A) may be implemented in the sensor wafer T1 or the logic wafer T3. Similar to the protection diode 250 of the embodiment corresponding to fig. 5-6, the protection diode 250A of the embodiment of fig. 7-8 includes a plurality of different doped regions for protecting the CIS 10 during fabrication and operation of the CIS 10. However, while the protection diode 250 includes three doped regions 260, 270, and 280, the protection diode 250A includes two doped regions 275 and 285. Doped region 275 is an N-type doped region embedded in substrate 210, and doped region 285 is a P-type doped region embedded in doped region 275. In some embodiments, doped region 275 includes a lightly doped N-well and a heavily doped N-type portion (the heavily doped N-type portion being located at or near the surface of substrate 210) and doped region 285 includes a heavily doped P-type portion (the heavily doped P-type portion being located at or near the surface of substrate 210). In cross-section, doped region 285 is surrounded by doped region 275 (except for the upper surface of doped region 285). Doped region 285 is electrically connected to the gate of pass transistor 230 through metal lines and vias of interconnect structures 310 and 320. The doped region 275 is electrically connected to a positive reference voltage, in this case 3.6V.

Although the structure and applied voltage reference between the protection diode 250 of fig. 5-6 and the protection diode 250A of fig. 7-8 are different, the protection diode 250A is still configured to maintain its P/N junction (e.g., one P/N junction formed by the doped region 285/275 and another P/N junction formed by the substrate 210 and the doped region 275) reverse biased regardless of the degree of voltage swing of the pass transistor 230. That is, when the voltage of pass transistor 230 swings between-1.2V and 3V, protection diode 250A still keeps substrate 210 from being pulled down to the negative voltage value of pass transistor 230. In addition, the protection diode 250A also protects the CIS 10 during the fabrication of the CIS 10, for example, during an etching process of the TSV 300 for forming the logic wafer T2. Similar to the protective diode 250 discussed above, the protective diode 250A may help to release plasma charges accumulated due to an etching or deposition process (which uses plasma), and thus, components of the CIS 10 are less likely to be damaged during fabrication of the CIS 10.

Fig. 9 is a schematic partial cross-sectional side view of a CIS 10 according to yet another embodiment of the present disclosure. Again, for reasons of consistency and clarity, similar components appearing in the embodiment of fig. 9 and similar components appearing in the embodiments of fig. 5-8 bear the same reference numerals.

In the embodiment of fig. 9, sensor wafer T1 is still bonded to logic wafer T2 through bonding interface 140, and logic wafer T2 is still bonded to logic wafer T3 through bonding interface 150, e.g., through HBLs 160-190. As in the embodiment of fig. 5-8, the light detecting pixel and one or more transistors 230 may be at least partially formed in the substrate 200, and the other transistors 240 and 245 may be at least partially formed in the substrate 210 and the substrate 220, respectively.

However, unlike the embodiment of fig. 5-8, the embodiment of fig. 9 implements a protection diode 250 in the sensor wafer T1. The protection diode 250 includes a doped region 260 embedded in the substrate 200, a doped region 270 embedded in the doped region 260, and a doped region 280 embedded in the P-type doped region 270. As in the case of the embodiments of fig. 5-6, doped regions 260 and 280 are doped with N-type dopants and doped region 270 is doped with P-type dopants. The doped regions 260 and 270 are electrically connected to a first reference voltage (e.g., 2.8V) and a second reference voltage (e.g., -2V), respectively, through vias and metal lines of the interconnect structure 310. Doped region 280 is electrically connected to the gate of pass transistor 230 through a via and metal line of interconnect structure 310. Again, other voltage reference values discussed above in connection with the embodiments of fig. 5-6 may also be used herein.

Similar to the protection diode 250 of the embodiment of fig. 5-6, the protection diode 250 herein utilizes the substrate 200 and doped region 260, doped region 270 and doped region 260, and doped region 270 and doped region 280 to form a P/N junction. And similar to the protection diode 250 of the embodiment of fig. 5-6, the structural configuration and electrical bias of the protection diode 250 herein also helps to maintain the P/N junction in reverse bias regardless of the degree of voltage swing of the pass transistor 230. In other words, the protection diode 250 helps isolate the substrate 210 from the substrate 210 being pulled down to a negative voltage by the pass transistor 230. In addition, the protection diode 250 also protects the CIS 10 during the fabrication of the CIS 10, for example, during an etching or deposition process of the TSV 300 for forming the logic wafer T2. Similar to the protective diode 250 of the embodiments of fig. 5-6 discussed above, the protective diode 250 herein may help to release plasma charges accumulated due to an etching or deposition process (which uses plasma), and thus, components of the CIS 10 are less likely to be damaged during fabrication of the CIS 10.

Fig. 10 is a schematic partial cross-sectional side view of a CIS 10 according to yet another embodiment of the present disclosure. Again, for reasons of consistency and clarity, similar components appearing in the embodiment of fig. 10 and similar components appearing in the embodiments of fig. 5-9 bear the same reference numerals.

In the embodiment of fig. 10, sensor wafer T1 is still bonded to logic wafer T2 through bonding interface 140, and logic wafer T2 is still bonded to logic wafer T3 through bonding interface 150, e.g., through HBLs 160-190. As in the case of the embodiments of fig. 5-9, the light detecting pixel and one or more transistors 230 may be formed at least partially in the substrate 200, and the other transistors 240 and 245 may be formed at least partially in the substrate 210 and the substrate 220, respectively.

However, unlike the embodiment of fig. 5-9, the embodiment of fig. 10 implements a protection diode 250 in logic wafer T3. The protection diode 250 includes a doped region 260 embedded in the substrate 220, a doped region 270 embedded in the doped region 260, and a doped region 280 embedded in the doped region 270. As in the case of the embodiments of fig. 5-6, doped regions 260 and 280 are doped with N-type dopants and doped region 270 is doped with P-type dopants. The doped regions 260 and 270 are electrically connected to a first reference voltage (e.g., 2.8V) and a second reference voltage (e.g., -2V), respectively, through vias and metal lines of the interconnect 330 of the logic wafer T3. Doped region 280 is electrically connected to the gate of pass transistor 230 through the vias and metal lines of interconnect structures 310-330. Again, other voltage reference values discussed above in connection with the embodiments of fig. 5-6 may also be used herein.

Similar to the protection diode 250 of the embodiment of fig. 5-6, the protection diode 250 herein utilizes the substrate 220 and doped region 260, doped region 270 and doped region 260, and doped region 270 and doped region 280 to form a P/N junction. And similar to the protection diode 250 of the embodiment of fig. 5-6, the structural configuration and electrical bias of the protection diode 250 herein also helps to maintain the P/N junction in reverse bias regardless of the degree of voltage swing of the pass transistor 230. In other words, the protection diode 250 helps isolate the substrate 210 from the substrate 210 being pulled down to a negative voltage by the pass transistor 230.

Fig. 11 is a flowchart illustrating a method 800 of manufacturing an image sensor device according to an embodiment of the present disclosure. The method 800 includes a step 810 of bonding a first side of a sensor wafer to a first side of a first logic wafer. The sensor wafer includes pixels configured to detect radiation entering the sensor wafer through a second side of the sensor wafer opposite the first side. The first logic wafer includes circuitry configured to operate the pixels. The sensor wafer or the first logic wafer includes a protection diode.

The method 800 includes thinning 820 the first logic wafer from a second side of the first logic wafer opposite the first side.

The method 800 includes a step 830 of forming a Through Substrate Via (TSV) in a first logic wafer. The protection diode protects the sensor wafer or the first logic wafer from damage during TSV formation.

The method 800 includes a step 840 of bonding a second side of the first logic wafer to the second logic wafer.

The method 800 includes a step 850 of thinning the sensor wafer from the second side of the sensor wafer.

In some embodiments, step 830 for forming a TSV includes: one or more etching or deposition processes using a plasma are performed. The protection diode protects the sensor wafer or the first logic wafer from plasma damage.

In some embodiments, prior to step 810 for bonding the first side of the sensor wafer to the first side of the first logic wafer, a protection diode is formed in the sensor wafer or the first logic wafer at least in part by: forming a first doped region in a substrate of a sensor wafer or in a substrate of a first logic wafer; forming a second doped region in the first doped region, wherein the second doped region has a different conductivity type than the first doped region; and forming a third doped region in the second doped region, wherein the third doped region has the same conductivity type as the first doped region.

In some embodiments, the sensor wafer includes a transfer gate.

It should be appreciated that method 800 may include further steps performed before, during, or after steps 810-850. For example, method 800 may include the step of electrically biasing the first doped region to a first reference voltage and the step of electrically biasing the second doped region to a second reference voltage that is different from the first reference voltage. One of the first reference voltage and the second reference voltage is a positive voltage, and the other of the first reference voltage and the second reference voltage is a negative voltage. As another example, the method 800 may include the step of electrically connecting the third doped region to the pass gate. As yet another example, the method 800 may include the step of electrically operating the image sensor device. The protection diode protects the image sensor device during electrical operation of the image sensor device. The image sensor device may be operated by applying a voltage between-M volts and N volts to the pass gate. The second reference voltage is a negative voltage more negative than-M volts. Other steps of method 800 may include steps of forming color filters and microlenses. For simplicity, these additional steps are not discussed in detail herein.

Fig. 12 illustrates an integrated circuit manufacturing system 900 according to an embodiment of the disclosure. The manufacturing system 900 includes a plurality of entities 902, 904, 906, 908, 910, 912, 914, 916 …, N connected by a communication network 918. The network 918 may be a single network or may be a variety of different networks, such as an intranet and the internet, and may include both wired and wireless communication channels.

In one embodiment, entity 902 represents a service system for manufacturing collaboration; entity 904 represents a user, such as a product engineer monitoring a product of interest; entity 906 represents an engineer, such as a process engineer controlling a process and related recipe, or an equipment engineer monitoring or adjusting the conditions and settings of a process tool; entity 908 represents a metrology tool for IC testing and measurement; entity 910 represents a semiconductor processing tool, such as an EUV tool for performing a photolithography process to define gate spacers of an SRAM device; entity 912 represents a virtual metrology module associated with processing tool 910; entity 914 represents a high-level process control module associated with process tool 910 as well as yet other process tools; and entity 916 represents a sampling module associated with processing tool 910.

Each entity may interact with other entities and may provide integrated circuit fabrication, process control, and/or computing capabilities to and/or receive such capabilities from other entities. Each entity may also include one or more computer systems that perform computations and perform automation. For example, the high-level processing control module of entity 914 can comprise a plurality of computer hardware with software instructions encoded therein. Computer hardware may include hard drives, flash drives, CD-ROMs, RAM memory, display devices (e.g., monitors), input/output devices (e.g., mice and keyboards). The software instructions may be written in any suitable programming language and may be designed to perform specific tasks.

Integrated circuit fabrication system 900 interfaces between entities for purposes of Integrated Circuit (IC) fabrication and advanced process control for IC fabrication. In an embodiment, advanced process control includes adjusting process conditions, settings, and/or recipes for one process tool for an associated wafer based on metrology results.

In another embodiment, metrology results are measured from a subset of processed wafers according to an optimal sampling rate determined based upon process quality and/or product quality. In yet another embodiment, metrology results are measured from selected fields and points of a subset of processed wafers according to an optimal sampling field/point determined based upon various characteristics of process quality and/or product quality.

One of the capabilities provided by IC fabrication system 900 may enable collaboration and information access in areas such as design, engineering and processing, metrology and advanced process control. Another capability provided by the IC fabrication system 900 may integrate the system between facilities, such as between a metrology tool and a processing tool. This integration enables the facility to coordinate its activities. For example, integrating the metrology tool and the processing tool may enable more efficient incorporation of manufacturing information into a manufacturing process or APC module, and wafer data from in-line or in-situ measurements may be implemented using metrology tools integrated into the associated processing tools.

The advanced photolithography processes, methods, and materials described above may be used in many applications, including applications in which transistors are implemented as fin field effect transistors (finfets). For example, the fins may be patterned to create relatively tight pitches between features, which the above disclosure is well suited for. Furthermore, spacers (also referred to as mandrels) used to form fins of a FinFET may be processed in accordance with the disclosure above. It should also be appreciated that the transistor may also be implemented using a multi-channel device, such as a Gate All Around (GAA) device. To the extent that the present disclosure relates to fin structures or FinFET devices, such discussion may apply equally to GAA devices.

The present disclosure may provide advantages over conventional devices. However, it should be understood that not all advantages are discussed herein, that different embodiments may provide different advantages, and that no particular advantage is required for any embodiment. One advantage is protection of the CIS device during its manufacture. As described above, the fabrication of the CIS device may include performing one or more processes involving the use of plasma, for example, an etching process for etching an opening through a substrate via, a metal deposition process filling the etched opening, or an ashing process. When plasma from these processes is exposed to various components (e.g., metallization features) of the CIS device, the CIS device may be damaged. By implementing the protection diode in the sensor wafer or in a logic wafer bonded to the sensor wafer, the plasma may be released or otherwise diffused by the protection diode, thereby reducing the likelihood of any damage to the CIS device by the plasma. This advantage is the inherent result of implementing a protection diode on an appropriate wafer prior to performing a plasma process.

Another advantage is protection of the CIS device during operation of the CIS device. As described above, some circuits (e.g., pass transistors of a sensor wafer) may swing between negative and positive voltage ranges. When the pass transistor swings to a negative voltage, the pass transistor may pull the substrate of the logic wafer down to a negative voltage, which is undesirable because the intended operation of the circuitry on the logic wafer assumes that the substrate is at electrical ground. Here, by electrically connecting the respective doped regions of the protection diode to the pass transistor and the predefined voltage reference, the P/N junction of the protection diode remains reverse biased, which prevents current flow, thereby reducing the likelihood that the substrate of the logic wafer will be pulled down to any negative voltage of the pass transistor. This advantage is another inherent consequence of the unique structural configuration of the protection diode and the particular biasing scheme applied therein. Other advantages may include compatibility with existing manufacturing processes, ease of implementation, and low cost.

One aspect of the present disclosure relates to an image sensor device. The image sensor device includes a first substrate including a plurality of pixels and at least one transistor. The image sensor device includes a second substrate bonded to the first substrate, the second substrate including circuitry for interacting with the pixels. The image sensor device includes a protection diode disposed in the first substrate or the second substrate. The protection diode includes: the semiconductor device includes a first doped region, a second doped region disposed within the first doped region, and a third doped region disposed within the second doped region. The first doped region and the third doped region have the same conductivity type. The second doped region has a different conductivity type than the first doped region and the third doped region. The third doped region is electrically coupled to a transistor of the first substrate.

Another aspect of the present disclosure relates to an image sensor device. The image sensor device includes a sensor substrate including a plurality of pixels and a transfer gate. The pixels are configured to detect radiation entering the sensor substrate through the backside of the sensor substrate. The image sensor device includes a first non-sensor substrate bonded to the sensor substrate through a front side of the sensor substrate, the first non-sensor substrate including circuitry configured to operate the pixels. The image sensor device includes a second non-sensor substrate bonded to the first non-sensor substrate such that the first non-sensor substrate is bonded between the sensor substrate and the second non-sensor substrate, the second non-sensor substrate including other circuitry configured to operate the pixels. The image sensor device includes one or more protection diodes implemented in the sensor substrate, the first non-sensor substrate, or the second non-sensor substrate. Each of the one or more protection diodes includes: the first doped well, the second doped well located within the first doped well, and the third doped well located within the second doped well. The second doped well has a different conductivity type than the first doped well and the third doped well. The first doped well is electrically connected to a first reference voltage. The second doped well is electrically connected to a second reference voltage different from the first reference voltage. The third doped well is electrically connected to the pass gate.

Yet another aspect of the disclosure relates to a method. The first side of the sensor wafer is bonded to the first side of the first logic wafer. The sensor wafer includes pixels configured to detect radiation entering the sensor wafer through a second side of the sensor wafer opposite the first side. The first logic wafer includes circuitry configured to operate the pixels. The sensor wafer or the first logic wafer includes a protection diode. The first logic wafer is thinned from a second side of the first logic wafer opposite the first side. Through Substrate Vias (TSVs) are formed in the first logic wafer. The protection diode protects the sensor wafer or the first logic wafer from damage during TSV formation. The second side of the first logic wafer is bonded to the second logic wafer. The sensor wafer is thinned from the second side of the sensor wafer.

The foregoing outlines features of some embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Example 1 is an image sensor device, comprising: a first substrate including a plurality of pixels and at least one transistor; a second substrate bonded to the first substrate, the second substrate including circuitry for interacting with the pixels; and a protection diode disposed within the first substrate or the second substrate, the protection diode including: a first doped region, a second doped region disposed within the first doped region, and a third doped region disposed within the second doped region; wherein: the first doped region and the third doped region have the same conductivity type; the second doped region has a different conductivity type than the first doped region and the third doped region; and the third doped region is electrically coupled to a transistor of the first substrate.

Example 2 is the image sensor device of example 1, wherein: the first doped region is electrically coupled to a first reference voltage; and the second doped region is electrically coupled to a second reference voltage that is different from the first reference voltage.

Example 3 is the image sensor device of example 2, wherein the first reference voltage is a positive voltage and the second reference voltage is a negative voltage.

Example 4 is the image sensor device of example 3, wherein: when the image sensor device is operating, the voltage associated with the transistor swings from-M volts to N volts; and the second reference voltage is more negative than-M volts.

Example 5 is the image sensor device of example 1, wherein: the transistor includes a pass gate.

Example 6 is the image sensor device of example 1, wherein: the protection diode is implemented within the first substrate but not within the second substrate; or the protection diode is implemented within the second substrate but not within the first substrate.

Example 7 is the image sensor device of example 1, wherein: a first instance of the protection diode is implemented within the first substrate; and a second instance of the protection diode is implemented within the second substrate.

Example 8 is the image sensor device of example 1, wherein: the first substrate includes a first surface and a second surface opposite the first surface; the first substrate includes a plurality of pixels configured to detect light entering the first substrate from the first surface; and the second substrate is bonded to the second surface of the first substrate.

Example 9 is the image sensor device of example 1, further comprising: and a third substrate bonded to the second substrate or the first substrate.

Example 10 is the image sensor device of example 9, wherein: the first substrate is part of a sensor wafer; the second substrate is part of a first logic wafer; the third substrate is part of a second logic wafer; a first surface of the first logic wafer is bonded to the second logic wafer; and a second surface of the first logic wafer is bonded to the sensor wafer.

Example 11 is the image sensor device of example 9, wherein: the first substrate is part of a first sensor wafer; the third substrate is part of a second sensor wafer; the second substrate is part of a logic wafer; and the first sensor wafer is bonded to the logic wafer through the second sensor wafer.

Example 12 is an image sensor device, comprising: a sensor substrate comprising a plurality of pixels and transfer gates, wherein the pixels are configured to detect radiation entering the sensor substrate through a backside of the sensor substrate; a first non-sensor substrate bonded to the sensor substrate through a front side of the sensor substrate, the first non-sensor substrate comprising circuitry configured to operate the pixels; a second non-sensor substrate bonded to the first non-sensor substrate such that the first non-sensor substrate is bonded between the sensor substrate and the second non-sensor substrate, the second non-sensor substrate including other circuitry configured to operate the pixel; one or more protection diodes implemented in the sensor substrate, the first non-sensor substrate, or the second non-sensor substrate; wherein: each of the one or more protection diodes includes: a first doped well, a second doped well located within the first doped well, and a third doped well located within the second doped well; the second doped well has a different conductivity type than the first doped well and the third doped well; the first doped well is electrically connected to a first reference voltage; the second doped well is electrically connected to a second reference voltage different from the first reference voltage; and the third doped well is electrically connected to the pass gate.

Example 13 is the image sensor device of example 12, wherein: the first reference voltage is a positive voltage; the second reference voltage is a negative voltage; and during operation of the image sensor device, the pass gate has a voltage in a range between-M volts and N volts, wherein-M volts is a negative voltage less negative than the second reference voltage.

Example 14 is the image sensor device of example 12, wherein the one or more protection diodes include at least a first protection diode embedded in the sensor substrate and a second protection diode embedded in the first non-sensor substrate.

Example 15 is a method of manufacturing an image sensor device, comprising: bonding a first side of a sensor wafer to a first side of a first logic wafer, wherein the sensor wafer comprises pixels configured to detect radiation entering the sensor wafer through a second side of the sensor wafer opposite the first side, wherein the first logic wafer comprises circuitry configured to operate the pixels, and wherein the sensor wafer or the first logic wafer comprises protection diodes; thinning the first logic wafer from a second side of the first logic wafer opposite the first side; forming a Through Substrate Via (TSV) in the first logic wafer, wherein the protection diode protects the sensor wafer or the first logic wafer from damage during the TSV formation; bonding a second side of the first logic wafer to a second logic wafer; and thinning the sensor wafer from the second side of the sensor wafer.

Example 16 is the method of example 15, wherein: forming the TSV includes: performing one or more etching or deposition processes using a plasma; and the protection diode protects the sensor wafer or the first logic wafer from the plasma.

Example 17 is the method of example 15, further comprising: forming the protection diode in the sensor wafer or in the first logic wafer prior to bonding the first side of the sensor wafer to the first side of the first logic wafer at least in part by: forming a first doped region in a substrate of the sensor wafer or in a substrate of the first logic wafer; forming a second doped region in the first doped region, wherein the second doped region has a different conductivity type than the first doped region; and forming a third doped region in the second doped region, wherein the third doped region has the same conductivity type as the first doped region.

Example 18 is the method of example 17, wherein the sensor wafer includes a transfer gate, and wherein the method further comprises: electrically biasing the first doped region to a first reference voltage; electrically biasing the second doped region to a second reference voltage different from the first reference voltage, wherein one of the first reference voltage and the second reference voltage is a positive voltage and the other of the first reference voltage and the second reference voltage is a negative voltage; and electrically connecting the third doped region to the pass gate.

Example 19 is the method of example 18, further comprising: the image sensor device is electrically operated, wherein the protection diode protects the image sensor device during the electrical operation of the image sensor device.

Example 20 is the method of example 19, wherein: electrically operating the image sensor device includes: applying a voltage between-M volts and N volts to the pass gate; and the second reference voltage is a negative voltage more negative than-M volts.

Claims

1. An image sensor device, comprising:

a first substrate including a plurality of pixels and at least one transistor;

a second substrate bonded to the first substrate, the second substrate including circuitry for interacting with the pixels; and

a protection diode disposed within the first substrate or the second substrate, the protection diode comprising: a first doped region, a second doped region disposed within the first doped region, and a third doped region disposed within the second doped region;

wherein:

the first doped region and the third doped region have the same conductivity type;

the second doped region has a different conductivity type than the first doped region and the third doped region; and is also provided with

The third doped region is electrically coupled to a transistor of the first substrate.

2. The image sensor device of claim 1, wherein:

the first doped region is electrically coupled to a first reference voltage; and is also provided with

The second doped region is electrically coupled to a second reference voltage that is different from the first reference voltage.

3. The image sensor device of claim 2, wherein the first reference voltage is a positive voltage and the second reference voltage is a negative voltage.

4. The image sensor device of claim 3, wherein:

when the image sensor device is operating, the voltage associated with the transistor swings from-M volts to N volts; and is also provided with

The second reference voltage is more negative than-M volts.

5. The image sensor device of claim 1, wherein: the transistor includes a pass gate.

6. The image sensor device of claim 1, wherein:

the protection diode is implemented within the first substrate but not within the second substrate; or alternatively

The protection diode is implemented within the second substrate but not within the first substrate.

7. The image sensor device of claim 1, wherein:

a first instance of the protection diode is implemented within the first substrate; and is also provided with

A second instance of the protection diode is implemented within the second substrate.

8. The image sensor device of claim 1, wherein:

the first substrate includes a first surface and a second surface opposite the first surface;

the first substrate includes a plurality of pixels configured to detect light entering the first substrate from the first surface; and is also provided with

The second substrate is bonded to a second surface of the first substrate.

9. An image sensor device, comprising:

a sensor substrate comprising a plurality of pixels and transfer gates, wherein the pixels are configured to detect radiation entering the sensor substrate through a backside of the sensor substrate;

a first non-sensor substrate bonded to the sensor substrate through a front side of the sensor substrate, the first non-sensor substrate comprising circuitry configured to operate the pixels;

a second non-sensor substrate bonded to the first non-sensor substrate such that the first non-sensor substrate is bonded between the sensor substrate and the second non-sensor substrate, the second non-sensor substrate including other circuitry configured to operate the pixel;

One or more protection diodes implemented in the sensor substrate, the first non-sensor substrate, or the second non-sensor substrate;

wherein:

each of the one or more protection diodes includes: a first doped well, a second doped well located within the first doped well, and a third doped well located within the second doped well;

the second doped well has a different conductivity type than the first doped well and the third doped well;

the first doped well is electrically connected to a first reference voltage;

the second doped well is electrically connected to a second reference voltage different from the first reference voltage; and is also provided with

The third doped well is electrically connected to the pass gate.

10. A method of manufacturing an image sensor device, comprising:

bonding a first side of a sensor wafer to a first side of a first logic wafer, wherein the sensor wafer comprises pixels configured to detect radiation entering the sensor wafer through a second side of the sensor wafer opposite the first side, wherein the first logic wafer comprises circuitry configured to operate the pixels, and wherein the sensor wafer or the first logic wafer comprises protection diodes;

Thinning the first logic wafer from a second side of the first logic wafer opposite the first side;

forming a through substrate via TSV in the first logic wafer, wherein the protection diode protects the sensor wafer or the first logic wafer from damage during the TSV formation;

bonding a second side of the first logic wafer to a second logic wafer; and

the sensor wafer is thinned from a second side of the sensor wafer.