CN116564836A - Package structure and method for forming the same - Google Patents
Package structure and method for forming the same Download PDFInfo
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- CN116564836A CN116564836A CN202310688252.7A CN202310688252A CN116564836A CN 116564836 A CN116564836 A CN 116564836A CN 202310688252 A CN202310688252 A CN 202310688252A CN 116564836 A CN116564836 A CN 116564836A
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- Prior art keywords
- metal substrate
- tin
- ink pattern
- semiconductor chip
- solder
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- 238000000034 method Methods 0.000 title claims abstract description 65
- 229910052751 metal Inorganic materials 0.000 claims abstract description 126
- 239000002184 metal Substances 0.000 claims abstract description 126
- 229910000679 solder Inorganic materials 0.000 claims abstract description 110
- 239000000758 substrate Substances 0.000 claims abstract description 105
- 239000004065 semiconductor Substances 0.000 claims abstract description 69
- 239000000463 material Substances 0.000 claims abstract description 26
- 229920003023 plastic Polymers 0.000 claims abstract description 18
- 239000004033 plastic Substances 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000004806 packaging method and process Methods 0.000 claims abstract description 12
- 238000003466 welding Methods 0.000 claims abstract description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 7
- 238000011161 development Methods 0.000 claims description 7
- 238000000465 moulding Methods 0.000 claims description 7
- 229910052718 tin Inorganic materials 0.000 claims description 7
- NTSDHVIXFWZYSM-UHFFFAOYSA-N [Ag].[Sb].[Sn] Chemical compound [Ag].[Sb].[Sn] NTSDHVIXFWZYSM-UHFFFAOYSA-N 0.000 claims description 6
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 claims description 6
- PQIJHIWFHSVPMH-UHFFFAOYSA-N [Cu].[Ag].[Sn] Chemical compound [Cu].[Ag].[Sn] PQIJHIWFHSVPMH-UHFFFAOYSA-N 0.000 claims description 6
- PSMFTUMUGZHOOU-UHFFFAOYSA-N [In].[Sn].[Bi] Chemical compound [In].[Sn].[Bi] PSMFTUMUGZHOOU-UHFFFAOYSA-N 0.000 claims description 6
- HRPKYGWRFPOASX-UHFFFAOYSA-N [Zn].[Ag].[Sn] Chemical compound [Zn].[Ag].[Sn] HRPKYGWRFPOASX-UHFFFAOYSA-N 0.000 claims description 6
- WGCXSIWGFOQDEG-UHFFFAOYSA-N [Zn].[Sn].[In] Chemical compound [Zn].[Sn].[In] WGCXSIWGFOQDEG-UHFFFAOYSA-N 0.000 claims description 6
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 claims description 6
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 claims description 6
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 claims description 6
- 229920000642 polymer Polymers 0.000 claims description 6
- 229910000969 tin-silver-copper Inorganic materials 0.000 claims description 6
- 238000012545 processing Methods 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 238000005520 cutting process Methods 0.000 claims description 2
- 238000007789 sealing Methods 0.000 claims description 2
- 230000007547 defect Effects 0.000 abstract description 4
- 229920005989 resin Polymers 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- -1 polybutylene terephthalate Polymers 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000032798 delamination Effects 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229920000098 polyolefin Polymers 0.000 description 2
- 229920002635 polyurethane Polymers 0.000 description 2
- 239000004814 polyurethane Substances 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- 239000004695 Polyether sulfone Substances 0.000 description 1
- 239000004698 Polyethylene Substances 0.000 description 1
- 239000004743 Polypropylene Substances 0.000 description 1
- 239000004372 Polyvinyl alcohol Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000005038 ethylene vinyl acetate Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920001200 poly(ethylene-vinyl acetate) Polymers 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 229920002577 polybenzoxazole Polymers 0.000 description 1
- 229920001707 polybutylene terephthalate Polymers 0.000 description 1
- 239000004417 polycarbonate Substances 0.000 description 1
- 229920000515 polycarbonate Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920006393 polyether sulfone Polymers 0.000 description 1
- 229920000573 polyethylene Polymers 0.000 description 1
- 229920000139 polyethylene terephthalate Polymers 0.000 description 1
- 239000005020 polyethylene terephthalate Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920001155 polypropylene Polymers 0.000 description 1
- 229920002451 polyvinyl alcohol Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000010008 shearing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229920005992 thermoplastic resin Polymers 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
- H01L21/4875—Connection or disconnection of other leads to or from bases or plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
Abstract
The method comprises providing a metal substrate, etching the front surface of the metal substrate, and forming multiple grooves in the metal substrate; forming a plurality of discrete ink pattern layers on the front surface of the metal substrate outside the groove, wherein the ink pattern layers are provided with through holes exposing the bottoms of the corresponding grooves; filling the grooves and the through holes with solder materials to form solder columns; providing a semiconductor chip; flip-chip the semiconductor chip on the front surface of the metal substrate, and welding the bonding pads on the functional surface of the semiconductor chip and the tops of the corresponding solder columns together; forming a plastic layer for plastic packaging the front surface of the metal substrate, the semiconductor chip and the ink pattern layer; and removing part of the metal substrate along the back surface of the metal substrate to form a plurality of metal pins electrically connected with the bottoms of the corresponding solder columns, so that layering defects of the formed solder columns, the metal substrate and the semiconductor chip are prevented.
Description
Technical Field
The present disclosure relates to semiconductor packaging, and more particularly, to a packaging structure and a method for forming the same.
Background
Flip Chip (FC) is a packaging technology commonly used for Chip packaging. The existing process of packaging chips by flip chip technology generally comprises: providing a substrate, wherein the substrate is used for carrying and fixing chips and plays a role of electric interconnection; providing a semiconductor chip, wherein the semiconductor chip comprises a functional surface and a non-functional surface opposite to the functional surface, and the functional surface is provided with a raised metal column and a solder layer positioned on the top of the metal column; flip-chip mounting a semiconductor chip on the upper surface of the substrate; and welding the solder layer on the functional surface of the semiconductor chip and the substrate together through a reflow soldering technology.
However, the existing packaging structure can deform and expand in the reflow soldering process, so that delamination (ack) defects are easily generated between the metal posts and the substrate, and the electrical performance is affected.
Disclosure of Invention
Some embodiments of the present application provide a method for forming a package structure, including:
providing a metal substrate comprising opposite front and back surfaces;
etching the front surface of the metal substrate to form a plurality of grooves in the metal substrate;
forming a plurality of discrete ink pattern layers on the front surface of the metal substrate outside the groove, wherein the ink pattern layers are provided with through holes exposing the bottoms of the corresponding grooves;
filling the grooves and the through holes with solder materials to form solder columns;
providing a semiconductor chip, wherein the semiconductor chip comprises a functional surface and a back surface which are opposite, and the functional surface is provided with a plurality of bonding pads;
flip-chip the semiconductor chip on the front surface of the metal substrate, and welding the bonding pads on the functional surface of the semiconductor chip and the tops of the corresponding solder columns together;
forming a plastic layer for plastic packaging the front surface of the metal substrate, the semiconductor chip and the ink pattern layer;
and removing part of the metal substrate along the back surface of the metal substrate to form a plurality of metal pins electrically connected with the bottoms of the corresponding solder columns.
In some embodiments, the side walls of the recess are stepped.
In some embodiments, the sidewall of the recess has at least one step, and the ink pattern layer spans the at least one step surface and a portion of the front surface of the metal substrate outside the recess.
In some embodiments, the recess is formed using a multi-step etching process.
In some embodiments, the material of the ink graphics layer is a photosensitive polymer.
In some embodiments, the ink pattern forming process includes: forming a plurality of discrete photosensitive ink film layers on the front surface of the metal substrate, wherein each photosensitive ink film layer is filled with a corresponding groove and covers the front surface of the metal substrate of the part outside the groove; and sequentially carrying out an exposure process and a development process on the photosensitive ink film layer, removing part of the photosensitive ink film layer, forming a plurality of discrete ink pattern layers on the front surface of the metal substrate outside the groove, and forming through holes exposing the bottoms of the corresponding grooves in the ink pattern layers.
In some embodiments, a pre-bake treatment is performed before and/or after the development process.
In some embodiments, the material of the solder column is one or more of tin, tin silver, tin lead, tin silver copper, tin silver zinc, tin bismuth indium, tin gold, tin copper, tin zinc indium, or tin silver antimony.
In some embodiments, the top surface of the solder column is higher than the top surface of the ink pattern layer, and the solder column is formed using a spot welding process.
In some embodiments, after the semiconductor chip is flipped over the front side of the metal substrate, a reflow process is performed to solder the pads on the functional side of the semiconductor chip with the corresponding top of the solder columns.
In some embodiments, after bonding the pads of the functional surface of the semiconductor chip with the corresponding solder column tops, further comprising: and curing the ink pattern layer.
In some embodiments, the metal substrate includes a plurality of package regions and scribe line regions between the package regions, and the step of forming the grooves, the ink pattern layer, the solder columns, the semiconductor chip, the plastic layer, and the metal pins is performed simultaneously in each of the package regions, the plastic layer also covering the front surface of the metal substrate of the scribe line regions; after the metal pins are formed, the plastic sealing layer is cut along the cutting channel area, so that a plurality of discrete packages are formed.
Some embodiments of the present application further provide a packaging structure, including:
a semiconductor chip comprising opposite functional and back surfaces, the functional surface having pads;
solder columns protruding from the functional surface of the semiconductor chip and electrically connected with the bonding pads;
an ink pattern layer coated on the side wall surface of the solder column;
a plastic layer coating the semiconductor chip and the ink pattern layer;
and the metal pins are positioned on the ink pattern layer and the surface, far away from the functional surface, of the solder column and are electrically connected with the solder column.
In some embodiments, the thickness of the ink pattern layer is less than the height of the solder columns.
In some embodiments, a surface of the solder column remote from the functional face is raised from a surface of the ink pattern layer remote from the functional face.
In some embodiments, the contact surfaces of the metal pins with the ink pattern layer and the solder columns are stepped.
In some embodiments, the material of the ink graphics layer is a photosensitive polymer; the material of the solder column is one or more of tin, tin silver, tin lead, tin silver copper, tin silver zinc, tin bismuth indium, tin gold, tin copper, tin zinc indium or tin silver antimony.
In the method for forming the package structure according to the foregoing embodiments of the present application, after providing a metal substrate, etching a front surface of the metal substrate, and forming a plurality of grooves in the metal substrate; forming a plurality of discrete ink pattern layers on the front surface of the metal substrate outside the groove, wherein the ink pattern layers are provided with through holes exposing the bottoms of the corresponding grooves; filling the grooves and the through holes with solder materials to form solder columns; providing a semiconductor chip, wherein the semiconductor chip comprises a functional surface and a back surface which are opposite, and the functional surface is provided with a plurality of bonding pads; flip-chip the semiconductor chip on the front surface of the metal substrate, and welding the bonding pads on the functional surface of the semiconductor chip and the tops of the corresponding solder columns together; forming a plastic layer for plastic packaging the front surface of the metal substrate, the semiconductor chip and the ink pattern layer; and removing part of the metal substrate along the back surface of the metal substrate to form a plurality of metal pins electrically connected with the bottoms of the corresponding solder columns. Compared with the prior art that the metal columns (the materials are generally copper and tungsten) are connected, when the solder columns are formed, and the solder pads on the functional surfaces of the semiconductor chips are welded with the tops of the corresponding solder columns, the solder columns have certain flowability, so that the solder columns have certain buffer action with the metal substrate and the semiconductor chips, stress effects caused by different thermal expansion coefficients of different materials in the process of forming the solder columns are reduced, and layering (crack) defects (such as displacement or separation of the solder columns from the metal substrate and/or the semiconductor chips) of the formed solder columns and the metal substrate and the semiconductor chips are prevented, and the electrical performance of the packaging structure is improved. And, in the process of forming the solder columns, the solder columns are defined by the grooves and the ink pattern layer, thereby ensuring the shape and position of the solder columns and preventing short circuits between adjacent solder columns.
Drawings
Fig. 1-10 are schematic structural diagrams illustrating a process of forming a package structure according to some embodiments of the invention.
Detailed Description
The following detailed description of specific embodiments of the present application refers to the accompanying drawings. In describing embodiments of the present application in detail, the schematic drawings are not necessarily to scale and are merely illustrative and should not be taken as limiting the scope of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
Some embodiments of the present application first provide a method for forming a package structure, and the method is described in detail below with reference to the accompanying drawings.
Referring to fig. 1, a metal substrate 100 is provided, the metal substrate 100 including opposite front and back surfaces.
The metal substrate 100 serves as a platform for subsequent processes on the one hand, and the metal substrate 100 is subsequently used for forming metal pins electrically connected with solder columns on the other hand.
The metal substrate 100 includes opposite front and back surfaces, and the front surface is provided with a semiconductor chip in a reverse manner.
In some embodiments, the material of the metal substrate 100 is one or more of W, al, cu, ti, ag, au, pt, ni.
In some embodiments, the metal substrate 100 may include a plurality of package regions (not shown) and scribe line regions (not shown) between the package regions, where the semiconductor chip is subsequently flip-chip mounted, and the scribe line regions are subsequently used to divide the package structure into a plurality of discrete packages.
Referring to fig. 2, the front surface of the metal substrate 100 is etched, and a plurality of grooves 101 are formed in the metal substrate 100.
The grooves 101 are then used in conjunction with the formed ink pattern layer to define the location and shape of the solder columns formed and to prevent shorting between adjacent solder columns.
In some embodiments, the sidewall of the groove 101 is stepped (see fig. 2). The side wall of the groove 101 has at least one step, the surface of which is higher than the bottom surface of the groove 101, and the number of steps of the side wall of the groove 101 may be one or more (two or more), and only one step is shown as an example in fig. 2 for illustration of the side wall of the groove 101. When the side wall of the groove 101 is in a step shape, the ink pattern layer can span the surface of the step (at least one) and the surface of the front surface of the metal substrate outside the groove when the ink pattern layer is formed subsequently, so that the contact area between the bottom of the ink pattern layer and the surface of the front surface of the metal substrate 100 is increased, the firmness between the formed ink pattern layer and the metal substrate 100 is improved, the ink pattern layer can be prevented from being deviated or separated from the surface of the front surface of the metal substrate 100, and the position of a subsequently formed solder column is well defined.
In other embodiments, the side walls of the groove may be perpendicular to the bottom of the groove, or the side walls of the groove may be inclined outward at an angle to the bottom of the groove.
The metal substrate 100 is etched using an etching process, and a groove 101 is formed in the metal substrate 100. The etching process includes a wet etching process or a dry etching process. A patterned mask layer (not shown), such as a patterned dry film or photoresist layer, is formed on the front surface of the metal substrate 100 prior to etching the metal substrate 100, the patterned mask layer serving as a mask when etching the metal substrate 100.
In an embodiment, when the sidewall of the recess 101 is stepped, the recess 101 having the sidewall stepped may be formed by a multi-step etching process. In a specific embodiment, when the sidewall of the groove 101 has a step, the forming process of the groove 101 includes: performing first-step etching to remove part of the metal substrate 100, and forming a first sub-groove in the metal substrate 100, wherein the first sub-groove has a first depth; and performing a second step of etching to remove part of the depth of the metal substrate 100 outside the first sub-groove, so as to form a second sub-groove communicated with the first sub-groove, wherein the second sub-groove has a second depth which is smaller than the first depth, and the second sub-groove and the first sub-groove form the groove 101.
Referring to fig. 3 and 4, a plurality of discrete ink pattern layers 103 are formed on the front surface of the metal substrate 100 outside the grooves 101, and the ink pattern layers 103 have through holes 102 therein exposing the corresponding grooves 101.
The ink pattern layer 103 is in a hollow ring shape, a through hole 102 exposing the bottom of the groove 101 is formed in the middle of the ink pattern layer 103, and the ink pattern layer 103 is used for defining the position, the height and the shape of a subsequently formed solder column in cooperation with the groove 101.
In one embodiment, the material of the ink pattern layer 103 is a photosensitive polymer, such as a photosensitive resin. Thus, by forming a photosensitive ink film layer, the ink pattern layer 103 having the through-holes 102 can be formed after sequentially performing an exposure process and a development process on the ink film layer.
In some embodiments, the forming of the ink pattern layer 103 includes: referring to fig. 3, a plurality of discrete photosensitive ink film layers 103a are formed on the front surface of the metal substrate 100, each of the photosensitive ink film layers 103a filling a corresponding one of the grooves 101 and covering a portion of the front surface of the metal substrate 100 outside the groove 101; referring to fig. 4, the photosensitive ink film layer is sequentially subjected to an exposure process and a development process, a portion of the photosensitive ink film layer is removed, a plurality of discrete ink pattern layers 103 are formed on the front surface of the metal substrate outside the groove 101, and the ink pattern layers 103 have through holes 102 exposing the bottoms of the corresponding grooves 101.
In some embodiments, the photosensitive ink film layer 103a may be formed by a screen printing process. In other embodiments, the photosensitive ink film layer 103a may also be formed by a spin-coating process.
In some embodiments, a pre-bake treatment is performed before and/or after the development process to maintain a certain toughness of the formed ink pattern layer 103, but not fully cure, and then the ink pattern layer 103 maintains a certain elasticity when forming the solder columns, and the ink pattern layer 103 may be further shrunk during the subsequent reflow process, so as to combine with the solder columns and avoid voids between the ink pattern layer 103 and the solder columns.
In some embodiments, the side wall of the groove 101 has at least one step, and the ink pattern layer 103 spans across the at least one step surface and a part of the front surface of the metal substrate 100 outside the groove 101, so that the contact area between the bottom of the ink pattern layer 103 and the front surface of the metal substrate 100 is increased, the firmness between the formed ink pattern layer 103 and the metal substrate 100 is improved, and the ink pattern layer 103 can be better prevented from being deviated or separated from the front surface of the metal substrate 100, so that a better defining effect is generated on the position of a subsequently formed solder column.
In some specific embodiments, when the number of steps is one, the ink pattern layer 103 spans over the step surface and a portion of the front surface of the metal substrate 100 outside the groove 101. In other embodiments, when the number of steps is plural, the ink pattern layer 103 spans over one or adjacent ones of the step surfaces located near the front surface of the metal substrate 100 and a part of the front surface of the metal substrate 100 outside the groove 101, specifically, when the number of steps is two, the ink pattern layer 103 may cover only the uppermost one or two or three all surfaces, or when the number of steps is three, the ink pattern layer 103 may cover only the uppermost one, the upper adjacent two or three all surfaces.
Referring to fig. 5, the grooves 101 and the through holes 102 (refer to fig. 4) are filled with solder material, forming solder columns 104.
The solder columns 104 are used to electrically connect the semiconductor chip to be subsequently flipped and the metal pins formed from part of the metal substrate 100.
The material of the solder column 104 is solder, and in some embodiments, the material of the solder column 104 is one or more of tin, tin silver, tin lead, tin silver copper, tin silver zinc, tin bismuth indium, tin gold, tin copper, tin zinc indium, or tin silver antimony.
In one embodiment, the top surface of the solder columns 104 is higher than the top surface of the ink pattern 103 layer, facilitating subsequent flip-chip bonding of the semiconductor chip to the solder columns.
In one embodiment, the solder columns 104 are formed using a spot welding process. In other embodiments, the solder columns 104 may be formed using a screen printing process.
Referring to fig. 6, a semiconductor chip 200 is provided, the semiconductor chip 200 including opposite functional surfaces and a back surface, the functional surfaces having a plurality of pads (not shown in the drawing); the semiconductor chip 200 is flip-chip mounted on the front surface of the metal substrate 100, and the bonding pads on the functional surface of the semiconductor chip 200 are soldered with the tops of the corresponding solder columns 104.
The semiconductor chip 200 has an integrated circuit (not shown) formed therein (having a specific function), and pads of the functional surface are electrically connected to the integrated circuit. The bonding pad is made of one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold and silver. In some embodiments, the semiconductor chip 200 includes, but is not limited to, a sensor chip, a power chip, a signal processing chip, a logic control chip, a memory chip, or a radio frequency chip.
The semiconductor chip 200 is flip-chip mounted on the front surface of the metal substrate 100, the functional surface of the semiconductor chip 200 is opposite to the front surface of the metal substrate 100, the bonding pads on the functional surface of the semiconductor chip 200 are contacted with the tops of the corresponding solder columns 104, and then reflow processing is performed to bond the bonding pads on the functional surface of the semiconductor chip 200 with the tops of the corresponding solder columns 104. In some embodiments, the temperature of the reflow process is 180 ℃ to 260 ℃.
In this application, compared with the conventional connection of the metal columns (generally copper and tungsten) by the solder columns 104 formed by the method, when the solder columns 104 are soldered together on the tops of the corresponding solder columns 104 during the reflow soldering (or reflow processing) process of forming the solder columns 104, the solder columns 104 have a certain flowability, so that the solder columns 104 have a certain buffer effect with the metal substrate 100 and the semiconductor chip 200, and stress effects caused by different thermal expansion coefficients of different materials during the formation of the solder columns 104 are reduced, thereby preventing the formed solder columns 104 and the metal substrate 100 and the semiconductor chip 200 from generating delamination (crack) defects (such as displacement or detachment of the solder columns 104 from the metal substrate 100 and/or the semiconductor chip 200), and improving the electrical performance of the package structure. Also, during the formation of the solder columns 104, the solder columns are defined by the grooves 101 and the ink pattern layer 103, thereby ensuring the shape and position of the solder columns 104 and preventing short circuits between adjacent solder columns 104.
In some embodiments, referring to fig. 7, after bonding the pads of the functional surface of the semiconductor chip 200 and the tops of the corresponding solder columns 104 together, the method further includes: the ink pattern layer 103 is subjected to a curing treatment to enhance ink hardness and adhesion.
The ink pattern layer 103 may be further shrunk in the height direction and the width direction at the time of the curing process to better fasten the solder column.
In some embodiments, the temperature of the curing process is 155 ℃ to 170 ℃.
Referring to fig. 8, a molding layer 105 is formed to mold the front surface of the metal substrate 100, the semiconductor chip 200, and the ink pattern layer 103.
The molding layer 105 serves to protect the semiconductor chip 200 and the connection pads between the semiconductor chip 200 and the metal substrate 100 from moisture, ionic contaminants, radiation, and harmful operation environments such as mechanical stretching, shearing, twisting, vibration, etc.
The material of the plastic layer 105 may be a silicon-based resin material, a thermoplastic resin material, a thermosetting resin material, or an ultraviolet-curable resin material. In a specific embodiment, the material of the plastic layer 105 is epoxy resin, polyimide resin, benzocyclobutene resin, or polybenzoxazole resin; or may be polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol.
In some embodiments, forming the plastic layer 105 includes an injection molding process or a transfer molding process.
Referring to fig. 9, a portion of the metal substrate 100 (refer to fig. 8) is removed along a back surface of the metal substrate, forming a plurality of metal pins 106 electrically connected to bottoms of corresponding solder columns 104.
The metal pins 106 are formed to cover the solder columns 104 and the bottom surface of the ink pattern layer 103.
A wet or dry etching process is used to remove a portion of the metal substrate 100. Forming a patterned mask layer on the back surface of the metal substrate 100 before removing a portion of the metal substrate 100, the patterned mask layer having a plurality of openings exposing a portion of the back surface of the metal substrate, the patterned mask layer being a patterned photoresist layer or a dry film; and etching and removing part of the metal substrate by taking the patterned mask layer as a mask to form a plurality of metal pins 106 electrically connected with the bottoms of the corresponding solder columns 104.
In some embodiments, when the metal substrate 100 includes a plurality of package regions and scribe line regions between the package regions, the steps of forming the grooves 101, the ink pattern layer 103, the solder columns 104, the semiconductor chip 200, the molding layer 105, and the metal pins 106 are performed simultaneously in each of the package regions, the forming of the molding layer 105 also covers the front surface of the metal substrate 100 of the scribe line regions; referring to fig. 10, after the metal pins 106 are formed, the molding layer 105 is cut along the scribe line region to form a plurality of discrete package structures.
Some embodiments of the present application further provide a package structure, referring to fig. 9 or fig. 10, including:
a semiconductor chip 200, the semiconductor chip 200 including opposite functional surfaces and a back surface, the functional surfaces having pads;
solder columns 104 protruding from the functional surface of the semiconductor chip 200 and electrically connected to the pads;
an ink pattern layer 103 coated on the sidewall surface of the solder column 104;
a plastic layer 105 covering the semiconductor chip 200 and the ink pattern layer 103;
and metal pins 106 electrically connected with the solder columns 104 are positioned on the ink pattern layer 103 and the surface, far away from the functional surface, of the solder columns 104.
In some embodiments, the thickness of the ink pattern layer 103 is less than the height of the solder columns 104.
In some embodiments, a surface of the solder column 104 remote from the functional surface is raised from a surface of the ink pattern layer 103 remote from the functional surface.
In some embodiments, the contact surface of the metal pins 106 with the ink pattern layer 103 and the solder columns 104 is stepped. The step shape includes at least one step.
In some embodiments, the material of the ink pattern layer 103 is a photosensitive polymer; the material of the solder column 104 is one or more of tin, tin silver, tin lead, tin silver copper, tin silver zinc, tin bismuth indium, tin gold, tin copper, tin zinc indium or tin silver antimony.
It should be noted that the terms "comprising" and "having," and variations thereof, as referred to in this disclosure are intended to cover non-exclusive inclusion. The terms "first," "second," and the like are used to distinguish similar objects and not necessarily to describe a particular order or sequence unless otherwise indicated by context, it should be understood that the data so used may be interchanged where appropriate. In addition, embodiments of the present disclosure and features of embodiments may be combined with each other without conflict. In addition, in the above description, descriptions of well-known components and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure. In the foregoing embodiments, each embodiment is mainly described for the differences from the other embodiments, and the same/similar parts between the embodiments need to be referred to (or referred to) each other.
Although the present invention has been described with respect to the preferred embodiments, it is not intended to limit the scope of the invention, and any person skilled in the art may make any possible variations and modifications to the technical solution of the present invention using the methods and technical matters disclosed above without departing from the spirit and scope of the present invention, so any simple modifications, equivalent variations and modifications to the above embodiments according to the technical matters of the present invention fall within the scope of the technical matters of the present invention.
Claims (17)
1. The method for forming the packaging structure is characterized by comprising the following steps:
providing a metal substrate comprising opposite front and back surfaces;
etching the front surface of the metal substrate to form a plurality of grooves in the metal substrate;
forming a plurality of discrete ink pattern layers on the front surface of the metal substrate outside the groove, wherein the ink pattern layers are provided with through holes exposing the bottoms of the corresponding grooves;
filling the grooves and the through holes with solder materials to form solder columns;
providing a semiconductor chip, wherein the semiconductor chip comprises a functional surface and a back surface which are opposite, and the functional surface is provided with a plurality of bonding pads;
flip-chip the semiconductor chip on the front surface of the metal substrate, and welding the bonding pads on the functional surface of the semiconductor chip and the tops of the corresponding solder columns together;
forming a plastic layer for plastic packaging the front surface of the metal substrate, the semiconductor chip and the ink pattern layer;
and removing part of the metal substrate along the back surface of the metal substrate to form a plurality of metal pins electrically connected with the bottoms of the corresponding solder columns.
2. The method of claim 1, wherein the sidewalls of the recess are stepped.
3. The method of claim 2, wherein the sidewall of the recess has at least one step, and the ink pattern layer spans the at least one step surface and a portion of the front surface of the metal substrate outside the recess.
4. The method of claim 2, wherein forming the recess uses a multi-step etching process.
5. The method of claim 1, wherein the ink pattern layer is made of a photosensitive polymer.
6. The method of forming a package structure according to claim 5, wherein the ink pattern forming process includes: forming a plurality of discrete photosensitive ink film layers on the front surface of the metal substrate, wherein each photosensitive ink film layer is filled with a corresponding groove and covers the front surface of the metal substrate of the part outside the groove; and sequentially carrying out an exposure process and a development process on the photosensitive ink film layer, removing part of the photosensitive ink film layer, forming a plurality of discrete ink pattern layers on the front surface of the metal substrate outside the groove, and forming through holes exposing the bottoms of the corresponding grooves in the ink pattern layers.
7. The method of claim 6, wherein the pre-bake treatment is performed before and/or after the development process.
8. The method of claim 1 or 5, wherein the solder column is made of one or more of tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-bismuth-indium, tin-gold, tin-copper, tin-zinc-indium, or tin-silver-antimony.
9. The method of claim 8, wherein the solder columns are formed with a spot welding process, wherein the top surfaces of the solder columns are higher than the top surfaces of the ink pattern layers.
10. The method of forming a package structure according to claim 1, wherein after flip-chip mounting the semiconductor chip on the front surface of the metal substrate, reflow processing is performed to solder the pads on the functional surface of the semiconductor chip with the corresponding tops of the solder columns.
11. The method of forming a package structure according to claim 10, wherein after bonding the pads of the functional surface of the semiconductor chip and the corresponding solder column tops together, further comprising: and curing the ink pattern layer.
12. The method of forming a package structure according to claim 1, wherein the metal substrate includes a plurality of package regions and scribe line regions between the package regions, the steps of forming the grooves, the ink pattern layer, the solder columns, the semiconductor chip, the molding layer, and the metal pins being performed simultaneously in each of the package regions, the molding layer further covering a front surface of the metal substrate in the scribe line regions; after the metal pins are formed, the plastic sealing layer is cut along the cutting channel area, so that a plurality of discrete packages are formed.
13. A package structure, comprising:
a semiconductor chip comprising opposite functional and back surfaces, the functional surface having pads;
solder columns protruding from the functional surface of the semiconductor chip and electrically connected with the bonding pads;
an ink pattern layer coated on the side wall surface of the solder column;
a plastic layer coating the semiconductor chip and the ink pattern layer;
and the metal pins are positioned on the ink pattern layer and the surface, far away from the functional surface, of the solder column and are electrically connected with the solder column.
14. The package structure of claim 13, wherein the thickness of the ink pattern layer is less than the height of the solder columns.
15. The package structure of claim 14, wherein a surface of the solder column remote from the functional surface is raised from a surface of the ink pattern layer remote from the functional surface.
16. The package structure of claim 15, wherein contact surfaces of the metal pins with the ink pattern layer and the solder columns are stepped.
17. The package structure of claim 13, wherein the material of the ink pattern layer is a photosensitive polymer; the material of the solder column is one or more of tin, tin silver, tin lead, tin silver copper, tin silver zinc, tin bismuth indium, tin gold, tin copper, tin zinc indium or tin silver antimony.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310688252.7A CN116564836A (en) | 2023-06-09 | 2023-06-09 | Package structure and method for forming the same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310688252.7A CN116564836A (en) | 2023-06-09 | 2023-06-09 | Package structure and method for forming the same |
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| CN116564836A true CN116564836A (en) | 2023-08-08 |
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| CN202310688252.7A Pending CN116564836A (en) | 2023-06-09 | 2023-06-09 | Package structure and method for forming the same |
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| CN (1) | CN116564836A (en) |
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