CN116561040A - Message processing device, system, method and equipment - Google Patents
Message processing device, system, method and equipment Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/12—Avoiding congestion; Recovering from congestion
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/24—Traffic characterised by specific attributes, e.g. priority or QoS
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/22—Parsing or analysis of headers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention provides a message processing device, a system, a method and equipment. A message processing apparatus includes: a plurality of preset virtual channels; the mapping module is used for establishing a mapping relation between a transmission type field of the message and a preset virtual channel and inputting the input message containing the transmission type field into the corresponding virtual channel according to the mapping relation; and the arbitration module is connected with each virtual channel, and is used for determining the priority of the virtual channel, confirming the order of the message output of each virtual channel according to the arbitration rule and sending the message of each virtual channel to the PCIE interface according to the order. The scheme disclosed by the invention reduces the peripheral level of the PCIE module, reduces the design difficulty of the peripheral module, adopts an arbitration mechanism, avoids the phenomenon of congestion in the scene of the rapid increase of the number of messages, causes the frame loss of message data, and improves the service quality of the messages.
Description
Technical Field
The present invention relates to the field of communications, and in particular, to a device, a system, a method, and an apparatus for processing a message.
Background
The BMC (Baseboard Management Controller ) generally processes various service messages through PCIE (Peripheral Component Interconnect Express, high-speed serial computer expansion bus standard) interfaces, and PCIE adopts a serial connection mode and uses a data packet TLP (Transaction Layer Packet ) form to perform data transmission.
In the related art of message processing, a message routing module and a type routing module are generally connected to a PCIE interface in an external mode to process PCIE output messages, and the processing mode increases a module hierarchy relationship, so that internal routing delay of a BMC is easily caused, and congestion is easily caused under a scene of rapid increase of the number of messages.
Disclosure of Invention
In view of this, the present invention provides a device, a system, a method and a device for processing a packet, which at least solve the problem that in the related art of packet processing, a PCIE interface is generally required to be externally connected with a message routing module and a type routing module to process a PCIE output packet, so that a hierarchical relationship of the modules is increased, and a delay of routing in a BMC and congestion easily occur in a scene of a surge in the number of packets are easily caused.
Based on the above object, an aspect of an embodiment of the present invention provides a message processing apparatus, including: a plurality of preset virtual channels; the mapping module is used for establishing a mapping relation between a transmission type field of the message and a preset virtual channel and inputting the input message containing the transmission type field into the corresponding virtual channel according to the mapping relation; and the arbitration module is connected with each virtual channel, and is used for determining the priority of the virtual channel, confirming the order of the message output of each virtual channel according to the arbitration rule and sending the message of each virtual channel to the PCIE interface according to the order.
In some embodiments, the mapping module is further to: and establishing a one-to-one mapping relation between the transmission type field of the message and the preset virtual channels by adapting the number of the transmission type fields to the number of the preset virtual channels.
In some embodiments, the arbitrated module is further to: the priority of the virtual channels from low to high is determined according to the sequence number of the virtual channels from small to large.
In some embodiments, the mapping module is further to: and responding to the received messages containing the transmission type fields, and respectively inputting the messages containing the transmission type fields into the corresponding virtual channels according to the mapping relation and in sequence from high to low according to the priority of the virtual channels.
In some embodiments, further comprising: the configuration module is respectively connected with the mapping module and the arbitration module, and is used for distributing transmission type fields corresponding to the messages of different types through PCIE driving software, inputting the messages containing the transmission type fields into the mapping module, and configuring the arbitration rules of the arbitration module according to user requirements.
In some embodiments, the arbitration rules include: and outputting the message of each virtual channel according to the order from high priority to low priority of the virtual channel.
In some embodiments, the arbitration rules include: and outputting the message of each virtual channel according to the message of the virtual channel with the highest priority and circularly outputting the messages of the virtual channels with the remaining priorities.
In another aspect of the embodiments of the present invention, a message processing system is provided, including a message processing device disposed at a sending end interface and/or a receiving end interface of a PCIE module, where the message processing device includes: a plurality of preset virtual channels; the mapping module is used for establishing a mapping relation between a transmission type field of the message and a preset virtual channel and inputting the input message containing the transmission type field into the corresponding virtual channel according to the mapping relation; and the arbitration module is connected with each virtual channel, and is used for determining the priority of the virtual channel, confirming the order of the message output of each virtual channel according to the arbitration rule and sending the message of each virtual channel to the PCIE interface according to the order.
In some embodiments, the mapping module is further to: and establishing a one-to-one mapping relation between the transmission type field of the message and the preset virtual channels by adapting the number of the transmission type fields to the number of the preset virtual channels.
In some embodiments, the arbitrated module is further to: the priority of the virtual channels from low to high is determined according to the sequence number of the virtual channels from small to large.
In some embodiments, the mapping module is further to: and responding to the received messages containing the transmission type fields, and respectively inputting the messages containing the transmission type fields into the corresponding virtual channels according to the mapping relation and in sequence from high to low according to the priority of the virtual channels.
In some embodiments, further comprising: the configuration module is respectively connected with the mapping module and the arbitration module, and is used for distributing transmission type fields corresponding to the messages of different types through PCIE driving software, inputting the messages containing the transmission type fields into the mapping module, and configuring the arbitration rules of the arbitration module according to user requirements.
In some embodiments, the arbitration rules include: and outputting the message of each virtual channel according to the order from high priority to low priority of the virtual channel.
In some embodiments, the arbitration rules include: and outputting the message of each virtual channel according to the message of the virtual channel with the highest priority and circularly outputting the messages of the virtual channels with the remaining priorities.
In another aspect of the embodiment of the present invention, a method for processing a message is provided, including: responding to the received input message by a mapping module, and inputting the input message into a corresponding virtual channel according to the transmission type field of the input message and the mapping relation between the transmission type field of the message and the virtual channel; determining the order of outputting the messages of each virtual channel according to the priority of the virtual channel and the arbitration rule by an arbitration module, and sending the messages of each virtual channel to a PCIE interface according to the order.
In another aspect of the embodiments of the present invention, there is also provided a computer device including at least one processor; and a memory storing computer instructions executable on the processor, the instructions when executed by the processor performing the steps of the method described above, wherein the method comprises: responding to the received input message by a mapping module, and inputting the input message into a corresponding virtual channel according to the transmission type field of the input message and the mapping relation between the transmission type field of the message and the virtual channel; determining the order of outputting the messages of each virtual channel according to the priority of the virtual channel and the arbitration rule by an arbitration module, and sending the messages of each virtual channel to a PCIE interface according to the order.
In another aspect of the embodiments of the present invention, there is also provided a computer-readable storage medium storing a computer program which when executed by a processor implements the steps of the method as described above, the method comprising: responding to the received input message by a mapping module, and inputting the input message into a corresponding virtual channel according to the transmission type field of the input message and the mapping relation between the transmission type field of the message and the virtual channel; determining the order of outputting the messages of each virtual channel according to the priority of the virtual channel and the arbitration rule by an arbitration module, and sending the messages of each virtual channel to a PCIE interface according to the order.
The invention has at least the following beneficial effects: the message processing device provided by the invention reduces the peripheral hierarchy of the PCIE module, analyzes the message through the transmission type field, reduces the design difficulty of the peripheral module, adopts an arbitration mechanism, sequentially outputs the messages of different transmission types according to the arbitration rule, avoids the phenomenon of congestion in the scene of the rapid increase of the number of the messages, causes the frame loss of the message data, and improves the service quality of the message.
Drawings
In order to more clearly illustrate the embodiments of the invention or the solutions of the prior art, the drawings which are necessary for the description of the embodiments or the prior art will be briefly described, it being evident that the drawings in the following description are only some embodiments of the invention and that other embodiments can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a message processing apparatus according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another structure of a message processing apparatus according to an embodiment of the present invention;
FIG. 3 is a flowchart of a message processing method according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a computer device according to an embodiment of the present invention;
fig. 5 shows a schematic structural diagram of a computer-readable storage medium according to an embodiment of the present invention.
Detailed Description
Embodiments of the present disclosure are described below. However, it is to be understood that the disclosed embodiments are merely examples and that other embodiments may take various alternative forms. The figures are not necessarily to scale; some functions may be exaggerated or minimized to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present invention. As will be appreciated by one of ordinary skill in the art, the various features illustrated and described with reference to any one of the figures may be combined with features illustrated in one or more other figures to produce embodiments that are not explicitly illustrated or described. The combination of features shown provides representative embodiments for typical applications. However, various combinations and modifications of the features consistent with the teachings of the present disclosure may be desired for certain specific applications or implementations.
Furthermore, it should be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
One or more embodiments of the present application will be described below with reference to the accompanying drawings.
In the prior art, in a PCIE packet processing manner adopted by the BMC chip, an ID routing module and a TYPE routing module need to be added outside the PCIE to perform additional analysis processing on the PCIE output packet. The ID routing module distinguishes the messages by analyzing ID related bus number data obtained by analyzing related fields, and the TYPE routing module distinguishes the messages by analyzing the message TYPEs of the messages. The processing mode greatly increases the module level outside the PCIE, the existence of the ID routing module and the TYPE routing module greatly increases the wiring delay inside the BMC chip, and when a plurality of groups of messages are simultaneously input to the PCIE module, congestion is easy to cause in a high-capacity message burst scene due to the design of lack of message priority. Therefore, a message processing apparatus is needed to reduce the external hierarchy of PCIE modules and reduce the internal routing delay of BMCs, so as to avoid congestion caused by the surge of the number of messages.
Based on the above objects, a first aspect of the embodiments of the present invention provides an embodiment of a message processing apparatus. Fig. 1 is a schematic structural diagram of a message processing apparatus provided in an embodiment of the present application, where, as shown in fig. 1, a message processing apparatus is connected to a PCIE interface, and includes: a plurality of preset virtual channels; the mapping module is used for establishing a mapping relation between a transmission type field of the message and a preset virtual channel and inputting the input message containing the transmission type field into the corresponding virtual channel according to the mapping relation; and the arbitration module is connected with each virtual channel, and is used for determining the priority of the virtual channel, confirming the order of the message output of each virtual channel according to the arbitration rule and sending the message of each virtual channel to the PCIE interface according to the order.
According to several embodiments of the present invention, the mapping module is further to: and establishing a one-to-one mapping relation between the transmission type field of the message and the preset virtual channels by adapting the number of the transmission type fields to the number of the preset virtual channels.
According to several embodiments of the invention, the arbitrated module is further to: the priority of the virtual channels from low to high is determined according to the sequence number of the virtual channels from small to large.
According to several embodiments of the present invention, the mapping module is further to: and in response to receiving a plurality of messages containing the transmission type fields, sequentially inputting the plurality of messages containing the transmission type fields into corresponding virtual channels according to the mapping relation and the order of the priorities of the virtual channels from high to low.
According to several embodiments of the present invention, further comprising: the configuration module is respectively connected with the mapping module and the arbitration module, and is used for distributing transmission type fields corresponding to the messages of different types through PCIE driving software, inputting the messages containing the transmission type fields into the mapping module, and configuring the arbitration rules of the arbitration module according to the user requirements.
According to several embodiments of the invention, the arbitration rules include: and outputting the message of each virtual channel according to the order from high to low of the priority of the virtual channel.
According to several embodiments of the invention, the arbitration rules include: and outputting the message of each virtual channel according to the message of the virtual channel with the highest priority, and circularly outputting the messages of the virtual channels with the remaining priorities.
According to the embodiments provided by the invention, the message processing device provided by the invention can analyze the message only by identifying the transmission type field of the message, and meanwhile, the message is processed with the confirmation of the virtual channel priority and the arbitration rule of the virtual channel message data output, so that a plurality of input messages can be sequentially input into the corresponding virtual channel according to the priority and simultaneously sequentially output according to the arbitration rule, the hierarchical module outside the PCIE module is reduced, wiring inside the chip is reduced, and the priority and the arbitration module are arranged to ensure the orderly output of the message, thereby avoiding congestion under the condition of the rapid increase of the message data quantity.
The following is another embodiment of a message processing apparatus provided in the present invention.
The invention provides a message processing device which processes messages by using a transmission TYPE (TC) field of a TLP supported by a PCIE protocol, namely a TC field and an arbitration mechanism supported by the PCIE protocol.
Taking a sending end of a PCIE module as an example, a message processing apparatus is disposed at an interface periphery of the sending end of the PCIE module, fig. 2 is a schematic structural diagram of another message processing apparatus provided by an embodiment of the present invention, and as shown in fig. 2, the message processing apparatus includes: a plurality of virtual channels, virtual channel 1, virtual channel 2, virtual channel 3, etc.; the mapping module is used for receiving data messages, message 1, message 2, message 3 and the like, establishing a mapping relation between TC fields of the messages and preset virtual channels, and inputting the input messages containing the TC fields into the corresponding virtual channels according to the established mapping relation; and the arbitration module is connected with each virtual channel, and is used for determining the priority of the virtual channel, confirming the order of the message output of each virtual channel according to the arbitration rule and sending the message of each virtual channel to the sending end of the PCIE module according to the order.
The message processing device further comprises a configuration module which is respectively connected with the arbitration module and the mapping module, and the PCIE driving software of the configuration module is used for distributing corresponding transmission type fields to messages with different transmission types, such as VGA image message configuration TC field 7, control message configuration TC field from a host to BMC direction 6 and the like, the TC field is 3 bits, the configuration of the transmission types from 7 to 0 is respectively corresponding, and the configuration module is used for distributing corresponding transmission type fields to the messages so as to input the messages containing the transmission type fields into the mapping module.
When the chip is electrified, the configuration module configures the mapping module and the arbitration module according to the requirements of the user on the message. Preferably, the mapping module establishes a one-to-one mapping relationship between a preset virtual channel and different transmission type fields, and sets a bit corresponding to a TC field through a TC/VC mapping register (transmission type field/virtual channel mapping register), for example, bit 0 corresponds to TC0, bit 1 corresponds to TC1, … … bits 7 corresponds to TC7, meanwhile, bit 0 corresponds to VC0, bit 1 corresponds to VC1, … … bits 7 corresponds to VC7, thereby establishing a one-to-one mapping relationship between TC0-TC7 and VC0-VC 7.
Meanwhile, the configuration module can also configure the arbitration rule of the arbitration module, different messages are input into the corresponding virtual channels VC according to the corresponding TC fields, then the sequence of outputting the messages of each virtual channel is confirmed according to the arbitration rule of the arbitration module, and the messages of each virtual channel are sent to the sending end of the PCIE module according to the sequence. Wherein the arbitration rules of the arbitration module optionally include: outputting the message of each virtual channel according to the order from high to low of the priority of the virtual channel, namely outputting according to the order of VC7, VC6 and VC5 … … VC 0; the message of each virtual channel is output firstly according to the message of the virtual channel with the highest priority, and the messages of the virtual channels with the remaining priorities are output circularly, so that the messages of the virtual channels with the high priority can pass through directly and quickly; the messages of all virtual channels are output in a cyclic mode, a weighting mode or an average mode, wherein the average mode refers to that messages of different VCs are sequentially output through ports, and the weighting mode refers to that the ports pass through messages of different VCs according to different proportions.
According to the message processing device provided by the invention, the peripheral hierarchy of the PCIE module is lightened, the message is analyzed through the transmission type field, the design difficulty of the peripheral module is reduced, meanwhile, an arbitration mechanism is adopted, the messages with different transmission types are sequentially output according to the arbitration rule, the phenomenon of congestion in the scene of increasing the number of the messages is avoided, the frame loss of the message data is caused, and the service quality of the message is improved.
In a second aspect of the embodiments of the present invention, a packet processing system is provided, which includes a packet processing device disposed at a sending end interface and/or a receiving end interface of a PCIE module. Wherein the message processing device comprises: a plurality of preset virtual channels; the mapping module is used for establishing a mapping relation between a transmission type field of the message and a preset virtual channel and inputting the input message containing the transmission type field into the corresponding virtual channel according to the mapping relation; and the arbitration module is connected with each virtual channel, and is used for determining the priority of the virtual channel, confirming the order of the message output of each virtual channel according to the arbitration rule and sending the message of each virtual channel to the PCIE interface according to the order.
According to several embodiments of the present invention, the mapping module is further to: and establishing a one-to-one mapping relation between the transmission type field of the message and the preset virtual channels by adapting the number of the transmission type fields to the number of the preset virtual channels.
According to several embodiments of the invention, the arbitrated module is further to: the priority of the virtual channels from low to high is determined according to the sequence number of the virtual channels from small to large.
According to several embodiments of the present invention, the mapping module is further to: and in response to receiving a plurality of messages containing the transmission type fields, sequentially inputting the plurality of messages containing the transmission type fields into corresponding virtual channels according to the mapping relation and the order of the priorities of the virtual channels from high to low.
According to several embodiments of the present invention, further comprising: the configuration module is respectively connected with the mapping module and the arbitration module, and is used for distributing transmission type fields corresponding to the messages of different types through PCIE driving software, inputting the messages containing the transmission type fields into the mapping module, and configuring the arbitration rules of the arbitration module according to the user requirements.
According to several embodiments of the invention, the arbitration rules include: and outputting the message of each virtual channel according to the order from high to low of the priority of the virtual channel.
According to several embodiments of the invention, the arbitration rules include: and outputting the message of each virtual channel according to the message of the virtual channel with the highest priority, and circularly outputting the messages of the virtual channels with the remaining priorities.
In a third aspect of the embodiment of the present invention, a message processing method is provided, and fig. 3 shows a flowchart of a message processing method provided by the embodiment of the present invention. As shown in fig. 3, a message processing method includes:
s1: responding to the received input message by a mapping module, and inputting the input message into a corresponding virtual channel according to the transmission type field of the input message and the mapping relation between the transmission type field of the message and the virtual channel;
s2: determining the order of outputting the messages of each virtual channel according to the priority of the virtual channel and the arbitration rule by an arbitration module, and sending the messages of each virtual channel to a PCIE interface according to the order.
In a fourth aspect of the embodiment of the present invention, a computer device is provided, and fig. 4 shows a schematic structural diagram of a computer device provided in the embodiment of the present invention. As shown in fig. 4, a computer device provided in an embodiment of the present invention includes the following modules: at least one processor 021; and a memory 022, the memory 022 storing computer instructions 023 executable on the processor 021, the computer instructions 023 when executed by the processor 021 implementing the steps of the method as described above, the method comprising: responding to the received input message by a mapping module, and inputting the input message into a corresponding virtual channel according to the transmission type field of the input message and the mapping relation between the transmission type field of the message and the virtual channel; determining the order of outputting the messages of each virtual channel according to the priority of the virtual channel and the arbitration rule by an arbitration module, and sending the messages of each virtual channel to a PCIE interface according to the order.
The invention also provides a computer readable storage medium. Fig. 5 is a schematic structural diagram of a computer-readable storage medium according to an embodiment of the present invention. As shown in fig. 5, the computer-readable storage medium 031 stores a computer program 032 which, when executed by a processor, performs the steps of the method as described above, wherein the method comprises: responding to the received input message by a mapping module, and inputting the input message into a corresponding virtual channel according to the transmission type field of the input message and the mapping relation between the transmission type field of the message and the virtual channel; determining the order of outputting the messages of each virtual channel according to the priority of the virtual channel and the arbitration rule by an arbitration module, and sending the messages of each virtual channel to a PCIE interface according to the order.
Finally, it should be noted that, as will be understood by those skilled in the art, implementing all or part of the above-described methods in the embodiments may be implemented by a computer program to instruct related hardware, and the program of the method for setting system parameters may be stored in a computer readable storage medium, where the program may include the flow of the embodiments of the methods described above when executed. The storage medium of the program may be a magnetic disk, an optical disk, a read-only memory (ROM), a random-access memory (RAM), or the like. The computer program embodiments described above may achieve the same or similar effects as any of the method embodiments described above.
Furthermore, the method disclosed according to the embodiment of the present invention may also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. The above-described functions defined in the methods disclosed in the embodiments of the present invention are performed when the computer program is executed by a processor.
Furthermore, the above-described method steps and system units may also be implemented using a controller and a computer-readable storage medium storing a computer program for causing the controller to implement the above-described steps or unit functions.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general purpose or special purpose computer or general purpose or special purpose processor. Further, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DOL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that as used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The foregoing embodiment of the present invention has been disclosed with reference to the number of embodiments for the purpose of description only, and does not represent the advantages or disadvantages of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program for instructing relevant hardware, and the program may be stored in a computer readable storage medium, where the storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will appreciate that: the above discussion of any embodiment is merely exemplary and is not intended to imply that the scope of the disclosure of embodiments of the invention, including the claims, is limited to such examples; combinations of features of the above embodiments or in different embodiments are also possible within the idea of an embodiment of the invention, and many other variations of the different aspects of the embodiments of the invention as described above exist, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. of the embodiments should be included in the protection scope of the embodiments of the present invention.
Claims (10)
1. A message processing apparatus, connected to a PCIE interface, comprising:
a plurality of preset virtual channels;
the mapping module is used for establishing a mapping relation between the transmission type field of the message and the preset virtual channel and inputting the input message containing the transmission type field into the corresponding virtual channel according to the mapping relation; and
and the arbitration module is connected with each virtual channel, and is used for determining the priority of the virtual channel, confirming the order of the message output of each virtual channel according to the arbitration rule and sending the message of each virtual channel to the PCIE interface according to the order.
2. The apparatus of claim 1, wherein the mapping module is further to:
and establishing a one-to-one mapping relation between the transmission type field of the message and the preset virtual channels by adapting the number of the transmission type fields to the number of the preset virtual channels.
3. The apparatus of claim 1, wherein the arbitration module is further to:
the priority of the virtual channels from low to high is determined according to the sequence number of the virtual channels from small to large.
4. The apparatus of claim 3, wherein the mapping module is further to:
and responding to the received messages containing the transmission type fields, and respectively inputting the messages containing the transmission type fields into the corresponding virtual channels according to the mapping relation and in sequence from high to low according to the priority of the virtual channels.
5. The apparatus as recited in claim 1, further comprising:
the configuration module is respectively connected with the mapping module and the arbitration module, and is used for distributing transmission type fields corresponding to the messages of different types through PCIE driving software, inputting the messages containing the transmission type fields into the mapping module, and configuring the arbitration rules of the arbitration module according to user requirements.
6. The apparatus of claim 5, wherein the arbitration rule comprises: and outputting the message of each virtual channel according to the order from high priority to low priority of the virtual channel.
7. The apparatus of claim 5, wherein the arbitration rule comprises: and outputting the message of each virtual channel according to the message of the virtual channel with the highest priority and circularly outputting the messages of the virtual channels with the remaining priorities.
8. A message processing system, comprising a message processing apparatus according to any of claims 1-7 arranged at a sender interface and/or a receiver interface of a PCIE module.
9. A method for processing a message, comprising:
responding to the received input message by a mapping module, and inputting the input message into a corresponding virtual channel according to the transmission type field of the input message and the mapping relation between the transmission type field of the message and the virtual channel;
determining the order of outputting the messages of each virtual channel according to the priority of the virtual channel and the arbitration rule by an arbitration module, and sending the messages of each virtual channel to a PCIE interface according to the order.
10. A computer device, comprising:
at least one processor; and
a memory storing computer instructions executable on the processor, which when executed by the processor, perform the steps of the method of claim 9.
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| CN117370239A (en) * | 2023-09-12 | 2024-01-09 | 象帝先计算技术(重庆)有限公司 | DMA task data transmission method, DMA controller and electronic equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117370239A (en) * | 2023-09-12 | 2024-01-09 | 象帝先计算技术(重庆)有限公司 | DMA task data transmission method, DMA controller and electronic equipment |
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