CN116545960A

CN116545960A - Two-dimensional network-on-chip structure, routing method, device, equipment and storage medium thereof

Info

Publication number: CN116545960A
Application number: CN202310409124.4A
Authority: CN
Inventors: 王源; 王梓霖; 钟毅; 崔小欣
Original assignee: Peking University
Current assignee: Peking University
Priority date: 2023-04-17
Filing date: 2023-04-17
Publication date: 2023-08-04

Abstract

The invention provides a two-dimensional network-on-chip structure, a routing method, a device, equipment and a storage medium thereof, relating to the technical field of communication. Wherein the two-dimensional network-on-chip structure comprises: a plurality of processing cores, any one of the processing cores comprising a routing node comprising five input distributors and five output arbiters; any input distributor is used for sending a transmission request of a target data packet to a target output arbiter, wherein the target output arbiter is determined based on a target routing direction, and the target routing direction is determined based on destination address information of the target data packet and an X-Y dimensional sequence routing strategy; the target output arbiter is used for responding to the transmission request so as to transmit the target data packet to a target position corresponding to the target output arbiter, wherein the target position comprises one routing node or a pulse data packet encoding and decoding interface in four adjacent routing nodes. The invention can better avoid the deadlock problem and improve the throughput rate of the two-dimensional network-on-chip structure.

Description

Two-dimensional network-on-chip structure, routing method, device, equipment and storage medium thereof

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a two-dimensional network on chip structure, and a routing method, apparatus, device, and storage medium thereof.

Background

With the approaching end of moore's law, in order to solve the communication problem between more and more processing cores on a single Chip, the design thought of NoC (Network on Chip) architecture is rapidly developed.

Currently, most communication modes among a plurality of processing cores in a NoC architecture adopt a routing technology. However, current routing algorithms do not avoid deadlocks well, resulting in reduced throughput of NoC architecture.

Disclosure of Invention

The invention provides a routing method, a routing device, electronic equipment and a storage medium of a two-dimensional network-on-chip structure, which are used for solving the defect of throughput rate reduction in the prior art.

The invention provides a two-dimensional network-on-chip structure, comprising:

a plurality of processing cores, any processing core comprising a routing node, the routing node comprising five input distributors and five output arbiters;

the routing nodes are connected with four adjacent routing nodes corresponding to the routing nodes to form four routing directions of the routing nodes, and the four adjacent routing nodes comprise routing nodes of four adjacent processing cores corresponding to any one processing core;

the routing node is connected with the pulse data packet coding and decoding interface of any processing core to form a routing direction of the routing node;

The five input distributors are used for receiving data packets sent by the four adjacent routing nodes and the pulse data packet coding and decoding interfaces, and the five output arbiters are used for sending the data packets to the four adjacent routing nodes and the pulse data packet coding and decoding interfaces;

any of the input distributors is used for sending a transmission request of a target data packet to a target output arbiter, wherein the target output arbiter is determined based on a target routing direction, and the target routing direction is determined based on destination address information of the target data packet and an X-Y dimensional sequence routing strategy;

the target output arbiter is configured to respond to the transmission request, so as to transmit the target data packet to a destination location corresponding to the target output arbiter, where the destination location includes one of the four adjacent routing nodes or the pulse data packet codec interface.

The invention also provides a routing method of the two-dimensional network-on-chip structure, wherein the two-dimensional network-on-chip structure is the two-dimensional network-on-chip structure, the method is applied to the first routing node, and the method comprises the following steps:

receiving a first target data packet sent by a second routing node, and determining the position relation between the second routing node and the first routing node in a two-dimensional network-on-chip, wherein the second routing node is an adjacent routing node of the first routing node;

Determining a first target input distributor from five input distributors of the first routing node based on the position relation, and sending the first target data packet to the first target input distributor;

determining a first target routing direction based on destination address information of the first target data packet and an X-Y dimensional sequence routing strategy;

determining a first target output arbiter from the five output arbiters based on the first target routing direction;

sending, by the first target input dispatcher, a first transmission request of the first target data packet to the first target output arbiter;

and responding to the first transmission request through the first target output arbiter so as to transmit the first target data packet to a first destination position corresponding to the first target output arbiter, wherein the first destination position comprises a third routing node adjacent to the first routing node or a pulse data packet encoding and decoding interface of the first routing node.

According to the routing method of the two-dimensional network-on-chip structure provided by the invention, the response to the first transmission request comprises the following steps:

determining response time of the first transmission request based on a preset transmission request priority rule;

Responding to the first transmission request based on the response time;

wherein the transmission request priority rule includes at least one of:

the priority of a transmission request sent by a first input distributor is highest, and the first input distributor is an input distributor corresponding to a pulse data packet encoding and decoding interface;

the priority of a transmission request sent by a second input distributor is higher than that of a transmission request sent by a third input distributor, the second input distributor is an input distributor corresponding to a first position relation, the third input distributor is an input distributor corresponding to a second position relation, the first position relation is the same in Y coordinate position on a two-dimensional network on chip, and the second position relation is the same in X coordinate position on the two-dimensional network on chip;

and under the condition that the first target output arbiter receives a third transmission request, the third transmission request is not answered, and the third transmission request meets the preset condition, the priority order of the first transmission request and the third transmission request is alternated in each answering process, and the preset condition comprises that the position relation corresponding to the third transmission request and the position relation corresponding to the first transmission request are both the first position relation.

The routing method of the two-dimensional network-on-chip structure provided by the invention further comprises the following steps:

copying the first target data packet under the condition that the first target data packet is determined to be copied based on multicast identification information of the first target data packet, so as to obtain a copied data packet, wherein the multicast identification information is used for determining whether the data packet is required to be copied or not;

determining a third destination location based on destination address information of the first destination data packet, the third destination location being different from the first destination location;

and sending the copied data packet to the third destination position.

According to the routing method of the two-dimensional network-on-chip structure provided by the invention, the multicast identification information comprises identification bit values of a plurality of routing rounds, and the bit number of the multicast identification information is determined based on the number of the plurality of processing cores;

the first target data packet is determined whether replication is required based on the following steps:

carrying out bit-by-bit analysis on the multicast identification information of the first target data packet to obtain an identification bit value of the current routing round;

and determining whether the first target data packet needs to be copied or not based on the identification bit value of the current routing round.

According to the routing method of the two-dimensional network-on-chip structure provided by the invention, the destination address information of the first target data packet comprises address bit values of a plurality of routing rounds, and the bit number of the destination address information of the first target data packet is determined based on the number of the plurality of processing cores;

the determining a third destination location based on destination address information of the first destination data packet includes:

carrying out bit-by-bit analysis on the destination address information of the first target data packet to obtain an address bit value of the current routing round;

and determining a third destination position based on a comparison result of the address bit value of the current routing round and the source address information of the first routing node.

receiving a second target data packet sent by a pulse data packet encoding and decoding interface of the first routing node;

determining a second target input distributor corresponding to a pulse data packet encoding and decoding interface of the first routing node from five input distributors of the first routing node, and sending the second target data packet to the second target input distributor;

Determining a second target routing direction based on destination address information of the second target data packet;

determining a second target output arbiter from the five output arbiters of the first routing node based on the second target routing direction;

transmitting, by the second target input dispatcher, a second transmission request of the second target data packet to the second target output arbiter;

and responding to the second transmission request through the second target output arbiter so as to transmit the second target data packet to a second destination position corresponding to the second target output arbiter, wherein the second destination position comprises a fourth routing node adjacent to the first routing node or a pulse data packet encoding and decoding interface of the first routing node.

The invention also provides a routing device of a two-dimensional network-on-chip structure, wherein the two-dimensional network-on-chip structure is the two-dimensional network-on-chip structure, the device is deployed at a first routing node, and the device comprises:

the data packet receiving module is used for receiving a first target data packet sent by a second routing node and determining the position relation between the second routing node and the first routing node in a two-dimensional network-on-chip, wherein the second routing node is an adjacent routing node of the first routing node;

The distributor determining module is used for determining a first target input distributor from the five input distributors of the first routing node based on the position relation and sending the first target data packet to the first target input distributor;

the direction determining module is used for determining a first target routing direction based on the destination address information of the first target data packet and an X-Y dimension sequence routing strategy;

the arbiter determining module is used for determining a first target output arbiter from the five output arbiters based on the first target routing direction;

a request sending module, configured to send, through the first target input dispatcher, a first transmission request of the first target data packet to the first target output arbiter;

and the request response module is used for responding to the first transmission request through the first target output arbiter so as to transmit the first target data packet to a first destination position corresponding to the first target output arbiter, wherein the first destination position comprises a third routing node adjacent to the first routing node or a pulse data packet encoding and decoding interface of the first routing node.

The invention also provides an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the routing method of the two-dimensional network-on-chip structure according to any one of the above when executing the program.

The present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a routing method of a two-dimensional network-on-chip structure as described in any of the above.

The invention provides a two-dimensional network-on-chip structure and a routing method, a device, equipment and a storage medium thereof, wherein the two-dimensional network-on-chip structure comprises a plurality of processing cores, a routing node in any processing core comprises five input distributors and five output arbiters, the five input distributors are used for receiving data packets sent by pulse data packet coding and decoding interfaces of four adjacent routing nodes and the processing cores, so that the data packets in five directions can be received, and the target output arbiters are used for responding to a transmission request so as to transmit the target data packets to target positions corresponding to the target output arbiters, and the target positions comprise one routing node or pulse data packet coding and decoding interface in the four adjacent routing nodes, so that the data packets can be sent to the five directions based on the five output arbiters, thereby realizing parallel processing of the five data packets and finally improving the throughput rate of the two-dimensional network-on-chip structure; any input distributor is used for sending a transmission request of a target data packet to a target output arbiter, the target output arbiter is determined based on a target routing direction, and the target routing direction is determined based on destination address information of the target data packet and an X-Y dimension sequence routing strategy, so that the target output arbiter can be determined from five output arbiters based on the X-Y dimension sequence routing strategy, further, the deadlock problem is better avoided, and finally, the throughput rate of the two-dimensional network-on-chip structure is improved.

Drawings

In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a two-dimensional network-on-chip structure according to the present invention;

FIG. 2 is a schematic routing diagram of a two-dimensional network-on-chip structure according to the present invention;

FIG. 3 is a second schematic routing diagram of the two-dimensional network-on-chip structure according to the present invention;

fig. 4 is a schematic routing multicast diagram of a two-dimensional network-on-chip structure according to the present invention;

FIG. 5 is a schematic flow chart of a routing method of a two-dimensional network-on-chip structure according to the present invention;

FIG. 6 is a second flow chart of a routing method of a two-dimensional network-on-chip structure according to the present invention;

fig. 7 is a schematic structural diagram of a routing device with a two-dimensional network-on-chip structure according to the present invention;

fig. 8 is a schematic structural diagram of an electronic device provided by the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In describing embodiments of the present invention, it should be noted that the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "east", "south", "west", "north", "local", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the embodiments of the present invention and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the embodiments of the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In describing embodiments of the present invention, it should be noted that, unless explicitly stated and limited otherwise, the terms "coupled," "coupled," and "connected" should be construed broadly, and may be either a fixed connection, a removable connection, or an integral connection, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium. The specific meaning of the above terms in embodiments of the present invention will be understood in detail by those of ordinary skill in the art.

In embodiments of the invention, unless expressly specified and limited otherwise, a first feature "up" or "down" on a second feature may be that the first and second features are in direct contact, or that the first and second features are in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction. Furthermore, the term "plurality" is meant to include two or more.

In the last decades, the processing power and integration of the chip has doubled within 18 to 24 months, following the path of operating frequency multiplication and transistor scaling proposed by moore's law. In recent years, as moore's law approaches its end, the traditional path that relies on frequency scaling to increase the chip's operation speed is not sustainable. Therefore, increasing the number of processing cores in parallel on a single chip becomes a reasonable choice.

Based on the above, in order to solve the problem of communication between more and more processing cores on a single Chip, similar to the organization structure of the brain, the design thought of NoC (Network on Chip) architecture commonly used for neural Network computation is rapidly developed. Common NoC topologies are 2D-Mesh, tree, ring, star, octagon, spiderson, torus, butterfly, and the like. Among them, the 2D-Mesh structure is most commonly used in neural network computation.

How to realize higher communication efficiency based on NoC architecture is an important issue at present. Currently, most communication modes among a plurality of processing cores in a NoC architecture adopt a routing technology. However, current routing algorithms do not avoid deadlocks well, resulting in lower throughput rates for NoC architectures. For example, the Tree structure has lower expandability and universality than the 2D-Mesh routing, and the on-chip communication bandwidth is lower, especially when the number of processing cores of the network-on-chip structure is lower than 64, the average routing distance of the Tree structure is farther; and the 2D-Mesh structure does not realize a network-on-chip routing algorithm capable of avoiding deadlock, and severely restricts the throughput rate of the system.

In view of the above problems, the present invention proposes the following embodiments. Fig. 1 is a schematic structural diagram of a two-dimensional network-on-chip structure provided in the present invention, and referring to fig. 1, the two-dimensional network-on-chip structure includes a plurality of processing cores 1, any processing core includes a routing node 11, and the routing node includes five input distributors 111 and five output arbiters 112.

Here, the input distributor 111 is used to send the data packet to be transmitted to the corresponding output arbiter 112. More specifically, the input dispatcher 111 is configured to receive a packet sent by a routing node of the four adjacent routing nodes of the routing node 11, or to receive a packet sent by the pulse packet codec interface 12, and to send a transmission request of the packet to the corresponding output arbiter 112.

Here, the output arbiter 112 is used to determine the transmission position of the data packet to be transmitted. More specifically, the output arbiter 112 is configured to send a data packet to be transmitted to one of the four adjacent routing nodes of the routing node 11, or to send the data packet to be transmitted to the pulse data packet codec interface 12, and to respond to a transmission request, so as to receive the data packet sent by the input distributor 111, and transmit the data packet to a location corresponding to the output arbiter 112.

In one embodiment, the processing core 1 receives a packet sent by another processing core, the packet is received by the input dispatcher 111 in the routing node 11, and then sent by the input dispatcher 111 to the output arbiter 112, and the output arbiter 112 transmits the packet to the processing core 1 through the pulse packet codec interface 12.

In another embodiment, processing core 1 sends a packet to another processing core, the packet is sent to input dispatcher 111 by pulse packet codec interface 12, then to output arbiter 112 by input dispatcher 111, and output arbiter 112 transmits the packet to another processing core through an adjacent routing node. The process of receiving the data packet by another processing core is similar to the above embodiment, and will not be described here again.

The routing node 11 is connected with four adjacent routing nodes corresponding to the routing node 11 to form four routing directions of the routing node 11, wherein the four adjacent routing nodes comprise routing nodes of four adjacent processing cores corresponding to any one processing core 1;

the routing node 11 is connected to the pulse packet codec interface 12 of any processing core 1 to form a routing direction of the routing node.

Here, the pulse packet codec interface 12 is an interface through which the processing core 1 communicates with the routing node 11.

Here, the routing direction is the transmission direction of the data packet on the routing node 11. Since the routing node 11 is connected to the adjacent routing nodes in four directions and is simultaneously connected to the pulse packet codec interface 12 of any processing core 1, i.e. is simultaneously connected to the pulse packet codec interface 12 of the local core, the routing node 11 has five routing directions.

For ease of understanding, it is assumed that four routing directions formed by connecting the routing node 11 with four adjacent routing nodes corresponding to the routing node 11 are an east direction, a west direction, a south direction, and a north direction, respectively, and that a routing direction formed by connecting the routing node 11 with the pulse packet codec interface 12 of any processing core 1 is a local direction, and based on this, the routing directions of the routing node 11 are the east direction, the west direction, the south direction, the north direction, and the local direction. Correspondingly, the routing node 11 may be connected to an adjacent routing node in the east direction, the routing node 11 may be connected to an adjacent routing node in the west direction, the routing node 11 may be connected to an adjacent routing node in the south direction, the routing node 11 may be connected to an adjacent routing node in the north direction, and the routing node 11 may be connected to the local direction pulse packet codec interface 12.

Illustratively, the routing direction may be described in terms of the relative positional relationship of the routing node 11 to four adjacent routing nodes. Referring to fig. 2, taking a two-dimensional network-on-chip structure formed by 16 cores as an example, the node in fig. 2 is a routing node, and the 4-bit destination address information of the data packet includes an X address of 2 bits and a Y address of 2 bits, for example, the X address is the core address 00 and 01 in fig. 2, and the Y address is the core address 00 and 01 in fig. 2. The two-dimensional network-on-chip structure can be described in an X-Y coordinate system, wherein on the X-Y coordinate system, four routing directions are respectively the east direction E with the increasing direction of an X address, the west direction W with the decreasing direction of the X address, the south direction S with the increasing direction of the Y address, and the north direction N with the decreasing direction of the Y address.

It should be noted that, in the embodiment of the present invention, the processing core 1 where the routing node 11 is located in a central area of the two-dimensional network-on-chip structure, that is, the routing node 11 has four adjacent routing nodes. In addition, if the processing core where the routing node is located in the edge area of the two-dimensional network-on-chip structure, namely, the routing node has 3 adjacent routing nodes; if the processing core where the routing node is located in a corner area of the two-dimensional network-on-chip structure, the routing node has 2 adjacent routing nodes.

The five input distributors are used for receiving the data packets sent by the four adjacent routing nodes and the pulse data packet coding and decoding interfaces, and the five output arbiters are used for sending the data packets to the four adjacent routing nodes and the pulse data packet coding and decoding interfaces.

there is one input distributor 111 and one output arbiter 112 in each of the five routing directions of the routing node 11, i.e. one input channel and one output channel for each routing direction, on which one input distributor 111 may be disposed and one output arbiter 112 may be disposed.

For ease of understanding, it is assumed that four routing directions formed by connecting the routing node 11 with four adjacent routing nodes corresponding to the routing node 11 are an east direction, a west direction, a south direction, and a north direction, respectively, and that a routing direction formed by connecting the routing node 11 with the pulse packet codec interface 12 of any processing core 1 is a local direction. Referring to fig. 3, a data packet transmitted from a neighboring routing node in a west direction is input to an input dispatcher, and the input dispatcher may transmit the data packet to an output arbiter corresponding to a routing direction of east direction, south direction, north direction, and local direction; data packets sent by adjacent routing nodes in the east direction are input into an input distributor, and the input distributor can transmit the data packets to an output arbiter corresponding to the routing directions of the west direction, the south direction, the north direction and the local direction; inputting a data packet sent by an adjacent routing node in the north direction into an input distributor, wherein the input distributor can transmit the data packet to an output arbiter corresponding to the local direction with the routing direction being the south direction; data packets sent by adjacent routing nodes in the south direction are input into an input distributor, and the input distributor can transmit the data packets to an output arbiter corresponding to the local direction and the north direction of the routing direction; data packets sent by adjacent routing nodes in the local direction are input to an input distributor, and the input distributor can transmit the data packets to an output arbiter corresponding to the routing directions including the east direction, the west direction, the south direction, the north direction and the local direction.

Here, the target packet is a packet to be transmitted by the input distributor. The destination address information of the target data packet is the address information of the final transmission position of the target data packet, namely the address information of the processing core of the final transmission of the target data packet. The destination address information is used to determine the routing direction of the destination packet. Referring to fig. 4, taking a two-dimensional network-on-chip structure composed of 16 cores as an example, the destination address information may be 4bit information, for example, a in fig. 4 is 1000, 1100, the destination address information may be 0000, 0100, 0001, 0010, etc., and further, the destination address information includes an X address and a Y address.

Specifically, after the target output arbiter responds to the transmission request, the target data packet corresponding to the transmission request is sent to the target output arbiter.

Considering that the condition that the deadlock occurs is that the routing node has a limited buffer space, when the buffer space of the node A is full, the data packet sending request sent by the node B to the node A cannot be answered, the data packet of the node B waits until the buffer space of the node A is available and then is sent, and then the buffer space of the node B is continuously occupied. If a "request-to-occupy" cache resource dependent loop is formed between multiple nodes, a so-called deadlock phenomenon occurs. Based on the above, the embodiment of the invention adopts an X-Y dimension sequence routing strategy to determine the routing direction.

Here, the X-Y dimension sequence routing strategy describes a two-dimensional network-on-chip structure in an X-Y coordinate system. The X-Y dimension sequence routing strategy provides that the target data packet firstly carries out the routing in the X-axis direction, and then carries out the routing in the Y-axis direction when the X address of the target address information is equal to the X address of the target data packet.

The two-dimensional network-on-chip structure provided by the embodiment of the invention comprises a plurality of processing cores, wherein a routing node in any processing core comprises five input distributors and five output arbiters, the five input distributors are used for receiving data packets sent by four adjacent routing nodes and pulse data packet coding and decoding interfaces of the processing cores, so that the data packets in five directions can be received, and the target output arbiters are used for responding to transmission requests so as to transmit the target data packets to target positions corresponding to the target output arbiters, and the target positions comprise one routing node or pulse data packet coding and decoding interface in the four adjacent routing nodes, so that the data packets can be sent to the five directions based on the five output arbiters, further the parallel processing of the five data packets is realized, and finally the throughput rate of the two-dimensional network-on-chip structure is improved; any input distributor is used for sending a transmission request of a target data packet to a target output arbiter, the target output arbiter is determined based on a target routing direction, and the target routing direction is determined based on destination address information of the target data packet and an X-Y dimension sequence routing strategy, so that the target output arbiter can be determined from five output arbiters based on the X-Y dimension sequence routing strategy, further, the deadlock problem is better avoided, and finally, the throughput rate of the two-dimensional network-on-chip structure is improved.

Based on the two-dimensional network-on-chip structure, the invention also provides a routing method of the two-dimensional network-on-chip structure, and the routing method is applied to the first routing node. Further, the execution body of the routing method may be a controller on an FPGA (Field Programmable Gate Array ) or a controller on a CPU (central processing unit, central processing unit), which is not limited in this embodiment of the present invention. Fig. 5 is a schematic flow chart of a routing method of a two-dimensional network-on-chip structure according to the present invention, as shown in fig. 5, where the routing method of the two-dimensional network-on-chip structure includes:

step 510, receiving a first target data packet sent by a second routing node, and determining a position relationship between the second routing node and the first routing node in a two-dimensional network-on-chip, where the second routing node is an adjacent routing node of the first routing node.

Here, the first routing node may be any routing node in a two-dimensional network-on-chip structure.

Here, the second routing node is an adjacent routing node of the first routing node, an X-Y coordinate system is established based on the two-dimensional network-on-chip structure, and a positional relationship between the first routing node and the second routing node in the two-dimensional network-on-chip can be determined.

Here, the positional relationship of the first routing node and the second routing node includes a first positional relationship, a second positional relationship, a third positional relationship, and a fourth positional relationship. The first position relation is a first input direction of the first routing node, the second position relation is a second input direction of the first routing node, the third position relation is a third input direction of the first routing node, and the fourth position relation is a fourth input direction of the first routing node.

In an embodiment, the first input direction is the east direction, the second input direction is the west direction, the third input direction is the south direction, and the fourth input direction is the north direction. Based on the above, the first positional relationship is the eastern direction of the first routing node, the second positional relationship is the western direction of the first routing node, the third positional relationship is the southern direction of the first routing node, and the fourth positional relationship is the north direction of the first routing node.

It should be noted that, the processing core where the first routing node is located in a central area of the two-dimensional network-on-chip structure, and the first routing node has four adjacent routing nodes. There are four possibilities of the positional relationship of the first routing node and the second routing node.

Step 520, determining a first target input dispatcher from the five input dispatcher of the first routing node based on the position relationship, and sending the first target data packet to the first target input dispatcher.

The five input distributors include an input distributor corresponding to the first position relation, an input distributor corresponding to the second position relation, an input distributor corresponding to the third position relation, an input distributor corresponding to the fourth position relation, and an input distributor corresponding to the fifth position relation. Here, the first destination input allocator is determined according to a positional relationship between the first routing node and the source of the first destination packet.

In an embodiment, the input distributor corresponding to the first position relationship is an input distributor in the eastern direction of the first routing node, the input distributor corresponding to the second position relationship is an input distributor in the western direction of the second routing node, the input distributor corresponding to the third position relationship is an input distributor in the southern direction of the third routing node, the input distributor corresponding to the fourth position relationship is an input distributor in the northern direction of the fourth routing node, and the input distributor corresponding to the fifth position relationship is an input distributor in the local direction of the fifth routing node.

Step 530, determining a first target routing direction based on the destination address information of the first target data packet and the X-Y dimension sequence routing policy.

Here, the destination address information of the first destination packet may be address information of one of the four adjacent routing nodes of the first routing node and the pulse packet codec interface to which the first routing node is connected.

Here, the X-Y dimension sequence routing strategy performs transmission in the X-axis direction first and then performs transmission in the Y-axis direction according to the positional relationship between the first routing node and the second routing node. Specifically, the transmission in the east and west directions is performed first, and then the transmission in the south and north directions is performed.

Here, the first target routing direction includes a first routing direction, a second routing direction, a third routing direction, a fourth routing direction, and a fifth routing direction. The first routing direction is a first output direction of the first routing node, the second routing direction is a second output direction of the first routing node, the third routing direction is a third output direction of the first routing node, the fourth routing direction is a fourth output direction of the first routing node, and the fifth routing direction is a fifth output direction of the first routing node.

In an embodiment, the first output direction is the east direction, the second output direction is the west direction, the third output direction is the south direction, the fourth output direction is the north direction, and the fifth output direction is the local direction. Based on this, the first routing direction is the east direction of the first routing node, the second routing direction is the west direction of the first routing node, the third routing direction is the south direction of the first routing node, the fourth routing direction is the north direction of the first routing node, and the fifth routing direction is the local direction of the first routing node.

Specifically, referring to fig. 3, the destination packet is input from the west direction, and the first destination routing direction may be the east, north, south, and local directions; the target data packet is input from the eastern direction, and the first target routing direction can be the west, north, south and local directions; the target data packet is input from the north direction, and the first target routing direction can be the south direction and the local direction; the target data packet is input from the south direction, and the first target routing direction can be the north direction and the local direction; the destination data packet is input from a local direction, and the first destination routing direction may be a west, east, north, south, local direction.

Step 540, determining a first target output arbiter from the five output arbiters based on the first target routing direction.

Here, the first target output arbiter includes a first output arbiter, a second output arbiter, a third output arbiter, a fourth output arbiter, and a fifth output arbiter.

In one embodiment, the first output arbiter is an output arbiter in the eastern direction of the first routing node, the second output arbiter is an output arbiter in the western direction of the first routing node, the third output arbiter is an output arbiter in the southern direction of the first routing node, the fourth output arbiter is an output arbiter in the northern direction of the first routing node, and the fifth output arbiter is an output arbiter in the local direction of the first routing node. Based on this, the first target output arbiter is an output arbiter in the east direction of the first routing node, the second routing direction is an output arbiter in the west direction of the first routing node, the third routing direction is an output arbiter in the south direction of the first routing node, the fourth routing direction is an output arbiter in the north direction of the first routing node, and the fifth routing direction is an output arbiter in the local direction of the first routing node.

Step 550, sending, by the first target input dispatcher, a first transmission request of the first target data packet to the first target output arbiter.

Step 560, responding to the first transmission request by the first target output arbiter, so as to transmit the first target data packet to a first destination location corresponding to the first target output arbiter, where the first destination location includes a third routing node adjacent to the first routing node or a pulse data packet codec interface of the first routing node.

Referring to fig. 3, the western direction input dispatcher may send transmission requests to the output arbiters, i.e., 4 transmission requests, in the 4 directions of east, north, south, and local; the eastern direction input distributor can send transmission requests to 4 output arbiters in the 4 directions of the west, north, south and local directions, namely, 4 transmission requests; the north input distributor can send transmission requests to 2 output arbiters in the south and local directions, namely 2 transmission requests; the south direction input distributor can send transmission requests to the north and local output arbiters in 2 directions, namely 2 transmission requests; the local direction input dispatcher may send transmission requests to the output arbitrator in 5 local directions, i.e., 5 transmission requests.

Here, the reply transfer request is used to confirm whether the first target output arbiter can transfer packets with the first target input dispatcher.

The first destination location includes a routing node corresponding to the first output direction, a routing node corresponding to the second output direction, a routing node corresponding to the third output direction, a routing node corresponding to the fourth output direction, and a pulse packet codec interface corresponding to the fifth output direction.

In an embodiment, the first output direction is the east direction, the second output direction is the west direction, the third output direction is the south direction, the fourth output direction is the north direction, and the fifth output direction is the local direction. Based on this, the first destination location may be a routing node corresponding to the eastern direction, a routing node corresponding to the western direction, a routing node corresponding to the southern direction, a routing node corresponding to the northern direction, and a pulse packet codec interface corresponding to the local direction.

According to the routing method of the two-dimensional network-on-chip structure, which is provided by the embodiment of the invention, a first routing node receives a first target data packet sent by a second routing node, and based on the position relation of the second routing node and the first routing node in the two-dimensional network-on-chip structure, a first target input distributor is determined from five input distributors of the first routing node, and the first target data packet is sent to the first target input distributor, so that the data packet in five directions can be received; determining a first target routing direction based on destination address information of a first target data packet and an X-Y dimension sequence routing strategy, and determining a first target output arbiter from five output arbiters based on the first target routing direction, so that the target output arbiter can be determined from the five output arbiters based on the X-Y dimension sequence routing strategy, thereby better avoiding deadlock problems and finally improving throughput of the two-dimensional network-on-chip structure; transmitting, by the first target input dispatcher, a first transmission request of the first target data packet to the first target output arbiter; and responding to the first transmission request through the first target output arbiter so as to transmit the first target data packet to a first destination position corresponding to the first target output arbiter, wherein the first destination position comprises a third routing node adjacent to the first routing node or a pulse data packet encoding and decoding interface of the first routing node, so that the data packet can be sent to five directions based on the five output arbiters, further, the parallel processing of the five data packets is realized, and finally, the throughput rate of the two-dimensional network-on-chip structure is improved.

Based on any of the above embodiments, considering that the condition that route starvation occurs is that when NoC network traffic is very large, output channels are continuously in an occupied state, a request from an input channel with the lowest priority will not be answered until other input channels no longer occupy the output channels, resulting in a rapid rise in route delay of a specific channel and path, which greatly increases the risk of route blocking. Based on this, in the method, in step 560, the responding to the first transmission request includes:

and determining the response time of the first transmission request based on a preset transmission request priority rule.

And responding to the first transmission request based on the response time.

Wherein the transmission request priority rule includes at least one of:

Here, the input distributor corresponding to the pulse packet codec interface is the input distributor of the local input channel.

In an embodiment, for the five output channels, namely, east, west, south, north and local, the priority of the transmission request sent by the local input channel is highest, so that the congestion condition of the local input channel can be reduced, the core circuit is prevented from suspending operation, and the throughput rate is improved.

Here, the second input distributor is an input distributor having a Y coordinate, and the second input distributor is an input distributor having an X coordinate.

In an embodiment, the first input splitter may be an input splitter in the east and west directions, and the second input splitter may be an input splitter in the north and south directions. For the north, south and local output channels, requests from the east and west input channels have higher priority than the north and south input channels. Because the condition of turning from east and west input channels to south and north output channels only happens when the data packet just ends the X-direction route and turns to the Y-direction route; the case of switching from the east and west input channels to the local output channel only occurs when the Y addresses of the source core and the destination core of the packet are the same and the X-direction routing is just ended. The traffic of the two cases is smaller, the occupation frequency of the output arbiter is lower, and the priority treatment can be carried out.

It should be noted that the two cases of smaller traffic are because when these two cases occur, only the local, Y-direction output arbiter is occupied.

Here, the third transmission request is a request sent by an input distributor on two input channels on the X-axis, including a request received by an output channel in the south direction from an input channel in the east and west directions; a request of an input channel in the east and west directions is received by an output channel in the north direction; the output arbiter in the local direction receives requests from the input channels in the east and west directions.

In one embodiment, the first transmission request and the third transmission request are input channel requests from east and west directions received by the output channel in the north direction, and the first transmission request and the third transmission request are alternately responded, that is, the input channel of the last received request has a lower priority.

According to the routing method of the two-dimensional network-on-chip structure, which is provided by the embodiment of the invention, the request priority from the local input channel is highest, and the core circuit is ensured to work normally. The method and the device have the advantages that two conditions of turning from an east input channel to a north output channel and turning from the east input channel to a west input channel and turning from the east input channel to the west input channel to a local output channel are preferentially processed, the flow of the two conditions is smaller, and the occupation frequency of an output arbiter is lower. Alternating the first transmission request and the third transmission request avoids that the same input channel is always assigned a low priority. By the means, the routing delay of the specific channel and the route is further reduced, the risk of route blocking is greatly reduced, and the problem of route starvation is finally solved.

Based on any of the above embodiments, the method further comprises:

and under the condition that the first target data packet is determined to be copied based on the multicast identification information of the first target data packet, copying the first target data packet to obtain a copied data packet, wherein the multicast identification information is used for determining whether the data packet is required to be copied or not.

In an embodiment, taking a two-dimensional network-on-chip structure formed by 16 cores as an example, the multicast identification information may be 4-bit information. Referring to fig. 4, if F [ i ] is 1, if each bit of F in the figure identifies multicasting of the corresponding bit of the corresponding destination address information a, it means that a [ i ] =0 and a [ i ] =1 are both destination addresses. The routing module analyzes A and F bit by bit, and judges whether the data packet is multicast copied at the corresponding bit.

And determining a third destination position based on destination address information of the first target data packet, wherein the third destination position is different from the first destination position.

Here, the third destination location is a destination location of a duplicate packet of the first target packet.

In an embodiment, taking a two-dimensional network-on-chip structure formed by 16 cores as an example, the destination address information may be 4-bit information. Referring to fig. 4, the core of address 1111 generates a packet of a=1000, f=0101. The second bit of F is 1, the second bit of a is 0, the packet is duplicated, and the destination location of the duplicated packet, i.e., the third destination location is 1100.

And sending the copied data packet to the third destination position.

In one embodiment, referring to FIG. 4, taking a two-dimensional network-on-chip architecture of 16 cores as an example, after a packet is routed to the core of address 1101, the packet replicates a packet to the core of address 1100. Thereby, the duplicate packets are sent to the third destination location.

According to the routing method of the two-dimensional network-on-chip structure, provided by the embodiment of the invention, the first target data packet is duplicated based on the multicast identification information of the first target data packet, so that the duplicated data packet is obtained and is sent to the third target position, and therefore, a routing multicast strategy is realized, and the routing multicast strategy is used as a solution of high-speed parallel data transmission, so that the transmission burden of a communication link can be effectively relieved, and the utilization rate of network bandwidth is improved.

Based on any of the above embodiments, in the method, the multicast identification information includes identification bit values of a plurality of routing rounds, and a number of bits of the multicast identification information is determined based on a number of the plurality of processing cores.

and carrying out bit-by-bit analysis on the multicast identification information of the first target data packet to obtain the identification bit value of the current routing round.

Here, the multicast identification information includes identification bit values of a plurality of routing rounds, and the number of bits of the multicast identification information is determined based on the number of the plurality of processing cores.

In an embodiment, taking a two-dimensional network-on-chip structure formed by 16 cores as an example, the multicast identification information may be 4-bit information, and the total routing round is 4 times. Referring to fig. 4, the core of the address 1111 generates a packet of destination address information a=1000 and multicast identification information f=0101. Analyzing a and F bit by bit, the first routing round, the first bit of F being 0 and the first bit of a being 1, indicates that the packet has arrived at the destination address, and no routing duplication is required. In the second routing round, the second bit of F is 1, the second bit of a is 0, the packet is copied, the copied packet enters the core of address 1011, and the second bit of F is cleared. In a third routing pass, two packets are routed to the cores at address 1001 and address 1101, respectively. In the fourth routing pass, the fourth bit of F is 1, the fourth bit of A is 0, and the two packets duplicate a packet to the core of address 1000 and address 1100, respectively. Thus, the packet completes a 1-to-4 copy.

According to the routing method of the two-dimensional network-on-chip structure, which is provided by the embodiment of the invention, the bit number of the multicast identification information is determined based on the number of the plurality of processing cores, and whether the first target data packet needs to be copied is further determined. Finally, the multicast replication technology is realized, so that the transmission burden of the communication link can be effectively relieved, and the utilization rate of the network bandwidth can be improved.

Based on any of the above embodiments, in the method, the destination address information of the first target data packet includes address bit values of a plurality of routing rounds, and the number of bits of the destination address information of the first target data packet is determined based on the number of the plurality of processing cores;

Here, the number of bits of the destination address information of the first target packet needs to be determined according to the number of the plurality of processing cores. In one embodiment, taking a two-dimensional network-on-chip structure formed by 16 cores as an example, the number of bits of the destination address information of the first target packet is 4.

According to the routing method of the two-dimensional network-on-chip structure, provided by the embodiment of the invention, the address bit value of the current routing round is determined based on the destination address information of the first target data packet, and the third destination position is determined by comparing the address bit value of the routing round with the source address information of the first routing node, so that a multicast replication technology is realized, and finally, the transmission burden of a communication link is effectively relieved, and the utilization rate of network bandwidth is improved.

Based on any of the above embodiments, fig. 6 is a second flow chart of a routing method of a two-dimensional network-on-chip structure according to the present invention, as shown in fig. 6, where the routing method of the two-dimensional network-on-chip structure includes:

step 610, receiving a second target data packet sent by the pulse data packet codec interface of the first routing node.

Step 620, determining a second target input dispatcher corresponding to the pulse data packet codec interface of the first routing node from the five input dispatcher of the first routing node, and sending the second target data packet to the second target input dispatcher.

Here, the second destination packet is a packet sent in the local direction of the first routing node.

Here, the second target input dispatcher is an input dispatcher in a direction local to the first routing node.

Only one of the five input splitters corresponds to the pulse packet codec interface.

Step 630, determining a second destination routing direction based on the destination address information of the second destination data packet.

Here, the destination address information of the second destination packet may be address information of one of the four adjacent routing nodes of the first routing node and the pulse packet codec interface to which the first routing node is connected.

Here, the second target routing direction includes a first routing direction, a second routing direction, a third routing direction, a fourth routing direction, and a fifth routing direction. The first routing direction is a first output direction of the first routing node, the second routing direction is a second output direction of the first routing node, the third routing direction is a third output direction of the first routing node, the fourth routing direction is a fourth output direction of the first routing node, and the fifth routing direction is a fifth output direction of the first routing node.

Step 640, determining a second target output arbiter from the five output arbiters of the first routing node based on the second target routing direction.

Here, the second target output arbiter includes a first output arbiter, a second output arbiter, a third output arbiter, a fourth output arbiter, and a fifth output arbiter.

In one embodiment, the first output arbiter is an output arbiter in the eastern direction of the first routing node, the second output arbiter is an output arbiter in the western direction of the first routing node, the third output arbiter is an output arbiter in the southern direction of the first routing node, the fourth output arbiter is an output arbiter in the northern direction of the first routing node, and the fifth output arbiter is an output arbiter in the local direction of the first routing node. Based on this, the first target output arbiter is an output arbiter in the east direction of the first routing node, the second routing direction is an output arbiter in the west direction of the first routing node, the third routing direction is an output arbiter in the south direction of the first routing node, the fourth routing direction is an output arbiter in the north direction of the first routing node, and the fifth routing direction is an output arbiter in the local direction of the first routing node

Step 650, sending, by the second target input dispatcher, a second transmission request of the second target data packet to the second target output arbiter.

Step 660, responding to the second transmission request by the second target output arbiter, so as to transmit the second target data packet to a second destination location corresponding to the second target output arbiter, where the second destination location includes a fourth routing node adjacent to the first routing node or a pulse data packet codec interface of the first routing node.

In one embodiment, referring to fig. 3, the local direction input dispatcher may send transmission requests to the output arbiters, i.e., 5 transmission requests, in the 5 directions east, south, west, north, and local.

Here, the reply transfer request is used to confirm whether the second target output arbiter can transfer packets with the second target input dispatcher.

The second destination location includes a routing node corresponding to the first output direction, a routing node corresponding to the second output direction, a routing node corresponding to the third output direction, a routing node corresponding to the fourth output direction, and a pulse packet codec interface corresponding to the fifth output direction.

The following describes a routing device of a two-dimensional network-on-chip structure provided by the present invention, and the routing device of the two-dimensional network-on-chip structure described below and the routing method of the two-dimensional network-on-chip structure described above can be referred to correspondingly.

Fig. 7 is a schematic structural diagram of a routing device with a two-dimensional network-on-chip structure according to the present invention, as shown in fig. 7, where the routing device with a two-dimensional network-on-chip structure includes:

a data packet receiving module 710, configured to receive a first target data packet sent by a second routing node, and determine a positional relationship between the second routing node and the first routing node in a two-dimensional network on chip, where the second routing node is an adjacent routing node of the first routing node;

A distributor determining module 720, configured to determine a first target input distributor from the five input distributors of the first routing node based on the location relationship, and send the first target data packet to the first target input distributor;

a direction determining module 730, configured to determine a first target routing direction based on destination address information of the first target data packet and an X-Y dimension sequence routing policy;

an arbiter determination module 740 configured to determine a first target output arbiter from the five output arbiters based on the first target routing direction;

a request sending module 750, configured to send, through the first target input dispatcher, a first transmission request of the first target data packet to the first target output arbiter;

and a request response module 760, configured to respond to the first transmission request through the first target output arbiter, so as to transmit the first target data packet to a first destination location corresponding to the first target output arbiter, where the first destination location includes a third routing node adjacent to the first routing node or a pulse data packet codec interface of the first routing node.

Fig. 8 illustrates a physical structure diagram of an electronic device, as shown in fig. 8, which may include: processor 810, communication interface (Communications Interface) 820, memory 830, and communication bus 840, wherein processor 810, communication interface 820, memory 830 accomplish communication with each other through communication bus 840. The processor 810 may invoke logic instructions in the memory 830 to perform a routing method for a two-dimensional network on chip structure, the method comprising: receiving a first target data packet sent by a second routing node, and determining the position relation between the second routing node and the first routing node in a two-dimensional network-on-chip, wherein the second routing node is an adjacent routing node of the first routing node; determining a first target input distributor from five input distributors of the first routing node based on the position relation, and sending the first target data packet to the first target input distributor; determining a first target routing direction based on destination address information of the first target data packet and an X-Y dimensional sequence routing strategy; determining a first target output arbiter from the five output arbiters based on the first target routing direction; sending, by the first target input dispatcher, a first transmission request of the first target data packet to the first target output arbiter; and responding to the first transmission request through the first target output arbiter so as to transmit the first target data packet to a first destination position corresponding to the first target output arbiter, wherein the first destination position comprises a third routing node adjacent to the first routing node or a pulse data packet encoding and decoding interface of the first routing node.

Further, the logic instructions in the memory 830 described above may be implemented in the form of software functional units and may be stored in a computer-readable storage medium when sold or used as a stand-alone product. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

In yet another aspect, the present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, is implemented to perform a method of routing a two-dimensional network-on-chip structure provided by the above methods, the method comprising: receiving a first target data packet sent by a second routing node, and determining the position relation between the second routing node and the first routing node in a two-dimensional network-on-chip, wherein the second routing node is an adjacent routing node of the first routing node; determining a first target input distributor from five input distributors of the first routing node based on the position relation, and sending the first target data packet to the first target input distributor; determining a first target routing direction based on destination address information of the first target data packet and an X-Y dimensional sequence routing strategy; determining a first target output arbiter from the five output arbiters based on the first target routing direction; sending, by the first target input dispatcher, a first transmission request of the first target data packet to the first target output arbiter; and responding to the first transmission request through the first target output arbiter so as to transmit the first target data packet to a first destination position corresponding to the first target output arbiter, wherein the first destination position comprises a third routing node adjacent to the first routing node or a pulse data packet encoding and decoding interface of the first routing node.

The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.

From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A two-dimensional network-on-chip structure, comprising:

2. A method of routing a two-dimensional network-on-chip structure, wherein the two-dimensional network-on-chip structure is the two-dimensional network-on-chip structure of claim 1, the method being applied to a first routing node, the method comprising:

3. The routing method of the two-dimensional network-on-chip structure according to claim 2, wherein said replying to the first transmission request comprises:

responding to the first transmission request based on the response time;

wherein the transmission request priority rule includes at least one of:

4. The routing method of a two-dimensional network-on-chip structure of claim 2, further comprising:

and sending the copied data packet to the third destination position.

5. The routing method of the two-dimensional network-on-chip structure of claim 4, wherein the multicast identification information comprises identification bit values of a plurality of routing rounds, the number of bits of the multicast identification information being determined based on the number of the plurality of processing cores;

6. The routing method of the two-dimensional network-on-chip structure of claim 4, wherein the destination address information of the first target packet includes address bit values of a plurality of routing rounds, and wherein the number of bits of the destination address information of the first target packet is determined based on the number of the plurality of processing cores;

7. The routing method of a two-dimensional network-on-chip structure of claim 2, further comprising:

8. A routing apparatus of a two-dimensional network-on-chip structure, wherein the two-dimensional network-on-chip structure is the two-dimensional network-on-chip structure of claim 1, the apparatus deployed at a first routing node, the apparatus comprising:

9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements a routing method for a two-dimensional network on chip structure according to any one of claims 2 to 7 when the program is executed.

10. A non-transitory computer readable storage medium, having stored thereon a computer program, which when executed by a processor, implements a routing method of a two-dimensional network on chip structure according to any of claims 2 to 7.