JPS63501663A - multiprocessor communication device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] The present invention provides a special purpose processing unit for use within a computer system. field, especially between individual computers in a multicomputer data processing system The present invention relates to a communication processor for communication.

7 on Neumann's basic computer architecture improvements. Attempts have been made. 7 on Neumann's design consists of a central processing unit coupled to memory. It consists of a management unit. This central processing unit stores It has the role of executing various calculations specified by the program. these The data used for calculations is also stored in that memory. This memory is multiple It consists of memory slots, which are called words. central processing unit The storage capacity of the card itself is extremely small. Typically, the central processing unit Fetches the next instruction to be executed and then retrieves any necessary data that is not yet in the central processing unit. retrieve the data, execute the instruction in question, and store the result back in memory .

The basic von Neumann system uses the speed of a central processing unit to Temp speed is limited.

One traditional solution to the speed limit of the basic 7-on Neumann design is Connecting multiple processing units to the same memory unit. their respective Processing units are connected to a common bus that links them to memory. It is continued. Each processing unit runs independently from the other units. Mail Two processing units trying to control the bus at the same time to access the Some form of arbitration is used to resolve conflicts between knits. The system A program to be executed is decomposed into a number of subprograms, each of which Executed by one of the processing units. This form of concurrency The ability to improve speed is due to the use of a common bus linking memory to each processing unit. limited by what is necessary. If one processing unit processes this for 10 clocks, memory to obtain instructions and data needed to keep busy for a cycle If access is required for one clock cycle, 10 processing units are required. can only be productively connected to the bus.

The internal storage capacity of these individual processing units is extremely small, so memory access The ratio of process cycles to computation cycles is extremely high for this type of system. big.

One conventional method to solve the speed limit of the above-mentioned shared bus system is to It uses a processing unit with its own memory. This design allows for various processing and communicating with their respective memories through one internal bus. Re The program consists of many subprograms executed by individual processors. It can be divided into

Since each individual processing unit contains a significant amount of memory, its communication links The ratio between the time required for communication and the time required for computation without such communication is This is extremely small compared to that in the shared bus system described above. This also applies from the following example It's something to understand.

Simple with 98 instructions requiring the use of a single data word stored in memory Consider a program that requires a second data word. Such a de Typically 1000 data words should be processed by this program. In some situations, memory is accessed 100 times each time a word is processed. must be This data word must be retrieved from memory.

Next, the program's 98 instructions must be retrieved, which requires memory An additional 98 accesses are required. Finally, the results must be memorized. .

In some bus-sharing systems, this program is called lo.

The number of times memory must be accessed to apply zero data words is , 100,000. If a processing unit has its own memory, For example, the communication link processes 1000 data words plus 98 instructions only once. processing unit and the 1000 resulting data words from the processing unit. It only needs to be used to send back. In this way, this communication link for a computational operation that required 100,000 accesses on a shared bus system. Therefore, only 2098 accesses are sufficient. This means that a larger number of Units will be able to share the same communication link.

However, sooner or later the communication link that services all of its processing units Since there is a limit to the ability of

When a communication link reaches its limit, another level of communication link can be installed to A lamid-like architecture must be formed. Two or more of the various processing units Each of the above systems is called a “cluster”, but these are “super communication links”. This super communication link is combined by providing a Processors are used to communicate tasks between each cluster, and each cluster communicates their tasks to the individual processing units through internal communication links. child There are several problems with this solution to communication link overloading.

First, the super communication link processor can handle only a few clusters. . This can be seen from the following. That is, super communication links connect individual Does not have a larger capacity than one of the buses. The reason for this is that if a larger capacity If it were possible to create a super communication link with This is because it could have been used for raster as well. Here, one cluster Consider the case where each processor in Try. The number of processors in the cluster is set such that the cluster bus operates at full capacity. That is, the capacity of this bus is chosen to Receives work for support and redirects the results of those tasks through the super communication link. It is saturated by the communication tasks required to make a turn. However, this each piece of data had to come from a super communication link. Therefore, a super communication link is also required to service this one cluster. It must be saturated by the load. In this way, super - A communication link can only service one cluster.

This means that each processor in the cluster gets its work from a super communication link. This is the result assuming that the

Therefore, in order for a super communication link to serve more than one cluster, each The cluster generates and “consumes” most of the communication traffic on its internal bus. There must be. This restricts the use of such pyramid architectures. limit The big improvement from including memory in each processing unit is It does not have similar improvements at the per communications link processor level.

The improvements mentioned at the outset allow programs to communicate with each processing unit to other processing units. This result eliminates the need for repeated transfers through a common memory bus shared with . Once each of the individual processing units has programmed and This type of pyramid architecture has enough memory to store the data. It is not possible to use architecture to further improve the communication density on the communication link. It is Noh.

A second problem inherent to the pyramid cluster method is that when extending the system, The need to introduce a new type of processor, a super communications link processor. It is. VLSI manufacturing technology is based on the structure of individual processing units and memory within a cluster. This has significantly reduced the cost of high-repetition functional elements used in production. However, The cost of the small number of parts used in a per-communications link processor is extremely high. Ru. An additional level of complexity is also added in the software required to drive the system. It introduces an additional level of complexity. This software solves each class of problems In addition to managing the splitting into larger pieces to be sent to the cluster, must also manage its division into smaller parts to be assigned to processing units. do not have.

Third, each super communication link is a potential communication bottleneck. same sue Two clusters attached to the par communication link processor handle large amounts of information (methods). Consider a situation where you need to replace a sage (called sage).

This exchange occupies a lot of time on the super communications link processor, thereby Messages between other clusters attached to that super communication link processor. There is a possibility that there will be no time left for the page transmission. As a result, those other If the raster cannot be worked on and becomes idle, reducing the throughput of the system. things can happen. To avoid this kind of problem, use an unsaturated rotating super – Requires a means to reroute messages through a communications link processor. Ru. It is this type of pillar that assembles a convenient configuration that provides such an alternative route. This is difficult with mid-architecture.

Finally, this type of pyramid architecture is not sufficiently fault tolerant.

When the number of processing units in a system is increased, one processing unit may be damaged due to an increase in malfunctions. Sometimes you have to take knits off the line. If the processing unit in question If the knit is a super communications link processor, the client it was servicing The entire raster must be taken out of service.

Therefore, it is an object of the present invention to To provide an improved communications processor and architecture for communications. Ru.

Another object of the present invention is to provide a solution to any large multipurpose device without adding new communication components. communication processors and communication architectures used to build multiprocessor systems; The goal is to provide technology.

Yet another object of the invention is to automatically route messages around bottlenecks. The aim is to provide a trust network.

Yet another object of the invention is to provide a fault tolerant communications processor. Ru.

These and other objects of the invention will be described in detail in the following detailed description of the invention. , and the accompanying drawings.

Summary of the invention The present invention consists of a communication network formed by a plurality of communication processors. These communication processors can be used in any two processors in a multiprocessor data processing system. Connect each other so that messages can be sent efficiently even between two processors has been done. This data processing system consists of multiple data processors, which They are preferably the same. Each data processor is connected to a communications processor. This communication processor is connected to other data processors that are connected to itself and to other data processors. is responsible for sending and receiving messages to and from the communication processor of the computer. These communication processes The sensors are organized into a two-dimensional hexagonal array.

Each communications processor has six adjacent communications processors and six ports. communicate through. Each of these ports has its own communications processor adjacent to it. to the corresponding port of one of the six communication processors.

A given data processor can interact with other data processors in a multiprocessor system. When you want to send a message to a server, put the message in its own memory, It then sends a signal to a communications processor coupled to it.

The communications processor accesses the memory of the data processor. Metsuse A signal indicating that the message is ready to be sent is sent by the communications processor to the memory of the data processor. Contains the information necessary to search for the corresponding message within.

Once this signal is given, the data processor is free to perform other calculations. can continue. In this way, the communication processor Virtually all the overhead associated with communicating with other data processors within the system It removes it from the data processor.

This communications processor connects to one adjacent communications processor through an appropriate port. Send a message. If the final destination of this message is If the data processor is coupled to and stored in the memory of the data processor. If the recipient sends the message If the data processor is not connected to the adjacent communication processor, then the adjacent communication The communications processor relays the message to an adjacent third communications processor.

In this way, a message is sent to a program bound to its final destination, a data processor. It is relayed until it reaches the processor.

The message routing algorithm used by each communications processor is Communication bottlenecks created by processor malfunction or local communication overload Automatically send messages via alternate routes around the road. If you receive a message, should be sent to the communication processor and automatically rerouted.

Communication processors at the edges of the hexagonal array are coupled to each of their ports. , and does not have an "adjacent" communication processor port. lacking such a bond The boats connected to the router are connected to a routing switch, which Connect those ports to opposite edges of the hexagonal array by external signal paths. be coupled to a communication processor or processor. The opposite side of this hexagonal array Joining to a message is a message whose destination is far from the data processor where the message originated. To reduce the transmission time of messages. This external signal path system is shown to give the shortest bus length in a hexagonal array. These guys Gibot also provides a way to communicate with the outside world of multiprocessor systems. 2, which is analogous to input-output ports in conventional computers. It is.

Brief description of the drawing FIG. 1 shows a communication network according to the invention.

FIG. 2 is a detailed diagram of the coupling between corresponding ports of adjacent communication processors. .

Figure 3(a) shows a larger network consisting of seven small hexagonal communication networks. Illustrating a communication network in the form of

Figure 3(b) shows an alternative configuration for the large communications network shown in Figure 3(a). vinegar.

Figure 4(a) shows a non-adjacent communication process in a communication network based on a hexagonal array. shows the routing of messages between servers.

Figure 4(b) shows non-adjacent communication processes in a communication network based on a rectangular array. Shows the routing of messages between servers.

Figure 5 shows the schematic used to connect ports on opposite edges of a hexagonal array. shows the GNAL path connection.

Figure 6(a) shows which ports on the edges of the hexagonal array should be connected to each other. We will show you how to decide.

FIG. 6(b) shows the numbering of the ports on each communications processor.

FIGS. 7(a) and 7(b) each show a six-way network with three communication processors on each side. Routing diagram for communication processors in a rectangular array Indicates the time.

Figure 8 shows the coordinate system for locating a given communication processor in an infinite hexagonal array. shows.

Figure 9 is a hexagon with three communication processors on each side of the coordinate system shown in Figure 8. Indicates conformance to the array.

FIG. 10 is a block diagram of a communications processor used in a preferred embodiment of the present invention.

Figure 11 is executed by the port controller when a packet is sent. It is a flowchart of operation.

Figure 12 shows the flow of operations performed by a port when a packet is to be sent. -This is a chart.

Figure 13 is a flowchart of the operations performed by a port when a packet is received. It is a chart.

Detailed description of the invention The present invention provides a method for communicating between data processors in a multiprocessor data processing system. It consists of a communications network for transmitting messages. Each data tap A processor is a communications processor that communicates with other communications processors in its network. connected to the processor. As will be apparent to those skilled in the art, various data processors Each device consists of two or more processing units coupled to a single memory. can be replaced by a cluster of data processors. According to the present invention, 1 A communications network with nine communications processors is shown in FIG. Make it easy to understand one or more data processors connected to each communication processor Not yet. The communication network includes a communication processor 22 that includes various communication processes. The hexagonal array 20 consists of a hexagonal array 20. A larger communication network is Can be constructed using hexagonal arrays with more communication processors on each side. can.

Each communication processor is represented by a hexagon. Because it's the communication professional next door. This is because it has six ports for communication with processors. This is the message You can send or receive from any of the ports. This is shown in detail in Figure 2. It is. The ports 24 of each communication processor are numbered from 1 to 6. . Each port 24 is connected to a corresponding port 24 of an adjacent communication processor. . Port 1 is connected to port 4 of an adjacent communication processor. Port 2 is next door It is connected to port 5 of another adjacent communication processor. Port 3 is connected to the adjacent is connected to port 6 of another communications processor. The same applies below. hexagonal a The boat connections used for the various communication processors on Ray's Edge are detailed below. I will explain.

The communications processor itself performs several tasks, as detailed further below. It is a concurrent processor that has the ability to process simultaneously. Each of the ports is Operates independently from other ports. This makes it difficult to send several messages at once or can be received. In addition, other messages are sent and received by the ports. Messages can then be transferred to processor memory while can.

Messages are routed between communication processors; the message to an adjacent communications processor, which in turn forwards it to the adjacent communications processor. the message passes to one of the processors, and the message is sent to the final destination, the data processor. communication processor connected to the server. suitable In an embodiment, the routing algorithm used for this process is The entire communication network must be Note that it does not require global information such as a network map.

Such information is dictated by the number of communication processors in the communication network. would have to be stored in a table of size. If you are on a network If the number of communication processors increases, the size of these tables also increases. Indispensable. This fixes all communication processor hardware changes , which is clearly undesirable. As stated below However, the present invention avoids the use of such tables.

According to the invention, one data processor is connected to other data processors in a hexagonal array. When you want to send a message to a data processor, the data processor you want to send the message to transfer the file to its own memory along with its destination. Next, connect the self-connected communications Send a signal to Sessa. A communication processor connected to that data processor access the memory of the data processor. The communication processor Do not read messages from processor memory. After that, the data processor is useless. It is unnecessary to take further actions that affect message transmission.

The transmitting communications processor encodes the message for transmission and to one of its ports. If the final destination of the message is an adjacent communication If the data processor is connected to one of the processors, the two communication A port connecting the processor is assigned to the message. If the message is If the final destination is a more distant data processor, you can use the method detailed below. Therefore, the port that minimizes the transmission time is selected.

When a communications processor receives a message on one of its ports, the communications processor checks the information contained in the message header that specifies the final destination of the message. , thereby transmitting the message to a data processor connected to said communication processor. Determine if the data should be sent to the service provider. This header information is initially placed in the message by the communications processor that sent it.

If the data processor is the final destination, the communications processor Store the message in the processor's memory and send the message to the data processor. Announce the arrival of Ji. If the data processor If not, the communications processor sends the message to the data processor connected to it. Retransmit as if the message originated in the processor.

This type of hexagonal array communication topology has several advantages over previous techniques. It has a certain point. Free-size communication network uses a single hexagonal array or can be constructed by combining several hexagonal arrays. No. Figure 3(a) shows that seven small hexagonal arrays 32-38 can be combined. This figure shows a possible large-scale network. In this example, each small The RAY contains 19 communication processors.

The communication processor at the center of each array is numbered by the array. I wanted to make it clear For this purpose, the boundaries of each array are outlined with dotted lines. Any number of such The combination of rays eliminates the need to introduce any connecting elements into the communication network. It is possible to do so. Therefore, in the present invention, in the conventional system, various groups are A special purpose communication processor used in combination with a data processor , has been excluded.

A second network similar to that shown in Figure 3(a) is shown in Figure 3(b). . This consists of 7 arrays of 32'-38''. Figure 3(b) From the network shown in , array 33' is higher than array 34'. This is different from the array 34 in FIG. 3(a) which is higher than the array 33. child The importance of combining these types of arrays is discussed in more detail below. do.

A shared bus, or Communication “The lack of a hub eliminates communication bottlenecks associated with traditional design methods.” has been avoided. If a given communications processor malfunctions or If you are unable to receive a message because there are messages left that should not be sent, Messages can be routed automatically around them, as detailed below. Can be done. Depending on the size of the data processing system, the hexagonal array may be As is increased by increasing the size of one hexagonal array, the given It should be noted that the number of possible communication paths for a message also increases. Ru. To this end, the capacity of a system to automatically reroute messages is With the increase in the amount of messages related to the number of data processors in the system, Increase automatically.

This choice of hexagonal arrays as opposed to other two-dimensional arrays was dictated by two considerations. Illustrated. They improve the efficiency and communication of multiprocessor data processing system manufacturing. It is the efficiency of message routing around the Shinwa Road. data processor preference Preferred embodiments are intended for fabrication on a single chip or single wafer.

The efficiency of surface area utilization of the chip or wafer is one important factor. why If so, it determines the number of processors included in the data processing system. It is. A hexagon is the highest order regular polygon and is used to cover a surface without any gaps between polygons. be able to. Therefore, the hexagonal shape is the best polygon to make efficient use of the chip surface area. It is a quadrilateral. Furthermore, if you use a polygon with more edges than that, then in the array The manufacturing process is complicated by the need for cross-connections between the various communications processors in the Become. Therefore, the array is not hexagonal, trigonal, quadrilateral, or trigonal. Therefore, the processor array should not have a particular orientation. This thing is , in addition to covering the entire surface of the chip, the processor array covers the communications processor area. Requires that the ray must be symmetrical about two orthogonal axes in the plane containing it. is equivalent to Since triangles and arrays of triangles lack this symmetry, communication networks.

This reduces the possible choices to an array of hexagons and quadrilaterals.

The choice of a hexagonal array over a quadrilateral array depends on the communication efficiency around the local bottleneck. This is for the purpose of This is illustrated in FIG. In Figure 4(a), the main A portion of the hexagonal array according to lighting is shown at 40. The communication processor 42 However, consider a message whose final destination is communications processor 44.

The optimal route for this message is through communications processor 48. This le The message is transmitted twice, once by the communication processor 42 and again by the communication processor 42. It needs to be transmitted once by communication processor 48. If the communication process If the processor 48 is unable to receive messages due to overload or malfunction. If not, the message is sent along one of two alternative paths. That pa The first one passes through communication processors 43 and 45, and the second one passes through communication processors 43 and 45. 46 and 47.

Each of these alternative buses requires the message to be transmitted three times, i.e., rather than through the optimal bus. Requires an extra transmission once.

In FIG. 4(b), a similar portion of the quadrilateral array of communications processors is shown at 50. There is. Here, the communication processor 52 sends a message and its final destination is the communication processor 54. Let's think about a certain message. Time required for only one pass, i.e. two transmissions The path that can be transmitted with a delay equal to is the path through the communication processor 56. if If the communications processor 56 does not receive a message due to overload or malfunction. If not, the message is routed to the communication processors 5g, 60 and 62. Must be. As a result, the transmission time is the same as the time required for four transmissions.

Therefore, under overload and malfunction conditions, access to non-adjacent communication processors is Hexagonal arrays are superior to quadrilateral arrays because they require shorter alternate buses.

The communication processors on the edges of the hexagonal array have There are not enough adjacent communication processors to join. For example, three communication For a hexagonal array with processors on each side, the communication processors on the edge The number of adjacent communication processors they can couple to is only three or four. This thing is This is shown in Figure 5, which consists of 19 communication processors (3 communication processors on the - side). One hexagonal array 70 with a processor) is shown. On the edge of array 70 Each of the communication processors 74 includes two communication processors that are not coupled to an adjacent communication processor. Or it has 3 ports. A typical such port is indicated by 72. be. These ports will be referred to as peripheral boats below. Each peripheral port is It is connected to a routing switch 76. Each routing switch has two It has routing ports 78 and 80.

Each of the routing boats 80 has a route on the opposite edge of this hexagonal array. For the routing port 80 of the switching switch 76, the signaling port 82 is connected by a local bus. The other one or more of each of the various edge communication processors 74 or the signal path and routing switch 76 connected to the two ports. , have been omitted from FIG. 5 for clarity. In this way, some Messages leaving one of the peripheral ports of Tsuji communication processor 74 are sent to a hexagonal array. Wraps around to opposite edge. This is far away from each other in the hexagonal array. To reduce the time required to transmit messages between distant communication processors. either The selection of which peripheral ports are coupled by a given signal path is detailed below. state

The second routing port 78 of each routing switch 76 has a hexagonal array. Used to connect to the “outside world”. It is the standardization of traditional data processing systems. It functions as a common input-output port. If an external device connects to this hexagonal array, When you want to send a message, send said message to the route connected to that array. The signal is sent to switch 76. Next, this routing switch 76 sends the message is relayed to the communication processor 74 connected thereto.

These routing switches 76 use the data in the header information of each message to be controlled. Messages to be transmitted to the “outside world” are sent using predetermined headers. This predetermined header is encoded with the message from the adjacent communication processor 74. Specifies an internal destination recognized by the routing switch 76 that receives the message. similar external device directed to the data processor connected to the hexagonal array. messages from the device, along with a header that identifies the data processor in question. coded. When switch 76 receives such a message, it connects to itself. send it to the connected communications processor.

The selection of peripheral ports connected by signal path 82 is determined by two considerations. I can't stand it. First, these connections often pass messages between communication processors. The purpose is to determine the time required for transmission. It is important to minimize this time . Second, through proper selection of peripheral port connections, as detailed below. In the resulting communications network, communications processors 74 on the edge of the array becomes indistinguishable from what is at the center of the hexagonal array. This is an individual communication Increase efficiency of processor manufacturing. In addition, this results in the communication processor It can also be used for hexagonal arrays of any size.

The selection of which peripheral ports should be interconnected is determined by the 19 communication processors. communication network (of which three communication processors are located at each edge). This is well explained in FIG. The method for determining the connection is shown in Figure 6(a). It can be more easily understood by referring to the diagram shown below. This diagram is 19 communication processors connected to 6 phantom communication networks 86-91. A communication network 84 is shown. Each phantom communication network is It is a copy of communication network 84. Each communication network in the communication network 84 The processor identifies the location where it appears in the communications network. It is labeled a. Phantom Network 86-91 is also labeled is attached. As can be seen above, each communication processor has a It has 6 ports labeled 1 to 6 as shown in the figure. which two Connections between communication processors also provide labels for each of the ports connected to each other. and giving a label for the communications processor containing each of those ports. You can specify more. For example, in the communication network 84, the communication processor 3a Port 6 of is connected to port 3 of communication processor 2a. Similarly, network For example, for the interconnection between two edge processors in the network 84: It becomes like this. Port 6 of communication processor 9a in communication network 84 is connected to port 3 of the communication processor 14a in the client communication network 86. Ru.

As described below, this corresponds to the signal path 82 shown in Figure 5. be.

For each peripheral boat in the communication network 84, it is necessary to connect it with a signal path. The corresponding peripheral port in the communication network 84 is determined as follows. . It identifies the peripheral port in question from within the communication network 84 and determines whether it is connected. There are suitable phantom communication networks 86.87.88, 89.90 connected to or the communication processor and peripheral ports in 91. The peripheral port is A network with the same communication processor label and port label in communication network 84 Connect to side port. For example, the communication processor 9a in the communication network 84 Port 6 is a port of communication processor 14a in phantom communication network 86. Connected to port 3. Therefore, the signal path uses the routing switch 76. , port 6 of the communication processor 9a in the communication network 84 is connected to the communication network 84 by connecting to port 3 of communications processor 14a in 84. Up As mentioned above, this is the signal path shown at 82 in FIG.

This signal path connection design connects each communications processor to one large array. It allows you to “imagine” that it is placed inside the device without a signal path connection. . Determines the routing of messages to be sent to a particular communication processor. In order to Check the communications processor to determine which communications processor the message should be sent to. All you have to do is find a communication processor with a label that matches the label of good. Examining Figure 6(a), we see that the communication processor can find out which label It does more than just look at two separate communications processors in the network 84. It is clear that this is not necessary. Therefore, this signal path connection design Messages to be transmitted between any two data processors in workpiece 84 is at most the delay required by the communication network to transmit the message twice. so that This is clearly a hexagonal architecture with three communication processors on each side. This is the smallest possible delay for the ray.

Therefore, a given communication processor, in the diagram shown in FIG. 6(a), At most, it is sufficient to memorize the parts within two communication processors from the communication processor concerned. It turns out. This part of the diagram is called the routing diagram. However, it is itself a hexagonal array centered around the communications processor. communication The routing diagrams for processors 5a and 9a are respectively seventh (a ) and FIG. 7(b). Each communication processor stores its information in this Contains related routing information. One in communication network 84 The only thing that distinguishes one communication processor from another is the memory stored in each communication processor. This is a specific routing diagram. Therefore, each communication process The hardware and software for the server are the same.

This greatly simplifies the configuration of the communication network of the present invention. less than As will be explained in detail, the routing diagrams are hexagonal It can be reduced to an algorithm that is independent of ray size.

The above analysis uses the phantom hexagonal array diagram shown in Figure 6(a). This was made from the one shown in Figure 3(a). Above As pointed out, this shape has a second possible diagram as shown in Figure 3(b). There's rum. As will be clear to those skilled in the field of topology, if a hexagonal array Phantom hexagonal signal path connections to 84 similar to those shown in Figure 3(b). Similar results are obtained when determined in terms of array diagrams. this The actual peripheral ports connected in each case will vary. However, the modified aspect of the invention is , a specific label of the routing diagram stored in each communications processor. That's it.

Finally, the above analysis considers a hexagonal array with three communication processors at each edge. This is what I used. A similar technique can be applied to a system with E communication processors on one side. It can also be applied to large hexagonal arrays of arbitrary size. Similar to that shown in Figure 6(a) A similar diagram can be constructed that shows the communication network in question in six frames. Shown with phantom copy. Those peripheral ports are connected by a signal bus. These signal paths link each peripheral port to A hexagonal array with the same label as that of the connected port and communication processor. to the communication processor port on the opposite edge of the edge. The resulting route The drawing diagram becomes a hexagonal array with E entries on each side. each The communications processor receives the E-1 communications processor from each other communications processor in the hexagonal array. It will be in the seta. This is the minimum distance between communication processors. Shown (Scblumberger Pslo Alto Re5e*r cb Report #47) 0 Therefore, the present invention provides that the message has the highest efficiency in terms of the number of retransmissions that must be made to reach the final destination. It is a communication network that

Minimize the distance between any two communication processors in a single hexagonal array In addition, signal paths and routing switches are defined in Figures 3(a) and 3(a). b) A large network combining several hexagonal arrays as shown in the figure. Provides improved performance. In such networks, routing Switches are used for connections between individual hexagonal arrays. one or more additions Communication processes located in different hexagonal arrays separated by a hexagonal array of When messages must be sent between Can be used to "jump" messages around a hexagonal array.

For example, from the communication processor labeled 37 in FIG. 3(a) to the communication processor labeled 35, Let's think about the message that should be sent to Sessa. without external signal path , this message is sent to the edge of the hexagonal array where communications processor 37 is located. It must pass from communications processor to communications processor to reach it.

This message is then passed across a hexagonal array containing communication processor 32. must be traversed in a similar manner until the edge of the hexagonal array is reached. . Finally, the message is sent to the appropriate location in the hexagonal array where the communications processor 35 is located. It passes through the appropriate communication processor and reaches the communication processor 35.

Routing switches on the edges of the hexagonal array route messages through the communication process. from the communication processor on the edge of the hexagonal array including the processor 32 to the hexagonal array relay to the communication processor at the opposite edge of the communication All communication processors in the hexagonal array, including the processor 32, are bypassed. child This greatly reduces the transmission time for messages sent to destinations far from the origin. .

As pointed out above, the important thing is that the communication processor has a hexagonal array size Contains no global information that would have to be stored in a table whose size depends on That's a good thing. This is the maximum that can be configured if such a table is requested. Large hexagonal arrays may be dependent on the available space in the table. This is because it becomes. The routing diagram mentioned above is suitable for such a table. It is bull. The present invention also provides a solution to this problem.

To avoid excessive space allocation for such tables, the present invention Using a labeling design for communication processors, this The information contained in the diagram can be stored in a way that makes storage requirements independent of the size of the hexagonal array. Reduce it to an algorithm. Therefore, the communication processor of the present invention has the following advantages: Connected as a hexagonal array, it can be used in communication networks of any size. It can be used.

The labeling design used in the present invention is shown in FIG. 8(a). “Infinity” A portion of the hexagonal array is indicated at 91'. Each communication processor has two numbers ( x, y), which are similar to coordinates in a Cartesian coordinate system. This specifies the position of each communication processor in the coordinate system. these two The numbers are shown separated by commas within each hexagon. The axis of this coordinate system is 92 It is shown. This coordinate system has non-orthogonal axes and is labeled D. It differs from a Cartesian coordinate system in that a third axis is defined. parallel to the x-axis When moving from communication processor to communication processor in the direction, the first coordinate is the direction of movement. Incremented or decremented by direction. Similarly, when moving in a direction parallel to the y-axis, , the second coordinate is incremented or decremented. Finally, when moving parallel to the D axis, Both the first and second coordinates are incremented or decremented. Each axis supports two ports. It should be noted that For example, messages sent from port l or port 4 The sage propagates in a direction parallel to the D axis. The port number is shown at 93 in Figure 8(b). It is.

Using this labeling design, the communications processor can The optimal bus can be calculated for any other communication processor without the need for This theory For purposes of this disclosure, the communications processor that is sending the message is designated as the sender, and The communication processor that is the final destination of the message will be called the receiver. Sending The believer first calculates the angle of the line connecting the sender to the receiver with respect to the X axis.

This angle is called the receiver angle. Each port is assigned a “port” corner, which is , the corner of the line connecting the sender to the communication processor adjacent to the sender connected to that port equal to degrees. The port angle is also calculated relative to the X axis. Therefore, port 1 The boat angle of port 2 is 60°, the port angle of port 2 is 120', and so on. Next, The forward port 1 and the rest are ported using the absolute value of the difference between the receiver angle and each boat angle. It is calculated by ordering the

For example, sent from the communication processor at (0,0) to the communication processor at (1,2) Let's think about it while reading the message. The center of the communication processor at the receiver angle ((0,0) The angle of the line connecting (1, 2) with the center of the communication processor) is 90°. Therefore , ports l and 2 are preferred. This is because they each have a difference angle of 30 from the receiver angle. Ports 6 and 3 each have a boat angle of This is the next most desirable port since the difference angle between the two ports is 900 boat angles. Same hereafter It's like that.

In the above example, if the receiver is (0,2), the receiver angle is 120°. Only one port, port 2, is desired. next most desired The new ports will be ports 1 and 3 in this case. The same applies below.

The above-mentioned routing algorithm applies to a finite hexagonal array communication network according to the present invention. Applicable to networks. According to the present invention, six communication processors with three communication processors on each side A communications network based on a rectangular array is shown at 94 in FIG. this The boundaries of the hexagonal array are outlined with thick lines. The relevant parts of the antom copy are shown outside this bold line.

As noted with respect to Figure 6 above, these phantom copies are A signal bus connecting opposite edges of Ray 94 is used for message routing. When used, it is used to simplify the calculation of optimal routing. These fa Each communications processor copies any other communications processor in the hexagonal array. It also makes it possible to calculate the coordinates of the communication processor.

These signal buses introduce discontinuities in the coordinate system described above. For example, (0,0 ) and proceeding along the positive y-axis, the next communication processor enters the communication processor at (0,2). The next communication processor encountered after the processor is the communication processor at (-2,-2) , and not the (0,3) communication processor in the case of an “infinite” hexagonal array. . Therefore, each communication processor must remember a number that specifies the size of the hexagonal array. the location of this discontinuity and the next communication beyond that discontinuity. We need to be able to calculate the coordinates of the processor.

The second difference between a finite hexagonal array and an infinite hexagonal array is that It can be reached by moving along many different directions relative to the target. example For example, when reaching the communication processor at (-2, -2) from the communication processor at (0, 0), by traveling along the positive y-axis or by traveling along the negative d-axis. or proceed along the positive D axis to the communication processor at (1,l) and then This is possible by proceeding along the X axis of . Select the correct bus as follows: It will be revealed. The sender determines that the recipient's coordinates are within range of the sender's E-1 communications processor. Calculate. where E is the number of communication processors on one side of the hexagonal array 94. be. A system for connecting communication processors on the edges of hexagonal array 94 as described above. The signal bus allows any communications processor to communicate with any other communications processor's E-1 communications Selected to be within the setter range.

This recipient's coordinates are once within the distance of the E-1 communications processor from the sender. will appear.

With the above modification, the sender can now use the algorithm described for an infinite hexagonal array. port used to send a message to any recipient in the hexagonal array using can be assigned in priority order. The sender shall use the sender's E-1 communication Compute the location of the communications processor with the coordinates of the recipient within processor range. child To do this, the sender must locate the recipient within the hexagonal array or a virtual copy thereof. Calculate the location of each communication processor that has the same target. Next, the sender's E- Select a communication processor located within one communication processor range. The sender then Calculates the angle of the line connecting this communication processor to the sender and sends the message. Compute a list of ports in priority order to be used. Message is the next highest priority Sent to an adjacent communications processor connected to the port. If such a port If there are two, the message is sent on the first free port. Moshiko when the adjacent communication processor is unavailable (for example, busy with other tasks). , why it is not working), and whether the message is successfully transmitted to the adjacent communication processor. The next highest priority port is used until

A preferred embodiment of a communications processor according to the present invention is shown at 100 in FIG.

It has four basic elements. The first element is buffer 102, which is Used to store messages passing through the communications processor. The second element is port controller 104, which controls the third element, the ports 106; Manage the transmission of messages. The fourth basic element is the direct storage access controller 1 0B, which is a buffer 102 and a data processor connected to the communication processor. Message transfer to and from the memory 110 of the processor 111 is managed.

For more efficient use of space in buffer 102, long messages are It is divided into multiple small messages called kets. Long mail to a series of packets The partitioning of the storage access controller directly 108. Each packet is marked with the message to which it belongs, and its Contains a header that identifies the final destination of the packet. Also, this header the number of packets in this message, and the position of the packet in this message. Contains. Finally, the header also indicates that the message was sent and received correctly. Contains error checking information used by port 106 to verify that .

Buffer 102 is divided into multiple storage slots. each memory slot is used to store one packet. In a preferred embodiment, the size of the packet is chosen to be the average message length sent in the data processing system.

Packets stored in buffer 102 are stored on bus 1 shared by six ports 106. 12 and one port 106 through the direct storage access controller 108. be transferred. Conflicts regarding the use of path 112 are caused by Solved with buffer controller. Various functions performed by the communications processor Action priorities are discussed in more detail below.

Path 112 supports all six boats 106 and the direct storage access controller. service, so packets are transferred from buffer 102 to a given port 1. 06 or directly to the storage access controller. It must be small compared to the time it takes to output a packet to a given port 106.

Otherwise, the packet is directed to port 106, which is free. Even at this time, it will have to wait in the buffer 102. In the preferred embodiment In this case, bus 112 is wide enough to transfer a packet in two bus cycles. It's the size. This is when necessary to output the packet through port 106. It is about 1/10 of that.

Each port 106 has an internal buffer sufficient to store one packet. ing. Therefore, each port 106 has a buffer 102 and another port 106. They can operate independently from each other. Port 106 is one neighbor from buffer 102 When used to forward packets to a communications processor, it The packet is transferred from buffer 102 and stored in its own internal buffer. this Port lO6 then transmits the packet regardless of other operations in the communications processor. . Similarly, if port 106 receives packets from one adjacent communications processor, If so, the port accumulates the packet in its own internal buffer.

As mentioned above, buffer 102 is configured to allocate storage space within this buffer. Contains a controller responsible for. Port 106 is stored in buffer 102 When a packet to be sent is received, this saves buffer space to buffer control. Requested by Laura. Similarly, a packet is successfully transmitted to an adjacent communication processor. When the port controller 104 sends a signal to the buffer controller , this buffer controller determines the available space occupied by the corresponding packet. Create a pace.

The flowchart of the operations performed by the port controller 104 is shown in FIG. It is shown in the figure. Port controller 104 stores packets in buffer 102. until it finds a packet ready to send.

This port controller then selects the desired one or determines multiple ports. As pointed out above, if the final destination of this packet is a data processor and its communication processor is not on a line parallel to one of the axes. has more than one optimal route to its communications processor. That is, there are two packets It is possible to send data from these ports without introducing any delay. If two or more If there are optimal ports, the port controller is free among those ports. Assign the packet to the first one. If one of the desired ports 106 If the port is free, it signals the boat in question to take the packet . If none of the desired ports are free, the counter will be incremented. Tests are made for critical values. If the count of the counter is a critical value, If the port controller is also large, the port controller chooses an alternate port for the packet. . This counter measures the number of times a packet is refused transmission, so the count is 8 is a measure of the "corruption" of the packet. Port controller 104 then: It passes through the packets in buffer 102 until it finds the next packet to send. Return to cycle operation.

If the packet is assigned I; port 106 successfully completes the transmission of the packet. When it does, port 106 sends a signal to port controller 104. port - Controller 104 then sends a signal to the buffer controller to The troller fills the space previously occupied by said packet with 7 lees. . If there is a report of packet transmission failure from the port 106, the packet The counter associated with the cut is incremented and subjected to the tests described above.

Which of these ports should I use when I have to choose an alternative port? Three factors influence the choice of . First, if the packet is sent to another communication (i.e., the communications processor simply intercepts the packet) relaying to its final destination), this packet is sent to the same port that received it. shall not be sent to If this rule is not followed, the packet will of the same communication processor until suitable routing is available. go back and forth between This is called “thrashing.” This thrashing Not only does it delay the packet from traveling to its destination, but it also This increases the communication load on the two communication processors. Boat on which the packet was received Information specifying 106 is stored in buffer 102 with the packet. child The information is provided by the port 106 that received the packet. in this way so the port controller has the necessary information to avoid this problem. Ru.

Second, larger hexagonal arrays (larger than those with 3° communication processors on the − side) In the network, a large number of packets can be sent for long-distance communication. There is a route. The port 106 selected to send the packet is Affects the number of routing decisions available for transmission. This is in the following example Therefore, it can be explained.

Referring to FIG. 8(a), the communication processor (1,-2) is left and the final destination is Regarding packets, the data processor connected to the communication processor (2, 2) Let's think about it. There are four optimal routes to (2,2), each with four optimal routes to (2,2). Requires transmission. Its first route is communication processor (1,-1), (1,O ) and (1゜l), the second route passes through the communication processor (1゜-1), ( 1,0) and (2,1), the third route is the communication processor (1,-1) ), (2,0) and (2,1), and the fourth route is the communication process. It passes through (2, -1), (2, O) and (2,1). Moshi packet is sent via communication processor (1,-1), then there are three optimal routes is possible, so the port connecting the communication processor and the communication processor (1, -1) is Port 2 is the port 1 that connects the communication processor and the communication processor (2, -1). more desirable than Port 2 allows greater flexibility in subsequent routing decisions. give.

In a preferred embodiment of the present invention, this "flexibility" information is Determining the optimal port and determining an alternative boat if the optimal port is not available. used for both. The angle calculation algorithm mentioned above automatically takes this information into account. I'm putting it in. In the above example, communication processor (1, -2) is The difference in angle between the line connecting (2, 2) and the line parallel to the y-axis passing through port 2 is the angle between the line and the angle of a line parallel to the D axis passing through port 1. Therefore. Poe point 2 will be automatically selected.

Finally, the availability of alternative ports must be considered. Here, two There are two alternative ports, which have the same length path but have less “flexibility”. Let's consider a different case. If the port with greater flexibility is busy , another port is selected. The “corruptness” of a packet (i.e., the packet is The critical value of the counter that measures the number of times the packet is refused is the number of times the packet is replayed once on average. It represents a piece of time that is longer than the time required for transmission. Therefore, sending a packet Instead of waiting for a slightly better route, it is better to take a slightly inferior route. It's better to

Other less complex routing algorithms will be apparent to those skilled in the art. is possible. For example, a port controller simply can be assigned to a randomly selected alternate port.

This port prevents packets from being routed further away from their final destination. You can choose from a variety of ports. Such a random assignment algorithm is It's not very efficient, but it requires less hardware to do this, so it's economical. It is preferable for economical reasons.

When the port controller requests port 106 to transmit a packet , a chart of the operations performed by port 106 is shown in FIG. Po If port 106 receives a request to transmit a packet, but it is busy, it transmits the packet. The port controller sends the same signal that is sent if the attempt to send is unsuccessful. Send to La 104. If the boat 106 is free, this port a signal to the buffer controller that transmits the packet to the buffer of that port 106. send. Port 106 then connects to the corresponding attempt to establish a communication link with port 106. If that fails, The ports send signals to port controller 104. If you succeed in that, The port sends the packet, and from the receiving boat 106, the packet is Wait for a signal indicating that it was received correctly. If it is not received correctly, then For example, the port 106 increments a counter. If the count of this counter is If it is less than a predetermined threshold value, the port sends the packet again. If that If the count of is greater than the critical value, then the port sends a signal indicating that transmission completion has failed. If the receiving port 106 Upon acknowledgment of success, the port 106 is sent to the port controller 104. sends a signal that the packet was successfully sent. After that, it enters the standby state.

port 106 if the adjacent communication processor wants to send a packet to port 106. FIG. 13 shows a small flowchart of the operations performed by the computer. If the port If 106 is busy when it receives the request, it sends a signal to the sending boat. send. This state indicates that the port is backing up the packet it received earlier from its buffer. This may occur if the data has not yet been transmitted to the file 102. If the port 106 is If so, it accepts the packet. At the same time, the port requests buffer space in buffer 102 from the controller.

Upon completion of the transmission, the port is checked by a normal cyclic redundancy check (CRC). Verify correct transmission of packets. If the packet was not transmitted correctly, , the port sends a signal to the sending port. If the packet is successfully transmitted and space in buffer 102 is available; sends the packet to a buffer, which is allocated by the buffer controller. stored in the specified location. When space is not available, transmit to the sending port Send a signal of failure.

Direct storage access controller 108 provides access to packets stored in buffer 102. The destination that has been waiting the longest for further processing and whose final destination is This continues until the communication processor finds a packet. direct memory access controller The troller 10B inspects the header information in the packet and determines whether this packet is extracted. Determine whether the original message received required more than one packet.

If only one packet is used, the direct storage access control The controller stores the message portion of the packet in the data processor's memory and to notify its data processor of the arrival of the message.

The direct storage access controller 10g is divided into more than one packet. Contains a table used to reassemble the message. If the message is If the direct storage access controller 108 has more than one packet, the direct storage access controller 108 Examine this table to determine if this is the first packet received from the message. decide.

If it is the first packet, the direct storage access controller 108 starts the first entry of this message into the table, and adds all messages. Allocate sufficient space in the data processor's memory to store the messages. Teru. Direct storage access controller 108 then forwards this packet to the in the memory block reserved for this message in the memory of the data processor. Store it in an appropriate location. Then, it searches for other packets in the buffer 102. Ru. If the packet in question is not the first packet of the message, it will be stored directly. The access controller 108 creates an entry indicating that it has received this packet. into the table, and then store the packet in a suitable location in the data processor's memory. Store in location. If the packet is the last one left to complete the message, package, the direct storage access controller 10g clear the message and signal the data processor that the message was received. .

When a data processor has a message to send, it directly Messages in data processor memory 110 are sent to access controller 10g. sends a signal giving the location of the target. Direct storage access controller 108 then message, assign appropriate header information to the message, and into packets. These packets are then stored in buffer 102.

The receiving communication processor sends the packets of this message to the packets of other messages. A unique message label is included in the header information to identify it from the There is. For example, this label identifies the communication processor sending the message and this a sequence number that is incremented each time a message is sent by the communications processor; It consists of

Priorities of various tasks executed by the communication processor and space in the buffer 102 The allocation is chosen to minimize the possibility of communication bottlenecks. 6 ports 1 06 and direct storage access controller 108 all share the same buffer 102. The packet is then retrieved for transmission and stored upon arrival. . This shared buffer minimizes the number of internal buses and wires required for each communications processor. This reduces the amount of buffer space required.

However, this architecture also supports buffers as shared resources. poses potential competition issues.

There are three common traffic patterns for packet transmission in a communications processor. There are two possible deadlock scenarios. Deadlock occurs because All buffer space is large enough for all adjacent communication processors to accept packets. is full of messages that are too busy to send. be. The traffic pattern is determined by the local outbound packets from a data processor to a remote communications processor; A remote communications processor whose destination is a data processor connected to that communications processor. Consists of inbound packets from the processor and the intercommunication processor The traffic is being relayed by the communication processor towards its final destination. Consists of packets originating from a remote communications processor.

Both outbound packets and intercommunication processor packets are on port 10. Take the route that passes through 6. Inbound packets are also sent to the direct storage access controller. must flow through the controller 108.

The buffer allocation algorithm used in the preferred embodiment does not create deadlocks. It is guaranteed that there will be no.

This allows packets to circulate across a communications network without deadlocks. This was achieved because the system had sufficient free buffer space. , and simultaneously use this buffer space to traverse the hexagonal array efficiently! of allocate in such a way as to result in a flow of In worse cases, packet transmission resulting in a delay.

In a preferred embodiment, buffer 102 has space for at least four packets. have. Systems with buffer space for different numbers of packets In the system simulation, a hexagonal array with three communication grossers on one side is used. The optimal buffer storage capacity in 2 is 19 packets. This buffer space The base is a rose. There are 3 packets of free space left in the border 102. - Can be used by controller 108 for traffic in any direction. child When there are three free spaces, the packets coming in from port 106 are tested to ensure that they do not cause deadlocks to occur. must be The space for one inbound packet is It must be kept free at all times to prevent locking. port 1 Packets coming in from 06 that would cause a deadlock are also rejected.

Is space for one more packet enough to prevent deadlock? However, in the preferred embodiment, space for three additional packets is provided for efficiency. are preparing. If there is only space for three additional packets, write them directly. The storage access controller 108 does not add any more packets to the buffer. do not have. In this case, the direct memory access hund c7-2 is just an inbound It just removes the packet from its buffer.

If one inbound packet on one boat 106 is is directed to a data processor connected to a One other packet sent to the data module of the direct storage access controller 108 If the inbound packet is already queued for transmission to the processor, The port is rejected by port 106. The intercommunication processor packet is Acceptance of the packet is sent to a data processor connected to the communications processor. leaves space in buffer 102 for one inbound packet As long as it is, Uke will be accepted. This usage is used when a communication network is locally overloaded. When loaded, lower the priority of the packet “manufacturer” and lower the priority of the packet “ This has the effect of raising the priority of consumers.

Packets are queued in buffer 102 for transmission to an adjacent communications processor. At some point, port controller 104 stores those packets in buffer 102. attempts to reduce that number by sending ports to their destination port 106. continue. This means that each packet's destination boat 106 is a list of available boats. This is done by comparing the As explained above, if the desired port 106 When busy, the count for that packet is incremented. This count If a request exceeds a predetermined value, the port 106 assigned to the packet will be If possible, the port is changed to another alternative boat 106.

Reducing the number of packets in the queue reduces the number of new packets into buffer 102. Prioritize memory. Therefore, port controller 104 also to port 106, which is ready to transmit the packet to an adjacent communication processor. Give priority. Direct storage access controller 108 determines whether it is a buffer or not. is transmitting packets to a data processor connected to the communication processor. When you have the highest priority.

There are two possible overload situations here.

First, the total load on the communication processor is relatively small, but the If some of the ports 106 have incoming packets that should all be retransmitted from one port, Let's think about the case where In this case, the total load on the communication processor Wait for many packets to be delivered through a single port 106, at least a few. (only one port 106 is heavily used). This communication processor There are many free ports 106 linking the communication processor with other neighboring communication processors. In this case, it is advantageous to route the packet through the alternate port 106. be. The algorithm described above automatically performs this route change. Because Pa The port is examined by port controller 104 and it is Each time it finds that port 106 is busy and cannot deliver, a counter is set. This is because it is incremented. When that count exceeds a predetermined value, if possible , the packet is rerouted and the workload is transferred to the less used port 1. Move to 06.

Next, consider a case where there is congestion with many adjacent communication processors. buffer 102 quickly fills up with packets destined for all six ports 106. Irritation Packets that can be rerouted to the heavily underused port 106 are routed that way. The root is changed. This also results in more equal packets in less loaded conditions. This will result in load distribution. However, this is due to the fact that packet transmission It also adds to the lag. Finally, as mentioned above regarding deadlock prevention, The generation of new packets at congested areas is reduced to relieve the congestion. Ru.

Those skilled in the art will appreciate that various modifications can be made without departing from the scope of the claims of the present invention. should be obvious.

2g FIGURE 1 FIGURE 3(e) FIGtJRE　3Tol \vinegar FIGURE H5 FIGURE 11 international search report Inpupil+II+lselfanmlAapli+++:onNo, PCT105861 02039

Claims (12)

[Claims] 1. A data processing system including a plurality of data processors, each of said data processors data processor sends to other data processors in the data processing system. said data processing means including memory means for storing messages received therefrom; In a data processing system, any two data processors in the data processing system The communication network for sending messages between servers is a hexagonal array communication protocol. an E-communications processor on each side of the hexagonal array; a hexagonal array in which the processors are operatively connected to one said data processor; each communication processor is connected to the communication processor; means for exchanging messages with an integrated data processor; sending a message to a communication processor adjacent to said communication processor in the includes port means for receiving messages therefrom, the port means 6 each port in said port means is connected to said communications processor. communication processors adjacent to one communication processor at a different corresponding port. be connected for purposes of use; A communication network consisting of 2. In the communication network according to claim 1, there is further provided one adjacent communication network. Each edge of the hexagonal array that is not coupled to a corresponding port of a communication processor connect the ports of the communications processor to the communications processor on the opposite edge of the hexagonal array; includes a signal path means for coupling to a corresponding port on the processor, thereby messages from any communications processor in said hexagonal array to said hexagonal array. Any E-2 communications processor in the hexagonal array without passing through more than any other E-2 communications processor. A communications network that allows communications to be sent to other communications processors. 3. The communication network according to claim 2, wherein each of the signal path hands The stage further includes a switch operatively connected to the at least one edge port. switch means for connecting said edge port to said hexagonal array; a communications network, including means for selectively coupling to a data processor external to the . 4. The communication network according to claim 1, wherein each said port further comprises: To, Whether the corresponding port to which it is to be bound can receive messages a means for determining whether a message sent to said corresponding port was transmitted correctly; means of deciding whether means for repeating the message if the message is not transmitted correctly; a means of notifying said corresponding port that said port can receive messages; Step, Whether the message received by the port from the corresponding port was transmitted correctly. and means for determining the last message sent by the corresponding port. means for repeating A communication network that includes 5. The communication network according to claim 1, wherein the communication processor comprises: ,moreover, a puffer means for storing messages, each message stored in the puffer means; means for specifying a destination port for the message, the destination port being a means for specifying a destination port for the message; If the communication processor is an operatively connected data processor or is the port through which said message passes; said memory means and said buffer means operatively connected to said communications processor; direct storage access control means for transferring messages between and The destination port specifying means specifies the message stored in the buffer means. binds to said port, and sends messages received by one of said ports to said buffer. a communication network consisting of control means for storing information in a communication means; 6. In the communication network according to claim 5, the buffer means is It includes several storage slots, and the message can be stored in one storage slot. contains a message that is too long, and the direct storage access control means ,moreover, Split long messages into multiple storage slots, each of which size corresponds to means for creating short messages such that each said short message is stored in a computer; is the original long message from which this was created, and the long message created from the long message. containing information specifying the relationship with other short messages that have been sent; and The short messages generated by splitting the long messages are recombined to generate the long messages. means for reconstructing the message, A communication network comprising: 7. The communication network according to claim 5, wherein the control means is further configured such that the destination port stored in said buffer means is a port means for sequentially examining each message; said communication process coupled to said port; means for checking whether the server can receive the message, the port If said communications processor coupled to is capable of receiving said message, means for coupling said message from said buffer means to said port; said port; because the communication processor coupled to was unable to receive the message. means for counting the number of times the message could not be sent; If it is indicated that the transmission cannot be sent more than a certain number of times, the a means for causing another destination port to be specified for the message; and communication network. 8. A data processing system having a plurality of data processors, each of said data processors The data processor sends or transmits information to other data processors in the data processing system. contains memory means for storing messages received therefrom; The memory means includes one communication processor included in a hexagonal array of communication processors. the data processing system operatively connected to a communications processor; teeth, means for exchanging messages with a data processor coupled to the communications processor; as well as sending a message to a communication processor adjacent to said communication processor in said hexagonal array; A port means for sending or receiving messages from a port, the means for sending or receiving messages from the port. The port means includes six individual ports, each said port in said port means being connected to said port means. A different one of the plurality of communication processors adjacent to the communication processor operatively connected to a corresponding port of a communication processor. stem. 9. 9. The communication processor according to claim 8, wherein the port further comprises: the corresponding port to which the port is bound can receive messages; means for determining whether a message sent to said corresponding port is transmitted correctly; a means of determining whether means for repeating the message if the message is not transmitted correctly; a means of notifying said corresponding port that said port can receive messages; Step, Whether the message received by the port from the corresponding port was transmitted correctly. and means for determining the last message sent by the corresponding port. means for repeating a communications processor containing a 10. The communication processor according to claim 9, further comprising: buffer means for storing messages; each message stored in the buffer means; means for specifying a destination port for the message, the destination port being a means for specifying a destination port for the message; If the communication processor is an operatively connected data processor or is the port through which said message passes; said memory means and said buffer means operatively connected to said communications processor; direct storage access control means for transferring messages between and The destination port specifying means specifies the message stored in the buffer means. binds to said port, and sends messages received by one of said ports to said buffer. control means for storing information in a communication processor. 11. The communication processor according to claim 10, wherein the buffer means including a plurality of storage slots, and the message is stored in one storage slot. contains a message that is too long and also does not comply with the direct storage access control procedure. The steps are further Split long messages into multiple storage slots, each of which size corresponds to means for creating short messages such that each said short message is stored in a computer; is the original long message from which this was created, and the long message created from the long message. containing information specifying the relationship with other short messages that have been sent; and The short messages generated by splitting the long messages are recombined to generate the long messages. means for reconstructing the message, A communications processor comprising: 12. The communication processor according to claim 10, wherein the control hand The step further comprises determining whether the destination port stored in the buffer means is a port. means for sequentially examining each message sent to said communication process coupled to said port; means for checking whether the porter can receive the message; if said communication processor coupled to said client is capable of receiving said message; means for coupling said message from said buffer means to said port; because the communication processor coupled to the client was unable to receive the message. means for counting the number of times the message could not be sent to If it is indicated that it cannot be sent more than a predetermined number of times, the and means for specifying another destination port for the message. communication processor.