CN116545470A - Decoding method of S response signal decoder based on PDW and FPGA implementation device - Google Patents
Decoding method of S response signal decoder based on PDW and FPGA implementation device Download PDFInfo
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Abstract
The invention discloses a decoding method of an S response signal decoder based on PDW and an FPGA implementation device, wherein the method comprises the following steps: pulse width filtering processing is carried out on the input PDW signals, and PDW signals with pulse widths outside the S response signals are filtered; judging the input PDW leading pulse according to the pulse width, the time interval and the amplitude, and judging whether the group of pulses are the S response mode marks or not; the code value of the S response mode is calculated by an information pulse decoding algorithm based on the PDW to form RDW output; outputting the result to an information identification module, wherein the information identification module obtains flight parameters of the aircraft, such as longitude and latitude and altitude, according to the code value information contained in the RDW output by the decoding module. The FPGA decoding based on PDW adopted by the invention can effectively improve the decoding accuracy and instantaneity, and can also improve the efficiency of analysis of the reason of signal interference and design of anti-interference strategies.
Description
Technical Field
The invention relates to the technical field of response signal processing in air traffic control, in particular to a decoding method of an S response signal decoder based on PDW and an FPGA implementation device.
Background
The S-mode response signal carries a large number of key parameters such as target states, and has wide application in a plurality of fields, for example, in civil aviation, the S-mode response signal carries a large number of unique flight numbers, altitude, longitude and latitude information of a passenger plane, and information such as special codes of emergency calls.
The S mode response signal works at 1090MHz frequency point, and a large amount of signals are interwoven on the working frequency point, so that the signal environment is complex. The current method for decoding the S response signal comprises the following steps: according to parameters such as signal arrival time and power reference value obtained by the leading pulse P1, data block decoding is carried out, 0 and 1 of data bits and confidence coefficient values are judged, and data bit extraction and confidence coefficient analysis algorithms are mainly concentrated in time domain processing, namely the data bit values and the confidence coefficient values are obtained through analysis of waveform sampling points. The amplitude comparison method is a conventional algorithm that determines the data value and confidence by comparing the amplitude of two CHIPs at the data location. The data bits can be received and processed by a multi-point sampling decision method, the information of N sampling values of each data bit and the reference power value obtained in the detection of the preamble pulse are fully utilized, the data value and the confidence value are determined through the relation between the information of the N sampling values of each data bit and the reference power value, and the decoding is completed and error correction can be performed through check bits. In a real environment, the pulse signal amplitude and the pulse position estimation of the intermediate frequency signal have obvious deviation due to the influence of noise and interference signals, and the data value and the confidence coefficient are judged by comparing the amplitude values of two CHIP at the data position, so that decoding errors are easy to cause, false alarms and missed alarms are generated, and the detection probability of a target is reduced.
The pulse detection and parameter measurement of the current electronic receiving system reach higher level, and the algorithms such as data fusion, PDW preprocessing and the like are adopted, so that pulse signals can be accurately detected and corresponding PDW information can be given.
Disclosure of Invention
In view of this, in order to reduce decoding errors caused by finishing information pulse decoding by using intermediate frequency signals, the invention provides a decoding method of an S response signal decoder based on PDW and an FPGA implementation device.
In order to achieve the above purpose, the present invention adopts the following technical scheme: according to a first aspect of the present invention, there is provided a PDW based decoding method for an S-acknowledgement signal decoder, the decoding method comprising the steps of:
pulse width filtering processing is carried out on the input PDW signals, and PDW signals with pulse widths outside the S response signals are filtered;
judging the input PDW leading pulse according to the pulse width, the time interval and the amplitude, and judging whether the group of pulses are the S response mode marks or not;
and when the condition is met, the code value of the S response mode is calculated by an information pulse decoding algorithm based on the PDW by the pulse, and RDW output is formed.
Preferably, the method further comprises: when the conditions are met, decoding the output RDW to obtain code value information of flight parameters including flight numbers, longitude and latitude and altitude of the airplane in the RDW;
when the condition is not satisfied, the reception determination jumps out.
Preferably, the pulse width filtering processing of the input PDW signal includes: primary pulse width filtering treatment and secondary pulse width filtering treatment; wherein, the liquid crystal display device comprises a liquid crystal display device,
the primary pulse width processing includes: filtering and removing PDW irrelevant to the S response signal, and only keeping PDW and flag mark signals with pulse widths within the range of 0.5us plus or minus 0.15us and 1us plus or minus 0.15 us;
the secondary pulse filtering process comprises the following steps: only the PDW and flag signals with pulse widths in the range of 0.5us + -0.15 us are retained.
Preferably, the determining the input PDW preamble pulse according to the pulse width, the time interval, and the amplitude, and determining whether the set of pulses is the S answer mode identifier includes:
when the blank time of the P1 leading pulse meets a set value, starting S response mode leading pulse relation judgment, and taking out the amplitude of the P1 as the reference amplitude of the leading pulse and the information pulse amplitude;
the current leading pulse time relation, the leading pulse width and the amplitude except for P1 are all in the jitter range, no redundant pulse exists between P4 and the first information pulse, the signal S response mode is judged, the information pulse decoding is continuously executed, and the receiving judgment of no is jumped out.
Preferably, when the P1 preamble pulse blank time satisfies the set value includes: when the pulse-free blank time before P1 is more than or equal to 10us;
the P1 preamble pulse time relationship satisfies: the first leading pulse P1 of the S-response is spaced 1 μs, 3.5 μs and 4.5 μs from the three following leading pulses P2, P3, P4, respectively, and each leading pulse has a width of 0.5 μs;
when the pulse width and amplitude of the P1 front pulse and the front pulse except for P1 are within the jitter range, the following needs to be satisfied: the width of the leading pulse is 0.5 mu s, and the amplitude variation of any two pulses should not exceed 2dB;
no extra pulse between P4 and the first information pulse needs to be satisfied: there is no pulse within 3.5 us.+ -. 0.15us after P4.
Preferably, the decoding algorithm of the information pulse based on PDW calculates a code value of the S response mode includes:
taking out the pulse width, amplitude and effective mark of the PDW to be combined into Pdwout;
the code value judgment of each 1 mu s information pulse is completed by using PDW parameters of 3 pulses of Pdwout (n), pdwout (n-1) and Pdwout (n+1);
reconstructing the PDW with the 1us pulse width into two PDWs with 0.5us pulse widths when the pulse width in the Pdwout (n) parameter is in the range of 1us plus or minus 0.15us, wherein the PDW of the first 0.5us pulse of the 1us information pulse is defined as Pdwout (n-1) ', and Pdwout (n-1)' =pdwout (n);
comparing the PDW amplitude of the first 0.5us pulse Pdwout (n-1)' of the current 1 mus period with the PDW amplitude of the previous 0.5us pulse Pdwout (n-1) detected by the actual PDW; comparing the PDW amplitude of the last 0.5 μs pulse Pdwout (n+1) detected in practice with the last 0.5 μs pulse of the current 1 μs period; and rechecking the amplitude of the front and rear groups of 1us information pulses and the reference amplitude to obtain the code values of the front and rear groups of 1us information pulses.
Preferably, after the code values of the two sets of 1 μs information pulses are obtained, the method further includes:
the decoding result is corrected by the check bit, and the S response decoding in 56 mu S and 112 mu S formats is processed according to the maximum information pulse duration of 112 mu S and then the RDW is output.
According to a second aspect of the present invention, there is provided a decoding method of an S-response signal decoder based on PDW and an FPGA implementation apparatus, including: a PDW pulse width filtering module, a leading pulse judging module and an information pulse decoding module, wherein,
the PDW pulse width filtering module filters PDW which does not meet the pulse width requirement of the S response mode signal;
the preamble pulse judging module judges the pulse width, the time interval and the amplitude of the PDW of the preamble pulse according to the format of the S response signal, and completes the judgment of whether the group of pulses are in the S response mode;
and the information pulse decoding module is used for finishing decoding of the information pulse by utilizing the information carried by the PDW according to the S response mode signal format and outputting the RDW.
Preferably, the system further comprises a signal receiving module, a parameter measuring module and a decoding module, wherein,
the signal receiving module is used for completing the function of filtering the receiving bandwidth of the AD input digital complex signal and the receiving bandwidth of the digital simultaneous multi-beam or single-channel signal;
the parameter measurement module is used for completing information extraction of the pulse signals and forming PDW;
and the decoding module is used for calculating the signal code value of the S response mode according to the signal format of the S response mode and a PDW decoding algorithm to form RDW output.
Preferably, the method further comprises: and the information identification module is used for receiving the RDW and obtaining flight parameters of the flight number, longitude and latitude and altitude of the airplane according to the code value information contained in the RDW output by the decoding module.
Compared with the prior art, the invention has the following technical effects:
the decoding method of the S response signal decoder based on the PDW and the FPGA implementation device provided by the invention adopt a data fusion and PDW preprocessing algorithm, so that pulse signals can be accurately detected and corresponding PDW information can be given.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below.
Fig. 1 is a schematic diagram of decoding of an S response signal FPGA based on PDW according to an embodiment of the present invention;
fig. 2 is a block diagram of an S response signal provided by an embodiment of the present invention;
FIG. 3 is a block diagram of an information pulse provided by an embodiment of the present invention;
FIG. 4 is a flowchart of a PDW-based preamble pulse determination according to an embodiment of the present invention;
FIG. 5 is a flowchart of decoding a PDW-based information pulse according to an embodiment of the present invention;
fig. 6 is a block diagram of an FPGA implementation device provided in an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Note that FPGA (Field Programmable Gate Array) is shown as a field programmable gate array, which is an integrated circuit with programmable characteristics that is designed and implemented in advance on a silicon wafer, and can be configured to a specified circuit configuration according to the needs of a designer, so that a customer does not have to rely on ASIC chips designed and manufactured by a chip manufacturer.
In the prior art, the currently commonly adopted information pulse decoding algorithm, namely the method for judging the data value and the confidence coefficient by comparing the amplitudes of two CHIP of the data position, cannot be realized by a confidence coefficient calculation method when the FPGA is realized, such as the PowerPC and a server, particularly when the FPGA is realized, the method is simultaneously in a multi-beam system, the medium frequency data quantity required to be transmitted is too large, the real-time effective transmission of the data cannot be realized, and the blockage of a transmission channel and the halt of processing software are easily caused. And the S response signal code value is obtained by judging the information pulse data value in the FPGA, the decoding signal accuracy is reduced due to the interweaving signal caused by the external complex electromagnetic environment, and the flight path of the aircraft is discontinuous.
In a real environment, due to the influence of noise, interference signals and the like, the amplitude and the pulse position of a pulse signal of an intermediate frequency signal used for information pulse decoding have obvious deviation, decoding errors are easy to cause, false alarms and false omission are generated, targets are discontinuous, and the detection probability of the targets is reduced.
The pulse detection and parameter measurement of the current electronic receiving system reach a higher level, in order to solve the problems in the prior art, the embodiment of the invention provides a decoding method of an S response signal decoder based on PDW, and fig. 1 is a decoding schematic diagram of an S response signal FPGA based on PDW. Specifically as shown in fig. 1, the decoding method of the S response signal FPGA based on PDW of the present invention includes the following steps:
pulse width filtering processing is carried out on the input PDW signals, and PDW signals with pulse widths outside the S response signals are filtered;
judging the input PDW leading pulse according to the pulse width, the time interval and the amplitude, and judging whether the group of pulses are the S response mode marks or not;
when the conditions are met, the code value of the S response mode is calculated based on the PDW information pulse decoding algorithm, RDW output is formed, information decoding is carried out on the output RDW, and code value information of flight parameters including flight numbers, longitude and latitude and altitude of the aircraft in the RDW is obtained;
when the condition is not satisfied, the reception determination jumps out.
The pulse width filtering processing of the input PDW signal includes a primary pulse width filtering and a secondary pulse width filtering, wherein the primary pulse width filtering uses a pulse width judgment criterion to reject PDW irrelevant to the S response signal, and only retains PDW and flag signals with pulse widths within the range of 0.5us +/-0.15 us and 1us +/-0.15 us. In this process, two adjacent 0.5 μs information pulses are combined for 1 pulse, and the second pulse filtering only retains the PDW and flag signals with pulse widths in the range of 0.5us + -0.15 us.
The S-mode response signal includes an S-mode 56bit response, an S-mode 112bit response (including ADS-B), and the like, and has the same basic frame format. The pulse width of the S mode response signal is 0.5us plus or minus 0.15us. See fig. 2 for a specific format. The S-mode reply signal consists of four preamble pulses, i.e., P1, P2, P3, P4, and 56-bit or 112-bit reply data blocks. The position of each data bit is a pulse with or without pulse interval with the width of 1us, the response data adopts a binary pulse position modulation mode, the pulse represents 1 when appearing in the first half section, the pulse represents 0 when appearing in the second half section, and each half section is 0.5 mu s; the first leading pulse of the mode S response is separated from the following three leading pulses by 1 μs, 3.5 μs, and 4.5 μs, respectively, each leading pulse having a width of 0.5 μs; the amplitude of any two pulses in the mode S response should not vary by more than 2dB. The specific meaning represented by the code value can be obtained by interpretation of the decoding result.
Specifically, the determining of the input PDW preamble pulse by pulse width, time interval, amplitude determines whether the mode of the set of signals is S-reply mode by determining the preamble pulse. Fig. 2 is a block diagram of S response signal information, which is a basic basis for decoding. The first leading pulse of the mode S response is theoretically separated from the following three leading pulses by 1 μs, 3.5 μs and 4.5 μs, respectively, each leading pulse having a width of 0.5 μs; the amplitude of any two pulses in the mode S response should not vary by more than 2dB. When the above condition is satisfied, it is determined whether or not the mode is the S response mode.
Fig. 3 is a block diagram of an information pulse, according to which the signal recognition can obtain the meaning represented by the different code values by interpretation of the RDW, as shown in fig. 3. The position of each information pulse is a pulse-with-pulse and pulse-free interval with the width of 1 mu s, response data adopts a binary pulse position modulation mode, the pulse represents 1 when appearing in the first half section, the pulse represents 0 when appearing in the second half section, and each half section is 0.5 mu s. Two adjacent 0.5 mu s information pulses are combined into 1 mu s pulse, so the above one pulse width filtering needs to first screen PDW and flag mark signals with pulse widths in the range of 0.5us plus or minus 0.15us and 1us plus or minus 0.15us.
Further, the determining of the PDW-based preamble pulse according to the satisfaction conditions of fig. 2 and 3 is specifically shown in fig. 4, where determining whether the set of pulses is the S-answer mode identifier includes: judging the relation between the P1 leading pulse blank time and the leading pulse: when the blank time of the P1 leading pulse meets a set value, starting S response mode leading pulse relation judgment; taking the amplitude of the P1 leading pulse as the reference amplitude of the leading pulse and the information pulse amplitude;
when the P1 preamble pulse time relationship and the preamble pulse width and amplitude other than P1 are both within the jitter range,
and no unnecessary pulse exists between the P4 and the first information pulse, and the group of signals is judged to be in the S response mode.
Specifically, since the leading pulse does not exist and the two pulses of 0.5 mu s before and after the leading pulse are detected as 1 wide pulse, the PDW and flag mark signals with the pulse width being out of the range of 0.5 mu s plus or minus 0.15 mu s should be filtered out first.
The step of starting S response mode leading pulse relation judgment when the P1 leading pulse blank time meets a set value comprises the step of starting S response mode leading pulse relation judgment when the P1 leading pulse blank time meets the preset value and the pulse-free blank time is more than or equal to 10 us. Wherein, the judging of the S response mode leading pulse relation comprises the following steps: and judging the relation between the pulse blank time and the leading pulse before P1.
The judging of the pulse-free blank time before P1 specifically comprises the following steps: no pulse blank time before screening P1, i.e. no threshold information is detected at least 10us or more before determining the leading pulse P1. The S response mode theory comprises 4 leading pulses, namely P1, P2, P3 and P4 in sequence, the real electromagnetic environment influence is considered, the judgment of the leading pulses considers that one pulse (P2 or P3) is not detected or one pulse is detected out of the 4 leading pulses (one pulse is inserted between the P2 and the P3), and the judgment of the leading pulse time difference and the amplitude difference (+ -3 dB) taking the P4 as a reference is used for determining whether the signal mode is the S response mode or not, so that the false alarm and the false alarm caused by decoding errors can be effectively reduced.
The preamble pulse relation judgment includes: and judging the relation of the time of the leading pulse, the pulse width and the amplitude of the leading pulse.
In this embodiment, the amplitude of the P1 preamble pulse is used as the reference amplitude of the preamble pulse and the information pulse amplitude, and when the P1 preamble pulse time relationship needs to be satisfied: the first preamble pulse P1 is separated from the following three preamble pulses P2, P3, P4 by 1 μs, 3.5 μs and 4.5 μs, respectively.
The leading pulse width and amplitude determination includes: when the amplitude of the P1 front pulse and the amplitude of the front pulses except for P1 are both in the jitter range, the amplitude deviation value range needs to be satisfied, that is, the pulse width and the amplitude of the front pulses except for P1 are both in the jitter range. I.e. within the allowable pulse width and amplitude deviation values, specifically the leading pulse width is 0.5 mus, the amplitude of any two pulses should not vary by more than 2dB.
No extra pulse between said P4 and the first information pulse comprises: and judging the pulse-free time after P4 and judging the alignment of the amplitude information delay of the S response signal after P4 and the first information pulse position, namely, judging that no pulse exists in 3.5us plus or minus 0.15us after P4.
The judgment of the pulse-free time after P4 is to firstly meet the requirement that no redundant pulse exists between P4 and the first information pulse, namely, no pulse exists in 3.5us plus or minus 0.15us after P4;
secondly, consider that there are three cases where two 0.5us information pulses before and after are detected as 1us pulse in fusion, and the first information pulse occurs at three positions: a first 0.5us initiated single pulse, a second 0.5us initiated single pulse, and a second 0.5us initiated fusion broad pulse. The current leading pulse time relation is within the allowable range of pulse width and amplitude deviation value, no pulse is before P4 and no redundant pulse exists between the first information pulse P1, the group of signals is judged to be the signal S response mode, the information pulse decoding module is continuously executed, and the receiving judgment of no is jumped out. The information pulse decoding module is a core module for decoding the S response mode signal.
Fig. 5 is a flow chart of decoding information pulses based on PDW. In the S reply signal format framework, the information pulse will occur in either one of the 0.5 mus periods of 1 mus. When the current 1 mu S information pulse appears in the 2 nd 0.5 mu S time period and the later 1 mu S information pulse appears in the 1 st 0.5 mu S time period, the situation that the front and the back two 0.5us information pulses are combined and detected to output 1 PDW as 1 mu wide pulse can occur, the PDW information of the first 1 0.5 mu S pulse needs to be supplemented, and each 0.5 mu S information pulse is ensured to have a corresponding PDW for judging the code value of the S response signal.
Based on the above, the decoding algorithm of the information pulse based on the PDW calculates the code value of the S response mode, including the following steps:
1. taking out pulse width (pw), amplitude (amp) and flag (PDW effective mark) of the PDW to be combined into Pdwout;
when the PDW bit width is 512bit and the multi-beam of the DBF system is processed simultaneously, more internal memory resources of the FPGA are occupied for delaying 512bit signals, so key parameters required for judging the selected code value are recombined into Pdwout for delaying processing, and the aim of reducing the internal memory resources of the FPGA is fulfilled by reducing the bit width of the delaying processing;
pdwout is a self-defined abbreviation for representing a set of PDW output parameters, PDW represents PDW, and out represents a signal parameter value extracted from the original PDW as needed, and includes pulse width, amplitude, and valid flag.
2. The code value judgment of each 1 mu s information pulse is completed by using PDW parameters (without PDW and flag value being 0) of 3 0.5 mu s pulses, namely Pdwout (n), pdwout (n-1) and Pdwout (n+1); when the pulse width in the Pdwout (n) parameter is in the range of 1 μs±0.15 μs, it means that the adjacent two 0.5 μs pulse combination detection can reconstruct into two PDWs with 0.5 μs pulse width by the PDW with 1us pulse width for 1 PDW, the PDW of the first 0.5us pulse of the 1us information pulse is defined as Pdwout (n-1) ', and Pdwout (n-1)' =pdwout (n), that is, within the 1us pulse, the front and back 0.5us share the PDW information of the current 1us information pulse;
3. comparing the PDW amplitude of the first 0.5us pulse Pdwout (n-1)' of the current 1 mus period with the PDW amplitude of the previous 0.5us pulse Pdwout (n-1) detected by the actual PDW; comparing the PDW amplitude of the last 0.5 μs pulse Pdwout (n+1) detected in practice with the last 0.5 μs pulse of the current 1 μs period; finally, the amplitude of the front and back groups of 1us information pulses and the reference amplitude (the amplitude of P1) are rechecked; the code values of the two sets of 1 mus information pulses can be obtained.
In the decoding process, the decoding result can be corrected by check bits; afterwards, S-reply decoding in 56 μs and 112 μs formats outputs RDW after 112 μs. In order to ensure the uniformity of decoding and the convenience of subsequent processing, the decoding processing of the S response is processed according to the maximum information pulse duration of 112 mu S.
And finally, decoding the information of the output RDW to obtain code value information of flight parameters including the flight number, longitude and latitude and altitude of the airplane in the RDW.
In summary, the main technical indexes of the method of the invention relate to pulse detection and reference measurement results. When the S response signal decoding based on the PDW is adopted, the amplitude information contained in the PDW detected by each 0.5 mu S information pulse is the result of the intermediate frequency signal amplitude multipoint smoothing, so that the detection probability in the process of judging the front and rear 0.5 mu S positions can be remarkably improved. The technical problem of decoding errors caused by obvious deviation of the amplitude of the intermediate frequency signal due to the influence of noise and interference signals is solved. Furthermore, the FPGA decoding based on PDW adopted by the invention can effectively improve the decoding accuracy and instantaneity, and also can improve the efficiency of signal interference cause analysis and anti-interference strategy design.
In addition, the embodiment of the invention also provides an FPGA implementation device of the S response signal decoder based on PDW, specifically as shown in figure 6, the S response signal FPGA decoding based on PDW comprises a PDW pulse width filter module, a preamble pulse judging module and an information pulse decoding module, wherein,
the PDW pulse width filtering module is used for filtering PDW which does not meet the pulse width requirement of the S response mode signal; in this embodiment, the pulse width filtering processing of the input PDW signal is implemented by the PDW pulse width filtering module.
The preamble pulse judging module is used for judging the pulse width, the time interval and the amplitude of the PDW of the preamble pulse according to the S response mode signal format to finish judging whether the group of pulses are in the S response mode; in this embodiment, the input PDW preamble pulse is determined by the preamble pulse determination module by pulse width, time interval, and amplitude to determine whether the mode of the set of signals is S-reply mode.
And the information pulse decoding module is used for finishing decoding of the information pulse by utilizing the information carried by the PDW according to the S response mode signal format and outputting an RPDW signal. In this embodiment, the input of the information pulse decoding module is the output of the PDW pulse width filtering module, and the leading pulse output by the leading pulse judging module judges the correct flag.
In addition, the decoding process of the S response signal based on the PDW further includes:
the signal receiving module is used for completing the function of filtering the receiving bandwidth of the AD input digital complex signal and the receiving bandwidth of the digital simultaneous multi-beam or single-channel signal;
the decoding module is used for calculating the signal code value of the S response mode according to the signal format of the S response mode and a PDW decoding algorithm to form RDW output; specifically, the decoding module comprises the three core modules of the PDW pulse width filtering module, the preamble pulse judging module and the information pulse decoding module.
The parameter measurement module is used for completing information extraction of the pulse signals and forming PDW;
and the information identification module is used for receiving the RDW and obtaining flight parameters of the flight number, longitude and latitude and altitude of the airplane according to the code value information contained in the RDW output by the decoding module.
While the invention has been described above by way of specific embodiments, many modifications and variations of the invention are possible without departing from the spirit of the invention, and the appended claims are intended to encompass such modifications and variations. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (10)
1. A PDW-based decoding method for an S-response signal decoder, comprising the steps of:
pulse width filtering processing is carried out on the input PDW signals, and PDW signals with pulse widths outside the S response signals are filtered;
judging the input PDW leading pulse according to the pulse width, the time interval and the amplitude, and judging whether the group of pulses are the S response mode marks or not;
and when the condition is met, the code value of the S response mode is calculated by an information pulse decoding algorithm based on the PDW by the pulse, and RDW output is formed.
2. The PDW based S-reply signal decoder decoding method of claim 1, further comprising:
when the conditions are met, information decoding is carried out on the output RDW, and code value information of flight parameters including flight numbers, longitude and latitude and altitude of the airplane is obtained from the RDW;
when the condition is not satisfied, the reception determination jumps out.
3. The method of decoding a PDW based S-reply signal decoder of claim 1, wherein said pulse width filtering the input PDW signal comprises: primary pulse width filtering treatment and secondary pulse width filtering treatment; wherein, the liquid crystal display device comprises a liquid crystal display device,
the primary pulse width processing includes: filtering and removing PDW irrelevant to the S response signal, and only keeping PDW and flag mark signals with pulse widths within the range of 0.5us plus or minus 0.15us and 1us plus or minus 0.15 us;
the secondary pulse processing includes: the filtering only retains the PDW and flag signals with pulse widths in the range of 0.5us + -0.15 us.
4. The method of decoding a PDW-based S-reply signal decoder of claim 1 wherein said determining the input PDW preamble pulse in terms of pulse width, time interval, amplitude, determining whether the set of pulses is an S-reply mode identification includes:
judging the relation between the blank time of the P1 leading pulse and the leading pulse;
when the blank time of the P1 leading pulse meets a set value, starting S response mode leading pulse relation judgment; taking the amplitude of the P1 leading pulse as the reference amplitude of the leading pulse and the information pulse amplitude; when the P1 leading pulse time relation and the leading pulse width and amplitude except P1 are in the jitter range and no redundant pulse exists between P4 and the first information pulse, the group of signals are judged to be in the S response mode.
5. The method for decoding a PDW based S-reply signal decoder of claim 4,
the step of when the P1 preamble pulse blank time satisfies the set value includes: when the pulse-free blank time before P1 is more than or equal to 10us ；
The P1 preamble pulse time relationship satisfies: the first leading pulse P1 of the S-response is spaced 1 μs, 3.5 μs and 4.5 μs from the three following leading pulses P2, P3, P4, respectively, and each leading pulse has a width of 0.5 μs;
when the pulse width and amplitude of the P1 front pulse and the front pulse except for P1 are within the jitter range, the following needs to be satisfied: the width of the leading pulse is 0.5 mu s, and the amplitude variation of any two pulses should not exceed 2dB;
no extra pulse between P4 and the first information pulse needs to be satisfied: there is no pulse within 3.5 us.+ -. 0.15us after P4.
6. The decoding method of the PDW-based S-response signal decoder according to claim 1, wherein the decoding algorithm of the PDW-based information pulse decoding algorithm calculates the code value of the S-response mode, including:
taking out the pulse width, amplitude and effective mark of the PDW to be combined into Pdwout;
the code value judgment of each 1 mu s information pulse is completed by using PDW parameters of 3 pulses of Pdwout (n), pdwout (n-1) and Pdwout (n+1); reconstructing the PDW with the 1us pulse width into two PDWs with 0.5us pulse widths when the pulse width in the Pdwout (n) parameter is in the range of 1us plus or minus 0.15us, wherein the PDW of the first 0.5us pulse of the 1us information pulse is defined as Pdwout (n-1) ', and Pdwout (n-1)' =pdwout (n);
comparing the PDW amplitude of the first 0.5us pulse Pdwout (n-1)' of the current 1 mus period with the PDW amplitude of the previous 0.5us pulse Pdwout (n-1) detected by the actual PDW; comparing the PDW amplitude of the last 0.5 μs pulse Pdwout (n+1) detected in practice with the last 0.5 μs pulse of the current 1 μs period; and rechecking the amplitude of the front and rear groups of 1us information pulses and the reference amplitude to obtain the code values of the front and rear groups of 1us information pulses.
7. The decoding method of the PDW-based S-reply signal decoder of claim 6, wherein after the code values of the two sets of 1 μs information pulses are obtained, further comprising:
the decoding result is corrected by the check bit, and the S response decoding in 56 mu S and 112 mu S formats is processed according to the maximum information pulse duration of 112 mu S and then the RDW is output.
8. An FPGA implementation device for decoding an S response signal decoder based on PDW, comprising: a PDW pulse width filtering module, a leading pulse judging module and an information pulse decoding module, wherein,
the PDW pulse width filtering module filters PDW which does not meet the pulse width requirement of the S response mode signal;
the preamble pulse judging module judges the pulse width, the time interval and the amplitude of the PDW of the preamble pulse according to the format of the S response signal, and completes the judgment of whether the group of pulses are in the S response mode;
and the information pulse decoding module is used for finishing decoding of the information pulse by utilizing the information carried by the PDW according to the S response mode signal format and outputting the RDW.
9. The FPGA implementation apparatus decoded by the PDW based S-reply signal decoder of claim 8, further comprising:
the signal receiving module is used for completing the function of filtering the receiving bandwidth of the AD input digital complex signal and the receiving bandwidth of the digital simultaneous multi-beam or single-channel signal;
the decoding module is used for calculating the signal code value of the S response mode according to the signal format of the S response mode and a PDW decoding algorithm to form RDW output;
and the parameter measurement module is used for completing information extraction of the pulse signals and forming PDW.
10. The FPGA implementation apparatus decoded by the PDW based S-reply signal decoder of claim 9, further comprising:
and the information identification module is used for receiving the RDW and obtaining flight parameters of the flight number, longitude and latitude and altitude of the airplane according to the code value information contained in the RDW output by the decoding module.
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