CN116545465A

CN116545465A - Data detection method, device and communication system

Info

Publication number: CN116545465A
Application number: CN202310527823.9A
Authority: CN
Inventors: 李�杰; 蒋知广
Original assignee: Shanghai Awinic Technology Co Ltd
Current assignee: Shanghai Awinic Technology Co Ltd
Priority date: 2023-05-10
Filing date: 2023-05-10
Publication date: 2023-08-04

Abstract

The application relates to the field of communication and discloses a data detection method, equipment and a communication system. The method comprises the steps that a first detection circuit and a second detection circuit receive a first input signal; the first detection circuit obtains a first output signal based on the first input signal; the first output signal comprises a first input signal and a first equipment bus connection mode; the first detection circuit sends a first output signal to the data processing circuit; the second detection circuit generates a blocking signal to enable the second detection circuit to be in a non-working state. The connection mode of the first detection circuit and the connection port is identical to the connection mode of the second device and the connection port, and the connection mode of the second detection circuit and the connection port is different from the connection mode of the second device and the connection port. Based on the above, a blocking signal is continuously generated in the detection circuit with abnormal bus relation, so that the error bus connection mode is prevented from being output to the subsequent circuit module, and the accurate judgment of the bus connection mode is realized.

Description

Data detection method, device and communication system

Technical Field

The present invention relates to the field of communications, and in particular, to a data detection method, device, and communications system.

Background

As the application requirements of RF Front-End devices (power amplifiers, low noise amplifiers, filters, etc.) become more and more widespread, and complex control of RF Front-End devices becomes more and more challenging, the mobile industry processor interface alliance (mobile industry processor interface, MIPI) proposes an RFFE (RF Front-End) bus interface for connecting multiple Front-End devices to other Front-End modules. 1 master device and at most 15 slave devices can be mounted on a single RFFE bus, when the master device and the slave devices communicate, each slave device obtains the bus connection mode of the slave device by detecting a signal sent by the master device and is matched with the bus connection mode corresponding to the slave device address USID in a 13bit command frame sent by the master device, if the bus connection mode of the USID in the 13bit command frame sent by the master device is the same as the bus connection mode of the slave device, the slave device receives and processes data sent by the master device, and only one slave device is required to process the data, so that the connection mode of different slave devices and the master device can be changed.

In some aspects, the slave determines the bus connection of the slave by detecting the SSC signal. However, if the connection mode of the plurality of slave devices determined based on the SSC signal is the same as the bus connection mode in the 13bit command frame, the plurality of slave devices execute the same 13bit command frame, which causes resource waste.

In order to solve the problem of resource waste in the above solutions, in some solutions, the slave device determines the bus connection mode of the slave device by detecting 13bit command frames by two detection circuits in the slave device that are different from the connection mode of the slave device. The scheme can execute the same 13bit command frame, and can solve the problem of resource waste in the scheme, but when the 13bit command frame sent by the main device is interfered in the transmission process, and the 13bit command frame is not satisfied due to data distortion, the correct detection circuits in the two detection circuits cannot acquire the bus connection mode of the slave device based on the 13bit command frame, and the error detection circuit can judge the bus connection mode of the slave device again through a certain number of pulses coming subsequently and output an error bus connection mode as the bus connection mode of the slave device, so that the accuracy of the judgment result of the bus connection mode is affected.

Disclosure of Invention

In view of this, embodiments of the present application provide a data detection method, apparatus, and communication system. By setting two detection circuits in the first device (the first device mentioned in the application may be the slave device in the embodiment of the application) to detect the 13bit command frame respectively to obtain the bus connection mode of the slave device, the detection circuit with the correct bus connection mode makes the bus relation judgment flow of the first device normally executed in the detection process, and the detection circuit with the incorrect bus connection mode can continuously generate the SSC2 signal (blocking signal) in the detection process to block the detection process of the error detection circuit. Therefore, the wrong bus connection mode is prevented from being output to a subsequent circuit module, and the first device (slave device) is prevented from performing redundant processing on data sent by the second device (master device).

In a first aspect, an embodiment of the present application provides a data detection method, where the method includes: the device comprises a first device, a second device and a data processing circuit, wherein the first device comprises a connecting port, a data detection device and a data processing circuit, the data detection device comprises a first detection circuit and a second detection circuit, the connecting mode of the first detection circuit and the first device is consistent with the connecting mode of the connecting port and the second device, and the connecting mode of the second detection circuit and the main device is different from the connecting mode of the connecting port and the second device; the first detection circuit and the second detection circuit receive a first input signal; the first detection circuit obtains a first output signal based on the first input signal; the first output signal comprises a first input signal and a bus connection mode of the slave device; the first detection circuit sends a first output signal to the data processing circuit; the second detection circuit generates a blocking signal for enabling the second detection circuit to be in a non-working state.

In the scheme, by blocking the detection process of the second detection circuit (error detection circuit), when the first detection circuit (correct detection circuit) cannot output the correct bus connection mode judgment result, the second detection circuit cannot judge again and output the error bus connection mode judgment result, and further accurate judgment of the bus connection mode is achieved.

In one possible implementation of the first aspect, the first detection circuit includes a first instruction determination unit; the first instruction judging unit acquires a first output signal based on the first input signal.

It can be understood that the instruction judging unit inside the first detection circuit with the correct bus connection mode receives the 13bit command frame and judges the bus connection mode of the slave device based on the 13bit command frame.

In one possible implementation of the first aspect, the first instruction determining unit obtains the first output signal based on the first input signal, and the first instruction determining unit outputs the first output signal when determining that the first input signal satisfies the data characteristic.

It can be understood that the instruction judging unit inside the first detection circuit with the correct bus connection mode judges the bus connection mode of the first device, and then the judging circuit inside the instruction judging unit judges that the data characteristic of the 13bit command frame is correct, and then the judging result of the 13bit command frame and the bus connection mode is output to the data processing circuit.

In a possible implementation of the first aspect, the data characteristic includes that the parity bits of the first input signal are correct, and that the command sequence of the first input signal corresponds to a preset sequence.

In one possible implementation of the first aspect, the first detection circuit further includes a first start signal detection unit, and further includes: the first start signal detection unit generates a start signal based on the high-low level change of the first input signal, the start signal controls the normal detection flow of the first detection circuit to be normally executed, and after the detection flow of the first detection circuit is ended, the first detection circuit is controlled to be restored to a default state.

It can be understood that after the first detection circuit is determined to be the detection circuit with the correct bus connection mode, the first detection circuit is started to detect after the SSC signal detection unit in the first detection circuit generates the SSC1 signal (start signal), and the first detection circuit performs normal detection and determination on the 13bit command frame, that is, the first detection circuit is in a normal working state.

In one possible implementation of the first aspect, the second detection circuit includes a second start signal detection unit; the second detection circuit generates a blocking signal comprising: the second start signal detection unit receives the first input signal and generates a blocking signal according to the high-low level change of the first input signal. The second start signal detection unit in the second detection circuit continuously generates SSC2 signal blocking detection process in the detection process, so that the second detection circuit cannot execute the complete detection process.

It can be understood that after the second detection circuit is determined to be a detection circuit with an incorrect bus connection mode, the SSC signal detection unit inside the second detection circuit continuously generates an SSC2 signal (blocking signal) to block the second detection circuit from detecting and determining the 13bit command frame, i.e. the second detection circuit cannot execute a complete detection flow.

By blocking the working process of the error detection circuit, when the first detection circuit with the correct bus connection mode cannot output the correct bus connection mode judging result, the second detection circuit with the incorrect bus connection mode cannot judge again and output the incorrect bus connection mode judging result because of a certain number of subsequent pulses, and therefore accurate judgment of the bus connection mode is achieved.

In one possible implementation of the first aspect, the second detection circuit includes a second instruction determination unit; after the data processing circuit receives the first output signal, the first instruction judging unit resets the first starting signal generating circuit; the second instruction judging unit resets the second start signal generating circuit.

It can be understood that, when the primary bus relation detection process of the first detection circuit with the correct bus connection mode is finished, the SSC signal detection unit of the first detection circuit controls the SSC signal to reset, so as to ensure that the SSC2 signal generated in the previous detection process does not affect the judgment process of the next bus connection mode.

In one possible implementation of the first aspect, the connection port includes a first clock signal terminal and a first data signal terminal, the first detection circuit includes a second clock signal terminal and a second data signal terminal, the second detection circuit includes a third clock signal terminal and a third data signal terminal, and the second device includes a fourth clock signal terminal and a fourth data signal terminal; the connection mode of the first detection circuit and the connection port is consistent with the connection mode of the second device and the connection port, the connection mode of the second detection circuit and the connection port is different from the connection mode of the second device and the connection port, and the connection mode detection circuit comprises: the first clock signal end is connected with the fourth clock signal end, and the first data signal end is connected with the fourth data signal end; the second clock signal end is connected with the fourth clock signal end, and the second data signal end is connected with the fourth data signal end; the third clock signal end is connected with the fourth data signal end, and the third data signal end is connected with the fourth clock signal end.

In a second aspect, an embodiment of the present application provides an apparatus, which is a first apparatus, where the first apparatus includes a connection port, a data detection device, and a data processing circuit, and the data detection device includes a first detection circuit and a second detection circuit; the connection mode of the first detection circuit and the first equipment is consistent with the connection mode of the connection port and the second equipment; the connection mode of the second detection circuit and the first equipment is different from the connection mode of the connection port and the second equipment; a first detection circuit for receiving a first input signal; a second detection circuit for receiving the first input signal; a first detection circuit for acquiring a first output signal based on a first input signal; the first output signal comprises a first input signal and a bus connection mode of the first device; the first detection circuit is used for sending a first output signal to the data processing circuit; the second detection circuit is used for generating a blocking signal, and the blocking signal is used for enabling the second detection circuit to be in a non-working state.

It will be appreciated that the first device is a slave device, the second device is a master device, the bus connection between the different slave devices and the master device is different, and the master device is responsible for sending 13bit command frames and other data to the slave devices.

In one possible implementation of the second aspect, the first detection circuit includes an instruction judging unit; and the first instruction judging unit is used for acquiring a first output signal based on the first input signal. And the first instruction judging unit is used for outputting a first output signal when the first input signal is determined to meet the data characteristic.

In one possible implementation manner of the second aspect, the connection port includes a first clock signal end and a first data signal end, where the first clock signal end is used to connect with a clock signal end of the second device, and the first data signal end is used to connect with a data signal end of the second device; the first detection circuit comprises a second clock signal end and a second data signal end, wherein the second clock signal end is used for being connected with the clock signal end of the second device, and the second data signal end is used for being connected with the data signal end of the second device; the second detection circuit comprises a third clock signal end and three data signal ends, wherein the third clock signal end is used for being connected with the data signal end of the second device, and the third data signal end is used for being connected with the clock signal end of the second device.

In a third aspect, embodiments of the present application provide a communication system, including: the system comprises a second device and at least two first devices, wherein the second device transmits a first input signal to the first devices.

Drawings

Fig. 1A illustrates an RFFE bus interface connection schematic, according to some embodiments of the present application;

fig. 1B illustrates an RFFE bus interface connection schematic diagram according to some embodiments of the present application;

FIG. 2 is a flow chart illustrating a method of determining slave bus connection according to some embodiments of the present application;

FIG. 3 illustrates a schematic diagram of a detection circuit in a slave device, according to some embodiments of the present application;

fig. 4A illustrates a schematic diagram of a configuration of an SSC detection unit, according to some embodiments of the present application;

fig. 4B shows a schematic diagram of the structure of another SSC detection element, according to some embodiments of the present application;

FIG. 5A illustrates a sequential logic diagram of an SSC detection unit, according to some embodiments of the present application;

FIG. 5B illustrates a sequential logic diagram of another SSC detection unit, according to some embodiments of the present application;

FIG. 6 illustrates a schematic diagram of an instruction predicate subunit, according to some embodiments of the present application;

Fig. 7A illustrates an RFFE bus interface connection schematic, according to some embodiments of the present application;

fig. 7B illustrates a schematic diagram of a data detection device, according to some embodiments of the present application.

Detailed Description

Illustrative embodiments of the present application include, but are not limited to, data detection methods, apparatus, and communication systems.

In order to make the objects, technical solutions and advantages of the embodiments of the present application more apparent, some embodiments of the present application will be described below with reference to the accompanying drawings and specific embodiments of the specification.

It can be understood that the data detection method of the present application may be applied to a radio frequency chip in a mobile phone, a notebook computer, etc., which is not limited herein.

Fig. 1A and 1B show a scenario in which 2 slaves and 1 master are mounted on a single RFFE bus, respectively. Specifically, as shown in fig. 1A, on the radio frequency bus, a master device 10, a slave device 11, and a slave device 12 are mounted. The clock end and the data end of the master device 10 are respectively connected with the clock end and the data end of the slave device 11 correspondingly, and the clock end and the data end of the master device 10 are respectively connected with the clock end and the data end of the slave device 12 correspondingly, that is to say, the bus connection modes of the two slave devices are correspondingly connected. As shown in fig. 1B, the clock end and the data end of the master device 10 are respectively connected with the clock end and the data end of the slave device 11 correspondingly, and the clock end and the data end of the master device 10 are respectively cross-connected with the clock end and the data end of the slave device 12, that is, the bus connection modes of the two slave devices are different.

It may be understood that the slave device may be a first device mentioned in the embodiment of the present application, and the master device may be a second device mentioned in the present application.

As previously described, in some aspects, the slave determines the bus connection mode of the slave by detecting the SSC signal. However, if the connection mode of the plurality of slave devices determined based on the SSC signal is the same as the bus connection mode in the 13bit command frame, the plurality of slave devices execute the same 13bit command frame, which causes resource waste.

In view of this, some embodiments of the present application provide a data detection method, which may be used for a first device, where the first device includes a connection port, a data detection device, and a data processing circuit, and the data detection device includes a first detection circuit and a second detection circuit, where a connection manner between the first detection circuit and the connection port is consistent with a connection manner between the second device and the connection port, and a connection manner between the second detection circuit and the connection port is different from a connection manner between the second device and the connection port; the detection method comprises the following steps: a first detection circuit and a second detection circuit are arranged in the slave device, the first detection circuit and the second detection circuit receive a first input signal, and then the first detection circuit obtains a first output signal based on the first input signal; the first output signal includes a first input signal and a bus connection of the first device. The first detection circuit sends the first output signal to the data processing circuit, and the second detection circuit generates a blocking signal, wherein the blocking signal is used for enabling the second detection circuit to be in a non-working state.

Based on the scheme, the first detection circuit with the correct bus connection mode normally executes the bus relation judging flow of the slave device in the detection process, and the second detection circuit with the incorrect bus connection mode can continuously generate blocking signals to block the detection process of the second detection circuit in the detection process. Therefore, the wrong bus connection mode is prevented from being output to the subsequent circuit module, and the accurate judgment of the bus connection mode is realized.

Referring to the following description of the data detection method mentioned in the embodiments of the present application, fig. 2 is a schematic flow chart of a data detection method according to an embodiment of the present application, where the method includes:

s101: the first device receives a first input signal transmitted by the second device.

The first device mentioned in the embodiment of the present application may be a slave device, the second device mentioned in the present application may be a master device, and the first input signal may be a 13bit command frame.

For example, in fig. 1B, the master device 10 transmits 13bit command frames to the slave device 11 and the slave device 12 through the clock side and the data side, and the slave device 11 and the slave device 12 receive the 13bit command frames transmitted by the master device 10, respectively.

S102: a first detection circuit and a second detection circuit in the first device receive the first input signal.

In some embodiments, after receiving the 13bit command frame from the slave device, the first detection circuit and the second detection circuit also receive the 13bit command frame and detect the bus connection mode of the slave device through the 13bit command frame respectively.

For example, in fig. 3, the slave device 31 receives the 13-bit command frame, and the first detection circuit 312 and the second detection circuit 313 inside the slave device 31 detect the 13-bit command frame and determine the bus connection mode of one slave device 31.

S103: a first detection circuit in the first device obtains a first output signal based on the first input signal and sends the first output signal to the data processing circuit.

In some embodiments, if the bus connection mode determined by the first detection circuit is determined to be correct based on the 13bit command frame, the first detection circuit is a detection circuit with a correct bus connection mode, and the first detection circuit includes a first instruction determination unit, where the first instruction determination unit outputs a first output signal when determining that the first input signal satisfies the data characteristic. The first detection circuit further comprises a first start signal detection unit, wherein the first start signal detection unit generates a start signal based on the high-low level change of the first input signal, and the start signal is used for enabling the first detection circuit to maintain a normal working state. Further, the first instruction judging unit may acquire the first output signal based on the first input signal, that is, the first instruction judging unit may send the bus connection manner of the slave device obtained in the 13-bit command frame and based on the 13-bit command frame to the data processing circuit.

It will be appreciated that the data characteristics include, but are not limited to, that the parity bits of the first input signal are correct, that the command sequence of the first input signal is consistent with a predetermined sequence, and the like.

For example, in fig. 3, the bus connection mode of the slave device 31 determined by the first detection circuit 312 of the slave device 31 is a corresponding connection, the bus connection mode of the slave device 31 determined by the second detection circuit 313 is a cross connection, and when the bus connection mode corresponding to the 13bit command frame is determined to be a corresponding connection based on the 13bit command frame, it can be determined that the first detection circuit 312 is a detection circuit with a correct bus connection mode, and the second detection circuit 313 is a detection circuit with an incorrect bus connection mode, further, the first start signal detection unit 3121 inside the first detection circuit 312 with a correct bus connection mode generates the SSC1 signal to ensure that the first detection circuit 312 operates normally, and the first detection circuit 312 can transmit the 13bit command frame and the bus connection mode (corresponding connection) of the slave device 31 obtained based on the 13bit command frame to the data processing circuit.

S104: the second detection circuit in the first device generates a blocking signal such that the second detection circuit is in a non-operational state.

In some embodiments, if the bus connection mode determined by the second detection circuit is incorrect based on the 13bit command frame, the second detection circuit is a detection circuit with incorrect bus connection mode, and the second detection circuit includes a second start signal detection unit, where the second start signal detection unit generates a blocking signal to close the working process of the second detection circuit.

For example, in fig. 3, the second start signal detection unit 3131 inside the second detection circuit 313 with the bus connection error generates the SSC2 signal so that the second detection circuit 313 is guaranteed to stop detection.

It is understood that the second detection circuit includes a second start signal detection unit therein; the second detection circuit generates a blocking signal. Specifically, the second start signal detection unit receives the first input signal and generates a blocking signal according to the high-low level change of the first input signal.

It will be appreciated that after the first detection circuit has stopped the detection process as a correct detection circuit, i.e. after the second detection circuit has stopped the detection process as an incorrect detection circuit, the one-time detection process is ended. At this time, the first instruction judging unit of the first detection circuit resets the first detection circuit, and the second instruction judging unit of the second detection circuit resets the second detection circuit, so that the blocking signal of the last time does not affect the next time when the master device sends the first input signal to the slave device, and the first detection circuit and the second detection circuit of the slave device can work normally.

According to some embodiments of the application, a correct detection circuit and an error detection circuit which are symmetrical in structure and different from the connection mode of the slave device are arranged in the slave device to detect the bus connection mode of the slave device, only the bus connection mode detected by the correct detection circuit is output as the bus connection mode of the slave device, and the bus connection mode is matched with the slave device address USID corresponding to the bus connection mode in a 13bit command frame sent by the master device, so that the slave device obtains the own slave device address USID. And it is guaranteed that when the data characteristic of the 13bit command frame sent by the master device to the slave device is problematic, the correct detection circuit cannot acquire the bus connection mode of the slave device based on the 13bit command frame, and the error detection circuit cannot judge the bus connection mode of the slave device again through a certain number of pulses coming subsequently, so as to output an error bus connection mode as the bus connection mode of the slave device. The stability of the whole detection system of the data detection device is improved on the premise of ensuring accurate bus judgment results.

The application provides equipment, which is first equipment, wherein the first equipment comprises a connecting port, a data detection device and a data processing circuit, and the data detection device comprises a first detection circuit and a second detection circuit; the first detection circuit is consistent with the connection mode of the connection port and the second equipment; the connection mode of the second detection circuit and the connection port is different from the connection mode of the second equipment and the connection port;

a first detection circuit for receiving a first input signal; a second detection circuit for receiving the first input signal;

a first detection circuit for acquiring a first output signal based on a first input signal; the first output signal comprises a first input signal and a bus connection mode of the first device;

the first detection circuit is used for sending a first output signal to the data processing circuit;

the second detection circuit is used for generating a blocking signal, and the blocking signal is used for enabling the second detection circuit to be in a non-working state.

The data detection device mentioned in the present application will be described in detail first.

For example, a data detection device 310 is shown in FIG. 3. As shown in fig. 3, the data detection device 310 includes a first detection circuit 312 and a second detection circuit 313. The first detection circuit 312 includes a first start signal detection unit 3121 and a first instruction determination unit 3122; the second detection circuit 313 includes a second start signal detection unit 3131, and a second instruction judgment unit 3132. Wherein the first start signal detection unit 3121 and the second start signal detection unit 3131 may be used to output an SSC1 signal controlling a normal detection process of the correct detection circuit and an SSC2 signal blocking a detection process of the error detection circuit; the first instruction judging unit 3122 and the second instruction judging unit 3132 may be used to judge whether the bus connection relationship of the detection circuits is correct and whether the data characteristics of the 13bit command frame are satisfied, and to control the first detection circuit 312 and the second detection circuit 313 to be circuit-reset.

Further, in connection with the schematic structure of the slave device 31 shown in fig. 3, the detection method mentioned in the present application is described by taking the bus connection mode between the slave device 31 and the master device 30 and the bus connection mode corresponding to the slave device address USID in the 13bit command frame sent by the master device 30 as the corresponding connection modes.

The master device 30 and the slave device 31 are specifically connected in such a manner that the first clock signal terminal C311 and the first data signal terminal D311 are connected to the second clock terminal C312 and the second data signal terminal D312 of the first detection circuit 312, respectively. The first clock signal terminal C311 and the first data signal terminal D311 are connected to the third clock terminal C313 and the third data signal terminal D313 of the second detection circuit 313, respectively. The first clock signal terminal C311 and the first data signal terminal D311 are connected to the fourth clock terminal C310 and the fourth data signal terminal D310 of the master device 30, respectively.

Specifically, when communication starts, the first detection circuit 312 and the second detection circuit 313 detect the 13bit command frame sent by the master device 30 to obtain the bus connection mode of the slave device 31. The specific detection process comprises the following steps: first, the master device 30 sends a 13-bit command frame to the slave device 31, where the bus connection mode corresponding to the 13-bit command frame is corresponding connection, and the clock corresponding to the 13-bit command frame is 0, and the data is 1. The second clock terminal C312 of the first detection circuit 312 receives the clock signal 0, the second data terminal D312 of the first detection circuit 312 receives the 13bit command frame, the third clock terminal C311 of the second detection circuit 313 receives the 13bit command frame, and the third data terminal D311 of the second detection circuit 313 receives the clock signal 0. Thus, the bus connection mode of the slave device 31 can be determined, and the bus connection mode is the same as the connection mode of the first detection circuit 312 and the first clock terminal C311 and the first data terminal D311 of the slave device 31, that is, the corresponding connection mode.

Then, the first detection circuit 312 and the second detection circuit 313 output the detection results to the data processing circuit 314, respectively, and the data processing circuit 314 can determine whether to execute the 13bit command frame based on the USID in the received 13bit command frame detected by the data detection device 310.

It will be appreciated that in some embodiments, when the first detection circuit confirms that its bus connection is the same as the bus connection corresponding to the USID in the 13bit command frame, that is, the first detection circuit is a detection circuit with a correct bus connection relationship. The first detection circuit executes the 13-bit command frame, acquires the bus connection mode of the slave device 31, and sends the 13-bit command frame and the corresponding bus connection mode as a first output signal to the data processing circuit 314.

And the third data terminal D311 of the second detection circuit 313 receives the clock signal of the master device, and correspondingly, the third clock terminal C311 of the second detection circuit 313 receives the 13bit command frame sent by the master device 30, so as to determine that the bus connection mode of the slave device 31 is cross connection. However, since the bus connection mode corresponding to the 13bit command frame is the corresponding connection mode, the second detection circuit 313 is a detection circuit with the wrong bus connection mode, and the SSC detection unit 31221 in the second detection circuit 313 generates an SSC2 signal to turn off the detection process of the second detection circuit 313.

It will be appreciated that in other embodiments, the bus connection manner corresponding to the slave address USID in the 13bit command frame sent by the master device 30 may also be a cross connection, which is not limited herein.

It can be understood that the SSC1 signal is a signal generated by a detection circuit with a correct bus relationship to ensure that the correct detection circuit detects normally; the SSC2 signal is a signal that the error detection circuit cannot perform abnormality determination due to a detection process of the shutdown error detection circuit generated in the bus relation error detection circuit.

It will be appreciated that the SSC detection unit supports asynchronous reset of the SSC2 signal to ensure that the SSC2 signal after the last communication does not affect the next communication.

It will be appreciated that in other embodiments, the first detection circuit 312 may be an error detection circuit and the second detection circuit 313 may be a correct detection circuit based on the difference between the bus connection of the two detection circuits and the slave device 31, which is not limited herein.

The following is a sequential logic diagram in conjunction with the schematic structural diagrams of the SSC detection unit shown in fig. 4A to 5B, further explaining the principle of generating SSC2 signals in the correct detection circuit and the error detection circuit in the slave device.

First, an operation principle in which the first start signal detection unit 3121 in the first detection circuit 312 generates only the SSC1 signal and does not generate the SSC2 signal is described with reference to fig. 4A and 5A.

For example, the first start signal detection unit 3121 of the correct first detection circuit 312 is schematically configured as shown in fig. 4A. The first start signal detection unit 3121 mainly includes: a first input terminal, a second input terminal, an SSC1 signal generation circuit 31211, an SSC2 signal generation circuit 31212, or a logic gate Y2. Wherein the first input terminal is connected to the data terminal C311 of the slave device 31 and the second input terminal is connected to the clock terminal D311 of the slave device 31.

The SSC1 signal generation circuit 31211 is configured by a cascade of two stages of registers T1, T2, the two stages of registers T1, T2 being configured to recognize a high pulse at the first input and generate the SSC1 signal after the recognition is successful. Since the first detection circuit 312 is a correct detection circuit at this time, only the SSC1 signal generating circuit in the first start signal detection unit 3121 within the first detection circuit 312 operates and generates the SSC1 signal, so as to ensure that the first detection circuit 312 can normally acquire the correct bus connection manner of the slave device 31 based on the 13bit command frame.

Further, fig. 5A shows a timing diagram of the first start signal detection unit 3121 in the first detection circuit 312.

Specifically, the first input terminal of the SSC2 signal generating circuit in the first start signal detecting unit 3121 receives the data signal, the second input terminal receives the clock signal, the data signal of the first input terminal is driven by the rising edge of the clock signal of the second input terminal, the divide-by-two signal generated by the clkn_div divide-by-two module inverts according to the falling edge of the clock signal of the second input terminal, and the pulse width of the clock signal of the second input terminal is extended by the divide-by-two signal clkn_div, so that the data signal of the first input terminal is identical to the pulse of the divide-by-two signal and has the phase overlapping of half the clock signal period, and therefore, no additional SSC2 signal is generated in the first detecting circuit 312.

Next, the operation principle of the second start signal detection unit 3131 in the second detection circuit 313 generating only the SSC2 signal will be described with reference to fig. 4B and 5B.

For example, the second start signal detection unit 3131 of the second detection circuit 313 shown in fig. 4B is schematically structured. The second start signal detection unit 3131 has the same structural composition as the circuit structure of the first start signal detection unit 3121 described above. Wherein the first input terminal is connected to the data terminal C311 of the slave device 31 and the second input terminal is connected to the clock terminal D311 of the slave device 31.

The SSC2 signal generating circuit 31212 is configured with a two-stage register T3, T4 cascade and a clkn_div divide-by-two module, wherein the two-stage register T3, T4 is used for identifying the high level pulse of the first input terminal, and the clkn_div divide-by-two module is used for generating the divide-by-two signal clkn_div according to the falling edge of the second input terminal, for expanding the pulse width of the second input terminal signal, and further generating the SSC2 signal for turning off the detection process of the error detecting circuit 3122. Since the second detection circuit 313 is an erroneous detection circuit at this time, only the SSC2 signal generation circuit 31212 is operated and the SSC2 signal is generated to turn off the detection operation of the second detection circuit 313 in the second start signal detection unit 3131 inside the second detection circuit 313.

Further, a timing diagram of the second start signal detection unit 3131 in the second detection circuit 313 shown in fig. 5B.

Specifically, the first input terminal of the SSC2 detection circuit in the second start signal detection unit 3131 is connected to the clock terminal of the slave device 31, i.e., the first input terminal receives the clock signal, and the second input terminal is connected to the data terminal of the slave device 31, i.e., the second input terminal receives the data signal. That is, at this time, the second input data signal is used as the clock signal, and the first input clock signal is used as the data signal. Since the clkn_div divided signal is divided by two by the falling edge of the second input data signal (as a clock signal), the pulse width of the second input data signal (as a clock signal) is extended, the minimum pulse width of the second input data signal (as a clock signal) is the same as the period of the first input clock signal (as a data signal), and the pulse width of the clkn_div divided signal is twice or more than the first input clock signal (as a data signal), the pulse width of the clkn_div divided signal is at a low level and at least contains the pulse of the first input clock signal (as a data signal), so that the SSC2 signal generating circuit generates the SSC2 signal.

It can be understood that the SSC2 signal generating circuit supports asynchronous reset of the SSC2 signal, so as to ensure that the SSC2 signal after the last communication will not affect the next communication.

Further, fig. 6 shows a schematic structural diagram of an instruction determining unit, where the first instruction determining unit 3122 is mainly composed of a collecting subunit 31221 and a determining subunit 31222, and may receive a 13bit command frame sent by a master device and determine data characteristics of the 13bit command frame, and determine a bus connection mode of a slave device after determining that the data characteristics of the 13bit command frame meet a condition. In addition, since the bus connection modes of the different detection circuits are different, the addresses used for addressing by the instruction judging units of the different detection circuits are also different. The collecting subunit 31221 mainly comprises a counter 312211 and a shift register 312212, and the collecting subunit 31221 is responsible for collecting and detecting the received 13bit command frame to determine the bus connection mode of the slave device; the judging subunit 31222 may be configured to judge whether the 13-bit command frame meets a preset data characteristic, and match a bus connection mode of the slave device with a bus connection mode corresponding to a slave device address USID in the 13-bit command frame after judging that the data characteristic of the 13-bit command frame meets a condition, so that the USID is a slave device address of the slave device.

It can be understood that the command control unit can also control the SSC detection unit to perform asynchronous reset, so as to ensure that the SSC2 signal generated by the SSC2 signal generating circuit in a certain communication will not affect the next communication.

It will be appreciated that since the two detection circuits are connected differently to the slave 31, the addresses used by the instruction determination unit for addressing are also different, and an extension of the addressing of the instruction determination unit can be achieved.

It will be appreciated that the determination disclosed in some embodiments is based on the SSC signal to determine the bus connection of the slave device. The bus connection mode of the slave device is judged mainly by the slave device receiving the SSC signal sent by the master device and obtaining the high and low levels of the clock end and the data end of the slave device according to the SSC signal.

The following describes in detail the technical solution for determining the bus connection mode of the slave device based on the SSC signal in some embodiments.

Specifically, the communication procedure between the master device 10 and the two slave devices mainly includes: the master device 10 transmits an SSC signal to a slave device connected to the master device 10 via a bus to start communication. After receiving the SSC signal sent by the master device, the slave device can determine its connection mode according to the signal received by the clock end and the data end.

It will be understood that the SSC signal is a start signal for the master to start communication with the slave, and the generating condition is that the clock terminal of the master is at a low level, and the data terminal of the master is a pulse signal, that is, the clock signal sent by the clock terminal of the master is 0, and the data signal sent by the data terminal is 1.

For example, in fig. 1A, for the slave device 11 and the slave device 12, the signals received by the clock terminals C111 and C121 of both are 0, and the slave device 11 and the slave device 32 may determine that their own clock terminals are connected to the clock terminal C101 of the master device 30. If the signals received by the data terminals D111 and D121 are both 1, the slave device 31 and the slave device 12 can determine that the data terminals thereof are both connected to the data terminal D101 of the master device 10. Further, the slave device 11 and the slave device 12 can determine that the connection method with the master device 10 is the corresponding connection.

For another example, in fig. 1B, if the signals received by the clock terminal C111 and the data terminal D111 of the slave device 11 are 0 and 1, respectively, the slave device 11 may determine that the clock terminal C111 of the slave device is connected to the clock terminal C101 of the master device 10, the data terminal D111 of the slave device 11 is connected to the data terminal D101 of the master device 10, and the slave device 11 may determine that the connection modes with the master device 10 are all corresponding connections. For the slave device 12, the signals received by the clock terminal C121 and the data terminal D111 are 1 and 0 respectively, the slave device 12 can determine that the clock terminal C121 of the slave device is connected to the data terminal D101 of the master device 10, the data terminal D121 of the slave device 12 is connected to the clock terminal C101 of the master device 10, and the slave device 12 can determine that the connection modes with the master device 10 are cross-connection. Further, the master device 10 transmits a first input signal to the slave device.

It will be appreciated that the first input signal comprises a 13bit command frame consisting of a 4bit slave address USID, a 3bit register write identification code (010), a 5bit register address, a 1bit parity bit P. The command frame composition of different read-write command sequences may be different, and the embodiment of the present application uses a 13bit command frame of a write command as an example, which is not limited herein;

in this way, after the slave device receives the first input signal, it can confirm whether its own bus connection mode is the same as the bus connection mode corresponding to the USID according to the USID in the 13bit command frame in the first input signal. If so, the slave considers the 13bit command frame to be sent to itself for execution and then executes the 13bit command frame.

For example, for the scenario shown in fig. 1B, the slave device 12 determines that its own bus connection is a cross connection according to the SSC signal, executes the specific content in the 13-bit command frame if the bus connection represented by the USID in the received 13-bit command frame is a cross connection, and does not execute the specific content in the 13-bit command frame if the bus connection represented by the USID in the received 13-bit command frame is a corresponding connection.

It will be appreciated that in this scenario, the slave device is dependent on the connection mode determined by the SSC signal to determine whether to execute the received 13bit command frame. If the connection mode of the plurality of slave devices judged based on the SSC signals is the same as the bus connection mode in the 13-bit command frame, the plurality of slave devices execute the same 13-bit command frame, so that resource waste is caused. If the bus connection modes determined by the slave devices based on the SSC signals are different from the bus connection modes in the 13bit command frame, there are cases where the slave devices do not execute the 13bit command frame sent by the master device.

For example, in the scenario shown in fig. 1A, the connection modes determined by the slave device 11 and the slave device 12 based on the SSC signal are both corresponding connections, so, after receiving the 13bit command frame sent by the master device 10, if the bus connection mode indicated by the USID in the received 13bit command frame is the corresponding connection mode, the slave devices 11 and 12 execute the specific content in the 13bit command frame, which may cause resource waste. If the bus connection mode indicated by the USID in the received 13-bit command frame is a cross connection mode, neither slave device executes the 13-bit command frame, i.e. the slave device does not execute the 13-bit command frame sent by the master device 10.

While for the connection of fig. 1B, although the different bus connections of the two slaves 11 and 12 can be distinguished by the SSC signal, if present: before primary master-slave communication, the clock signal of the clock terminal C111 and the data signal of the data terminal D111 of the master device 10 are both 0, that is, a normal SSC signal cannot be generated to start communication, but at this time, the data terminal D111 of the master device 10 has burrs, so that the data signal of the master device 10 becomes 1, and the master device 10 mistakenly triggers an SSC signal, and the slave device 11 and the slave device 12 still detect after receiving the SSC signal, so as to detect the bus connection mode of themselves. However, the SSC signal is transmitted due to a false trigger by the master device 10, and then no further 13bit command frames are transmitted. Thus, the slave device 11 and the slave device 12 perform one-time detection that is not necessary.

According to the scheme, the detection circuit with the correct bus connection mode in the two detection circuits in the slave device detects the 13bit command frame to acquire the correct bus connection mode of the slave device, so that the slave device with the same bus connection mode as the USID in the 13bit command frame executes the 13bit command frame, and the slave device with the different bus connection mode as the USID in the 13bit command frame does not execute the 13bit command frame, and the problem of resource waste caused by the fact that a plurality of slave devices execute the 13bit command frame in the scheme is solved.

It will be appreciated that the manner of determination disclosed in some embodiments is based on a 13bit command frame to determine the bus connection of the slave device. The bus connection mode of the slave device can be judged according to whether clock signals or 13bit command frames are respectively received by a clock end and a data end of the two detection circuits.

The following describes in detail the technical solution for determining the bus connection mode of the slave device based on the 13bit command frame in some embodiments.

Specifically, the master device generally transmits a clock signal through a clock end and transmits a 13bit command frame through a data end, two detection circuits are arranged in a data signal detection device in the slave device, wherein the clock end and the data end of one detection circuit are correspondingly connected with the clock end and the data end of the slave device, and the clock end and the data end of the other detection circuit are respectively in cross connection with the clock end and the data end of the slave device. When the bus connection mode of the slave device is the corresponding connection mode, in the data signal detection device in the slave device, the clock end of the detection circuit correspondingly connected with the clock end and the data end of the slave device receives the clock signal, the data end receives the 13bit command frame, the clock end of the detection circuit cross-connected with the clock end and the data end of the slave device receives the 13bit command frame, and the data end receives the clock signal. When the bus connection mode of the slave device is a cross connection mode, in the data signal detection device inside the slave device, the clock end of the detection circuit of the cross connection slave device and the data end receives the clock signal, the data end receives the 13bit command frame, the clock end of the detection circuit of the corresponding connection slave device and the data end receives the 13bit command frame, and the data end receives the clock signal.

Therefore, the bus connection mode of the slave device can be confirmed by judging whether the clock end and the data end of the two detection circuits respectively receive the clock signal or the 13bit command frame.

Specifically, for example, as shown in fig. 7A, the bus connection modes of the slave device 21 and the slave device 22 and the master device 20 are corresponding connection and cross connection, respectively, and the data detection means 212 and the data detection means 222 are provided inside the slave device 21 and the slave device 22, respectively. The data detection means 212 and 222 can confirm the bus connection mode of the slave device by means of the internal two detection circuits. A specific detection method by the data detection device 212 will be described below by taking the data detection device as an example.

As shown in fig. 7B, the data detection device 212 includes a first detection circuit 2121 and a second detection circuit 2122. The clock terminal C2121 and the data terminal D2121 of the first detection circuit 2121 are respectively connected to the clock terminal C211 and the data terminal D211 of the slave device 21, the clock terminal C2122 of the second detection circuit 2122 is connected to the data terminal D211 of the slave device 21, and the data terminal D2121 is connected to the clock terminal C211 of the slave device 51.

Assuming that the slave device 21 and the master device 20 are correspondingly connected as shown in fig. 7A, when the master device 20 transmits a clock signal through the clock terminal C211 and transmits a 13bit command frame to the slave device 21 through the data terminal D211, the clock terminal C2121 of the first detection circuit 2121 receives the clock signal, the data terminal D2121 of the first detection circuit 2121 receives the 13bit command frame, the clock terminal C2122 of the second detection circuit 2122 receives the 13bit command frame, and the data terminal D2122 of the first detection circuit 2121 receives the clock signal. Thus, the bus connection mode of the slave device 21 can be determined, which is the same as the connection mode of the first detection circuit 2121 and the clock terminal C211 and the data terminal D211 of the slave device 21, that is, the corresponding connection mode.

Then, the first detection circuit 2121 and the second detection circuit 2122 output detection results to the data processing circuit 2124, respectively, and the data processing circuit 2124 can determine whether to execute the 13-bit command frame by determining the USID in the received 13-bit command frame based on the bus connection method detected by the data detection device 212.

Assuming that the slave device 21 and the master device 20 are correspondingly connected and cross-connected, when the master device 20 sends a clock signal through the clock terminal C201 and sends a 13bit command frame through the data terminal D201, the clock terminal C2122 of the second detection circuit 2122 is connected to the data terminal D211 of the slave device 21, and the data terminal D511 of the slave device 21 is connected to the clock terminal C201 of the master device 20, so that the clock terminal C2122 of the second detection circuit 2122 receives the clock signal sent by the master device 50, and correspondingly, the data terminal D2122 of the second detection circuit 2122 receives the 13bit command frame sent by the master device 20, so that it can be determined that the bus connection mode of the slave device 21 is the same as the connection mode of the clock terminal C211 and the data terminal D211 of the second detection circuit 2122 and the slave device, that is, the cross connection.

Then, the first detection circuit 2121 and the second detection circuit 2122 output detection results to the data signal processing circuit 2124, respectively, and the data signal processing circuit 2124 can determine whether to execute the 13-bit command frame by determining the USID in the received 13-bit command frame based on the bus connection method detected by the data detection device 212.

However, in the above embodiment, if the 13-bit command frame sent from the master device is interfered and distorted during the transmission process, the 13-bit command frame does not satisfy the data characteristic (the parity bit is correct and the command sequence is the RFFE protocol specified sequence), which results in that in the data detection device of the slave device, the detection circuit that connects the data end with the data end of the master device will not determine the bus connection mode according to the 13-bit command frame. Therefore, another detection circuit in the data detection device can re-collect the clock signal and the 13bit command frame once, at this time, since the data end of the detection circuit is connected with the clock end of the master device, the clock end is connected with the data end of the master device, and the output bus connection mode is not the bus connection mode of the slave device, the problem of error judgment of the bus connection mode of the slave device can occur.

For example, with the scenario shown in fig. 7A and 7B, if the 13bit command frame transmitted by the master device 20 is disturbed during transmission, and the data characteristics are not satisfied, the first detection circuit 2121 will not determine the bus connection mode for the 13bit command frame, and only the second detection circuit 2122 will determine it. The bus connection method determined by the second detection circuit 2122 is cross connection, but the connection method of the slave device 21 and the master device 20 is corresponding connection, so that the determination result is erroneous.

According to the scheme, the 13bit command frame is detected by the detection circuit with the correct bus connection mode in the two detection circuits in the slave device so as to acquire the correct bus connection mode of the slave device, and the detection circuit with the incorrect bus connection mode stops detecting after judging that the detection circuit is the error detection circuit. Therefore, only the correct detection circuit can correctly detect the bus connection mode of the slave device, and the accuracy of the result of the bus connection mode of the slave device, which is caused by the fact that the error detection circuit detects the bus connection mode of the wrong slave device in the scheme, is solved.

The application provides equipment, which is first equipment, wherein the first equipment comprises a connecting port, a data detection device and a data processing circuit, and the data detection device comprises a first detection circuit and a second detection circuit; the first detection circuit is consistent with the connection mode of the connection port and the second equipment; the connection mode of the second detection circuit and the connection port is different from the connection mode of the second device and the connection port, wherein:

a first detection circuit for receiving a first input signal; a second detection circuit for receiving the first input signal; a first detection circuit for acquiring a first output signal based on a first input signal; the first output signal includes a first input signal and a bus connection of the first device.

The first detection circuit is used for sending a first output signal to the data processing circuit; the second detection circuit is used for generating a blocking signal, and the blocking signal is used for enabling the second detection circuit to be in a non-working state.

The first detection circuit comprises a first instruction judging unit;

a first instruction judging unit for acquiring a first output signal based on a first input signal;

and the first instruction judging unit is used for outputting a first output signal when the first input signal is determined to meet the data characteristic.

The connection port comprises a first clock signal end and a first data signal end, the first detection circuit comprises a second clock signal end and a second data signal end, the second detection circuit comprises a third clock signal end and a third data signal end, and the second device comprises a fourth clock signal end and a fourth data signal end.

The connection mode of the first detection circuit and the connection port is consistent with the connection mode of the second device and the connection port, the connection mode of the second detection circuit and the connection port is different from the connection mode of the second device and the connection port, and the connection mode detection circuit comprises:

the first clock signal end is connected with the fourth clock signal end, and the first data signal end is connected with the fourth data signal end;

The second clock signal end is connected with the fourth clock signal end, and the second data signal end is connected with the fourth data signal end;

the third clock signal end is connected with the fourth data signal end, and the third data signal end is connected with the fourth clock signal end.

The embodiment of the application provides a communication system, which comprises: the system comprises a second device and at least two first devices, wherein the second device transmits a first input signal to the first devices.

The embodiment of the application can also provide electronic equipment comprising the communication system, wherein the electronic equipment can be any electronic equipment such as a mobile phone, a computer and the like.

The embodiment of the application also provides a program product for realizing the data detection method provided by the above embodiments.

Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of these implementations. Embodiments of the present application may be implemented as computer modules or module code executing on a programmable system including at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.

Module code may be applied to input instructions to perform the functions described herein and generate output information. The output information may be applied to one or more output devices in a known manner. For purposes of this application, a processing system includes any system having a processor such as, for example, a digital signal processor (digital signal processor, DSP), microcontroller, application specific integrated circuit (application specific integrated circuit, ASIC), or microprocessor.

The module code may be implemented in a high level modular language or an object oriented programming language for communication with a processing system. The module code may also be implemented in assembly or machine language, if desired. Indeed, the mechanisms described in the present application are not limited in scope to any particular programming language. In either case, the language may be a compiled or interpreted language.

In the drawings, some structural or methodological features may be shown in a particular arrangement and/or order. However, it should be understood that such a particular arrangement and/or ordering may not be required. Rather, in some embodiments, these features may be arranged in a different manner and/or order than shown in the illustrative figures. Additionally, the inclusion of structural or methodological features in a particular figure is not meant to imply that such features are required in all embodiments, and in some embodiments, may not be included or may be combined with other features.

It should be noted that, in the embodiments of the present application, each unit/module is a logic unit/module, and in physical aspect, one logic unit/module may be one physical unit/module, or may be a part of one physical unit/module, or may be implemented by a combination of multiple physical units/modules, where the physical implementation manner of the logic unit/module itself is not the most important, and the combination of functions implemented by the logic unit/module is the key to solve the technical problem posed by the present application. Furthermore, to highlight the innovative part of the present application, the above-described device embodiments of the present application do not introduce units/modules that are less closely related to solving the technical problems presented by the present application, which does not indicate that the above-described device embodiments do not have other units/modules.

It should be noted that in the examples and descriptions of this patent, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

While the present application has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present application.

Claims

1. The data detection method is used for a first device and is characterized in that the first device comprises a connection port, a data detection device and a data processing circuit, the data detection device comprises a first detection circuit and a second detection circuit, the connection mode of the first detection circuit and the connection port is consistent with the connection mode of a second device and the connection port, and the connection mode of the second detection circuit and the connection port is different from the connection mode of the second device and the connection port;

the first detection circuit and the second detection circuit receive a first input signal;

the first detection circuit obtains a first output signal based on the first input signal; the first output signal comprises the first input signal and a bus connection mode of the first device;

the first detection circuit sends the first output signal to the data processing circuit;

The second detection circuit generates a blocking signal for enabling the second detection circuit to be in a non-working state.

2. The data detection method according to claim 1, wherein the first detection circuit includes a first instruction judgment unit;

the first instruction judging unit acquires the first output signal based on the first input signal.

3. The data detection method according to claim 2, wherein the first instruction judging unit acquires the first output signal based on the first input signal, comprising:

the first instruction judging unit outputs the first output signal when it is determined that the first input signal satisfies a data characteristic.

4. A data detection method according to claim 3, wherein the data characteristic comprises that the parity bits of the first input signal are correct and that the command sequence of the first input signal corresponds to a predetermined sequence.

5. The data detection method according to claim 1, wherein the first detection circuit further includes a first start signal detection unit, further comprising:

the first start signal detection unit generates a start signal based on the high-low level change of the first input signal, wherein the start signal is used for enabling the first detection circuit to maintain a normal working state.

6. The data detection method according to claim 1, wherein the second detection circuit includes a second start signal detection unit therein; the second detection circuit generates the blocking signal, comprising:

the second start signal detection unit receives the first input signal and generates the blocking signal according to the high-low level change of the first input signal.

7. The data detection method according to claim 2, wherein the second detection circuit includes a second instruction judgment unit;

after the data processing circuit receives the first output signal,

the first instruction judging unit resets the first detection circuit generating circuit;

the second instruction judging unit resets the second detection circuit generating circuit.

8. The data detection method of claim 1, wherein the connection port comprises a first clock signal terminal and a first data signal terminal, the first detection circuit comprises a second clock signal terminal and a second data signal terminal, the second detection circuit comprises a third clock signal terminal and a third data signal terminal, and the second device comprises a fourth clock signal terminal and a fourth data signal terminal;

The connection mode of the first detection circuit and the connection port is consistent with the connection mode of the second device and the connection port, and the connection mode of the second detection circuit and the connection port is different from the connection mode of the second device and the connection port, comprising:

9. The device is characterized by being a first device, wherein the first device comprises a connection port, a data detection device and a data processing circuit, and the data detection device comprises a first detection circuit and a second detection circuit; the connection modes of the first detection circuit, the connection port and the second equipment are consistent with the connection mode of the connection port; the connection mode of the second detection circuit and the connection port is different from the connection mode of the second device and the connection port;

The first detection circuit is used for receiving a first input signal; the second detection circuit is used for receiving the first input signal;

the first detection circuit is used for acquiring a first output signal based on the first input signal; the first output signal comprises the first input signal and a bus connection mode of the first device;

the first detection circuit is used for sending the first output signal to the data processing circuit;

10. The apparatus according to claim 9, wherein the first detection circuit includes a first instruction judgment unit;

the first instruction judging unit is used for acquiring a first output signal based on the first input signal;

the first instruction judging unit is used for outputting the first output signal when the first input signal is determined to meet the data characteristic.

11. The device of claim 9, wherein the connection port comprises a first clock signal terminal and a first data signal terminal, the first detection circuit comprises a second clock signal terminal and a second data signal terminal, the second detection circuit comprises a third clock signal terminal and a third data signal terminal, and the second device comprises a fourth clock signal terminal and a fourth data signal terminal;

12. A communication system, comprising: a second device, at least two first devices according to claim 9, the second device sending the first input signal to the first device.