CN116545447A

CN116545447A - Satellite signal encoder and decoder based on FPGA

Info

Publication number: CN116545447A
Application number: CN202310830881.9A
Authority: CN
Inventors: 常兴
Original assignee: Wuhan Cpctech Co ltd
Current assignee: Wuhan Cpctech Co ltd
Priority date: 2023-07-07
Filing date: 2023-07-07
Publication date: 2023-08-04

Abstract

The invention relates to the technical field of information processing, in particular to a satellite signal encoder and a satellite signal decoder which are realized based on an FPGA. Furthermore, the circuit design and simulation are realized by using the FPGA (Field Programmable Gate Array ) without using the assembly of an actual hardware circuit, so that the circuit development time can be saved, the waste of hardware resources can be reduced, and the development efficiency can be improved.

Description

Satellite signal encoder and decoder based on FPGA

Technical Field

The invention relates to the technical field of information processing, in particular to a satellite signal encoder and decoder based on FPGA.

Background

Channel codec is a key element in satellite communication systems. Since the original signal is not suitable for direct transmission in the prescribed Channel, it is necessary to process the original signal to a form suitable for transmission in the prescribed Channel, and this encoding process and the corresponding decoding process are called Channel Coding (Channel Coding).

Satellite communication is applied to various fields, such as the fields of weather, navigation, earth resource detection, data transmission of large-area television programs and broadcast programs, and the like, because of the advantages of wide coverage, long communication distance, no limitation of complex geographic conditions or natural disasters, large communication capacity, mobile communication or emergency communication realization and the like. Along with the continuous expansion of satellite communication application fields, requirements on transmission signals are higher and higher, for example, weather surveys and large-area television broadcasting need to process a large amount of weather data or image information, high-performance encoding and decoding equipment is needed to accelerate the signal processing speed, and meanwhile, stronger anti-interference capability is required to improve the quality and efficiency of a satellite communication system.

In the widely adopted satellite signal encoding and decoding equipment at present, special equipment based on hardware circuits is used, namely, different hardware circuits are required to be designed aiming at different signals and different application fields, so that the development cost is high and the development period is long; in addition, once the design of the devices is completed, the devices cannot be changed and upgraded, so that the devices are difficult to adapt to new satellite signal coding standards or upgrade existing functions, and are relatively inefficient in maintenance and management.

In summary, the existing satellite signal encoding and decoding method needs higher development resources and maintenance resources, and the product has low adaptability and flexibility and low resource utilization rate.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a satellite signal encoder and a satellite signal decoder which are realized based on an FPGA, which are used for solving the defects that in the prior art, different hardware circuits are specially designed for signals with different purposes, the development period is long and the resource cost is high, realizing a coding and decoding development scheme with wider applicability, and not needing special research.

The invention provides a satellite signal encoder realized based on an FPGA, which comprises a BCH encoding module and an LDPC encoding module; the output end of the BCH coding module is connected with the input end of the LDPC coding module;

the BCH coding module is used for shifting the input message sequence to obtain a first coding sequence corresponding to the input message sequence;

the LDPC coding module is used for calculating a check matrix of the first coding sequence and determining a second coding sequence according to the product of the check matrix and the BCH coding sequence;

the LDPC coding module is used for outputting the second coding sequence to a preset channel.

According to the satellite signal encoder based on FPGA, each BCH encoder comprises three linear feedback shift registers; the satellite signal encoder further includes a first counter control gate and a second counter control gate;

each BCH coding module is used for resetting each register;

under the condition that a first counter control gate is opened and a second counter control gate is closed, each BCH coding module is used for acquiring an input message sequence, sequentially inputting the input message sequence into the three linear feedback shift registers, enabling the three linear feedback shift registers to perform division operation on the input message sequence to obtain check bits, and outputting a first group of information elements;

under the condition that the first counter control gate is closed and the second counter control gate is opened, each BCH coding module is used for outputting the check bit; and combining the check bits with the first group of information elements to obtain a first coding sequence corresponding to the input message sequence.

According to the satellite signal encoder based on the FPGA, the LDPC encoding module comprises a linear feedback shift register, a column accumulator buffer, a row processor and an output controller;

the linear feedback shift register is used for generating an LDPC base matrix aiming at the first coding sequence;

the column accumulator is used for calculating variable nodes and check nodes according to the LDPC base matrix;

the column accumulator cache is used for receiving and storing the variable nodes and the check nodes;

the row processor is used for carrying out potential difference calculation on the variable nodes and the check nodes to obtain a check matrix;

and the output controller is used for multiplying the first code sequence by the check matrix to obtain the second code sequence.

According to the satellite signal encoder based on the FPGA, the LDPC encoding module further comprises a controller; the controller is respectively connected with the column accumulator and the column accumulator buffer;

the controller is used for controlling the column accumulator to output the variable node and the check node to the column accumulator buffer according to a first preset clock period;

the controller is used for controlling the column accumulator buffer to output the variable node and the check node to the row processor according to a second preset clock period.

According to the satellite signal encoder based on the FPGA, the satellite signal encoder comprises a plurality of BCH encoding modules;

the output of each BCH coding module is connected with the input of the LDPC coding module;

each BCH coding module is used for shifting the input message grouping sequence to obtain a first coding grouping sequence corresponding to each group of input message grouping sequences; the input message grouping sequence is obtained by grouping the input message sequence;

the LDPC coding module is used for combining all first coding grouping sequences to obtain the first coding sequence; and calculating a check matrix of the first coding sequence, and determining a second coding sequence according to the product of the check matrix and the first coding sequence.

The invention also provides a satellite signal decoder realized based on the FPGA, which comprises an LDPC decoding module and a BCH decoding module; the output end of the LDPC decoding module is connected with the input end of the BCH decoding module;

the LDPC decoding module is used for receiving a sequence to be decoded from the preset channel; decoding the sequence to be decoded by utilizing a decoding algorithm based on probability theory to obtain an LDPC decoding result;

and the BCH decoding module is used for checking the LDPC decoding result to obtain a final decoding result and outputting the final decoding result.

According to the satellite signal decoder based on the FPGA, the LDPC decoding module comprises a noise scale conversion module, a local oscillation generator, a linear feedback shift register and a controller;

the noise scale transformation module is used for carrying out scale adjustment on the sequence to be decoded to obtain a sequence to be decoded after the scale adjustment;

the local oscillation generator is used for generating a high-frequency signal;

the linear feedback shift register is used for generating a synchronizing signal according to the high-frequency signal, and carrying out phase synchronization on the sequence to be decoded after the scale adjustment by utilizing the synchronizing signal to obtain a synchronizing result;

the controller is used for carrying out multiple iterations on the synchronous result until a preset decoding condition is met, and outputting an LDPC decoding result; in each iteration, the controller updates the check node according to the estimated value vector obtained in the previous iteration; calculating the synchronization result based on the check matrix to obtain a current estimated value vector transmitted by a variable node to a check node connected with the variable node; judging whether the current estimated value vector meets the preset decoding condition, and if so, outputting the current estimated value vector as an LDPC decoding result.

According to the satellite signal decoder based on the FPGA, in each iteration, the current estimated value vector is phase-synchronized by using the synchronizing signal which is generated by the local oscillation generator and the linear feedback shift register together, so as to obtain the synchronized current estimated value vector.

According to the satellite signal decoder based on FPGA, the BCH decoding module is used for calculating a comprehensive mismatch operator aiming at the LDPC decoding result; calculating a polynomial through a Berlekamp algorithm; finding the root of the polynomial using the Chein Search algorithm; the root is used for displaying the error code position; and correcting errors according to the error code positions to obtain the final decoding result.

According to the satellite signal decoder based on the FPGA, the satellite signal decoder comprises a plurality of BCH decoding modules;

the input of each BCH decoding module is connected with the output of the LDPC decoding module;

the LDPC decoding module is used for grouping the sequences to be decoded to obtain a plurality of grouping sequences to be decoded; decoding each group of grouping sequence lines to be decoded to obtain LDPC decoding grouping results; inputting LDPC decoding grouping results into each BCH decoding module respectively;

each BCH decoding module is used for checking the LDPC decoding grouping result row to obtain a grouping checking result, combining the grouping checking results to obtain a final decoding result, and outputting the final decoding result.

The invention realizes the design of the satellite communication signal encoder by using the cascading mode of the BCH encoding module and the LDPC encoding module and the design of the satellite communication signal decoder by using the cascading mode of the BCH decoding module and the LDPC decoding module, and the encoder or the decoder obtained by the design can be widely applied to encoding and decoding of various satellite communication signals, thereby improving the wide applicability of the circuit.

Furthermore, the circuit design and simulation are realized by using the FPGA (Field Programmable Gate Array ) without using the assembly of an actual hardware circuit, so that the circuit development time can be saved, the waste of hardware resources can be reduced, and the development efficiency can be improved.

Drawings

Fig. 1 is a schematic structural diagram of a satellite signal encoder and decoder based on FPGA implementation provided by the present invention;

FIG. 2 is a schematic diagram of an internal structure of a linear shift register according to the present invention;

FIG. 3 is a schematic diagram of a BCH encoder according to the present invention;

FIG. 4 is a schematic diagram of an LDPC encoding module according to the present invention;

FIG. 5 is a schematic diagram of another FPGA-based satellite signal encoder and decoder according to the present invention;

FIG. 6 is a schematic diagram of an LDPC decoder according to the present invention;

FIG. 7 is a schematic diagram of a BCH decoder according to the present invention.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

Example 1:

referring to fig. 1-2, a circuit configuration diagram of a satellite signal encoder is shown:

the invention provides a satellite signal encoder based on FPGA, comprising a BCH encoding module 101 and an LDPC encoding module 102; as shown in fig. 1, wherein an output end of the BCH encoding module is connected with an input end of the LDPC encoding module;

the BCH encoding module 101 is configured to shift an input message sequence to obtain a first encoded sequence corresponding to the input message sequence;

the BCH coding module is used for generating a BCH code; the BCH code is a cyclic code proposed by three people Bose, chandhari, hocquenghem and capable of correcting a plurality of random errors, and is one of the best linear block codes, and can divide a message sequence to be sent by a source into message groups according to a fixed k-bit group mode, and then independently transform each message group into a binary digit group of n (n > k), which is called a codeword. If the number of message groups is M (M.gtoreq.2), the totality of the M codewords thus obtained is called a block code of code length n and the number of message groups is M, i.e. BCH coding. In general, parameters of the BCH code can be expressed by (n, k, t), where n is a code length, k is a number of transmitted information bits, the number of check bits generated after encoding is n-k, each check bit is called a check element, and t is the maximum number of error bits that can be corrected by the BCH code.

As cyclic codes, the BCH encoder is mainly implemented by a linear feedback shift register, specifically, an (n-k) level dividing circuit (i.e. the linear feedback shift register) can be adopted to process an input message sequence sent by an information source, so as to realize the encoding process of the BCH code, and obtain a first encoding sequence, namely BCH (n, k, t) codes.

As shown in fig. 2, fig. 2 is a logic gate implementation block diagram of a (n-k) stage linear feedback shift register implemented by an FPGA, where,、/>、…、/>the linear feedback shift register comprises (n-k) D flip-flops. />、/>、…、/>Item 1, item 2, … … (n-k-1) in the generator polynomial for the BCH (n, k, t) code;

specifically, describing the circuit shown in fig. 2, the initial state of the linear feedback shift register is cleared first, and in clock cycles 1 to k, the counter control gate S1 is opened (S1 is grounded as shown in fig. 2), S2 is closed (S2 is set to 2), and the first k bits in the original message sequence (i.e., the input message sequence) are input from the input terminal, where the linear feedback shift register can output the k bits unchanged; meanwhile, the first k bits in the original message sequence are sent to a shift register to calculate (n-k) bit parity check bits;

for clock periods k+1 to n, the counter control gate S1 is closed, S2 is open (S2 is set at 1), and the above parity bits stored in the linear feedback shift register are output; the (n-k) bit parity check bits are combined with the k bits already output to obtain an n-bit BCH code, i.e., a first code sequence.

The LDPC coding module is used for calculating a check matrix of the first coding sequence and determining a second coding sequence according to the product of the check matrix and the first coding sequence;

Specifically, an LDPC code (Low-density Parity-check) is a linear block code, and the LDPC code is designed to start with constructing a check matrix H and then perform subsequent encoding through the check matrix H.

In the invention, the LDPC coding module generates a check matrix H for the first coding sequence, determines a second coding sequence according to the product of the check matrix H and the first coding sequence (namely BCH coding), and outputs the second coding sequence value to a preset channel (such as an air interface).

According to the embodiment, the design of the satellite communication signal encoder is realized in a mode that the BCH coding module and the LDPC coding module are cascaded through the FPGA design, and finally generated codes can be widely applied to various satellite communication purposes through the combination of the BCH coding module and the LDPC coding module, so that the wide applicability of the circuit is improved.

Further, by using BCH coding in combination with LDPC coding, link reliability is improved and data throughput is increased.

Example 2:

on the basis of the satellite signal encoder based on FPGA implementation provided in the above embodiment 1, as shown in fig. 3, in the satellite signal encoder based on FPGA implementation provided in this embodiment, each BCH encoder includes three linear feedback shift registers; the satellite signal encoder further comprises a first counter control gate S1 and a second counter control gate S2;

each BCH coding module is used for resetting each register;

under the condition that a first counter control gate S1 is opened and a second counter control gate S2 is closed, each BCH coding module is used for acquiring an input message sequence, sequentially inputting the input message sequence into three linear feedback shift registers, enabling the three linear feedback shift registers to perform division operation on the input message sequence to obtain check bits, and outputting a first group of information elements;

each BCH encoding module for outputting the check bit with the first counter control gate S1 closed and the second counter control gate S2 open; and combining the check bits with the first group of information elements to obtain a first coding sequence corresponding to the input message sequence.

In the embodiment, the BCH encoder is realized through three linear feedback shift register combinations, and a data base is provided for realizing satellite signal encoding subsequently.

Example 3:

on the basis of the satellite signal encoder implemented based on the FPGA provided in the above embodiment 1, fig. 4 shows a schematic structural diagram of an LDPC encoding module in the satellite signal encoder, where the LDPC encoding module includes a linear feedback Shift register (Shift register), a column accumulator (Column Accumulator), a column accumulator buffer (Column Accumulator Buffer), a Row Processor (Row Processor), and an Output controller (Output Control);

the linear feedback shift register is used for generating LDPC base matrix for the first code sequence (namely BCH code)；

The LDPC base matrix is used for generating a check matrix H.

The column accumulator is used for being based on the LDPC base matrixCalculating variable nodes and check nodes; wherein, according to the principle of linear block code correlation, LDPC base matrix +.>The column vectors satisfy a certain relation, so that the variable nodes and the check nodes also satisfy a certain relation, and therefore, the column accumulator can be utilized to control the LDPC base matrix +.>And calculating each column vector in the set to obtain a variable node and a check node.

the row processor is used for carrying out potential difference calculation on the variable nodes and the check nodes to obtain a check matrix H; the bit difference calculation means that the difference of each bit connected with the variable node and the check node is compared in a Hamming distance or other measurement mode;

Specifically, the LDPC code is an error correction code which realizes encoding by a sparse check matrix, and as shown in FIG. 4, the LDPC encoding module first generates an LDPC base matrix by a linear feedback shift registerCalculating Variable Nodes (VN) and check Nodes through a column accumulator, storing the calculated Nodes in a column accumulator buffer, calculating bit difference through a row processor to obtain a check matrix H, and finally inputting data (namely a first coding sequence) through an output controllerColumn, also BCH code) is multiplied by the check matrix H to obtain an LDPC code.

According to the embodiment, the LDPC encoder is formed by combining various gate circuits in the FPGA, so that the BCH error correction code can be generated into the LDPC code, and the reliability and the safety of information to be transmitted are improved.

Example 4:

based on the FPGA-based satellite signal encoder provided in embodiment 3, in the FPGA-based satellite signal encoder, the LDPC encoding module further includes a Controller (Controller); the controller is respectively connected with the column accumulator and the column accumulator buffer; as shown in fig. 4:

The difference metric value obtained by the bit difference calculation is used for filling the check matrix. Each row of the check matrix represents a check node and each column represents a variable node. The difference metric values are filled in to the corresponding positions.

In the above embodiments, the Controller (Controller) controls the working flow of each logic gate in different clock cycles, so that accurate channel coding can be obtained.

Example 5:

as shown in fig. 5, according to the present invention, a satellite signal encoder implemented based on an FPGA includes a plurality of BCH encoding modules;

In the embodiment, the plurality of BCH coding modules are used for coding simultaneously, so that the throughput of the system can be improved. Meanwhile, the plurality of BCH coding modules are detachable, so that the flexibility of the system can be improved.

Example 6

The invention also provides a satellite signal decoder based on FPGA, as shown in figure 1, comprising an LDPC decoding module 103 and a BCH decoding module 104; wherein, the output end of the LDPC decoding module 103 is connected with the input end of the BCH decoding module 104;

The specific decoding process of the LDPC decoding module is described in embodiment 7 below, and the specific decoding process of the BCH decoding module is described in embodiment 8 below.

According to the embodiment, the LDPC decoding module and the BCH decoding module can decode the coded signal of the original signal and realize error correction, so that the signal transmission reliability is improved.

Example 7

As shown in fig. 6, according to the present invention, the LDPC decoding module includes a noise scale conversion module (Noise Dependent Scaling), a Local oscillator (Local oscillator), a linear feedback Shift register (Shift register), and a Controller (Controller);

the local oscillation generator is used for generating a high-frequency signal;

the controller is used for carrying out multiple iterations on the synchronous result until a preset decoding condition is met, and outputting an LDPC decoding result; in each iteration, the controller updates the check node according to the estimated value vector obtained in the previous iteration; calculating the synchronization result based on a Check matrix to obtain a current estimated value vector transmitted by a Variable node (VN, variable Nodes) to a Check node (CN, check Nodes) connected with the Variable node; judging whether the current estimated value vector meets the preset decoding condition, and if so, outputting the current estimated value vector as an LDPC decoding result.

Wherein an additive white gaussian noise generator is used to simulate noise and interference.

As shown in fig. 6, according to the satellite signal decoder based on the FPGA implementation provided by the present invention, in each iteration, a synchronization signal generated by a local oscillation generator and a linear feedback shift register is used to perform phase synchronization on the current estimated value vector, so as to obtain a synchronized current estimated value vector.

Example 8

According to the satellite signal decoder based on FPGA implementation provided by the present invention, as shown in fig. 7, the BCH decoding module 104 is configured to calculate a comprehensive appropriate match operator (Syndrome Calculator) for the LDPC decoding result; calculating a polynomial through a Berlekamp algorithm; finding the root of the polynomial using the Chein Search algorithm; the root is used for displaying the error code position; and correcting errors according to the error code positions to obtain the final decoding result.

The Berlekamp algorithm is used for solving constant coefficient linear recursion; the Chein Search algorithm is used to calculate the root of the error location polynomial to determine the number of error locations. PCN: one parameter in the place and route tool in the FPGA is used to indicate the priorities and constraints required in the FPGA design.

Example 9

According to the satellite signal decoder based on the FPGA, as shown in fig. 5, the satellite signal decoder comprises a plurality of BCH decoding modules;

In the embodiment, by adopting the multi-branch structure, the branches of the BCH and the cascade connection of the LDPC can be disabled or enabled according to the requirements of different tasks on the processing performance, so that the performance flexible scheduling is achieved.

In describing embodiments of the present invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "center", "top", "bottom", "inner", "outer", "inside", "outside", etc. indicate orientations or positional relationships based on the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Wherein "inside" refers to an interior or enclosed area or space. "peripheral" refers to the area surrounding a particular component or region.

In the description of embodiments of the present invention, the terms "first," "second," "third," "fourth" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", "a third" and a fourth "may explicitly or implicitly include one or more such feature. In the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.

In describing embodiments of the present invention, it should be noted that the terms "mounted," "connected," and "assembled" are to be construed broadly, as they may be fixedly connected, detachably connected, or integrally connected, unless otherwise specifically indicated and defined; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.

In the description of embodiments of the invention, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.

Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims

1. The satellite signal encoder is realized based on the FPGA and is characterized by comprising a BCH encoding module and an LDPC encoding module; the output end of the BCH coding module is connected with the input end of the LDPC coding module;

the BCH coding module is used for dividing and shifting an input message sequence to obtain a first coding sequence corresponding to the input message sequence;

2. The FPGA-based satellite signal encoder of claim 1, wherein each BCH encoder comprises three linear feedback shift registers; the satellite signal encoder further includes a first counter control gate and a second counter control gate;

each BCH coding module is used for resetting each register;

3. The FPGA-based satellite signal encoder of claim 2, wherein the LDPC encoding module comprises a linear feedback shift register, a column accumulator buffer, a row processor, an output controller;

4. The FPGA-based satellite signal encoder of claim 3, wherein the LDPC encoding module further comprises a controller; the controller is respectively connected with the column accumulator and the column accumulator buffer;

5. The FPGA-based implemented satellite signal encoder of claim 4, wherein the satellite signal encoder comprises a plurality of the BCH encoding modules;

6. The satellite signal decoder is realized based on the FPGA and is characterized by comprising an LDPC decoding module and a BCH decoding module; the output end of the LDPC decoding module is connected with the input end of the BCH decoding module;

the LDPC decoding module is used for receiving a sequence to be decoded from a preset channel; decoding the sequence to be decoded by utilizing a decoding algorithm based on probability theory to obtain an LDPC decoding result;

7. The FPGA-based satellite signal decoder according to claim 6, wherein said LDPC decoding module comprises a noise scale conversion module, a local oscillation generator, a linear feedback shift register, and a controller;

the local oscillation generator is used for generating a high-frequency signal;

8. The FPGA-based satellite signal decoder of claim 7, wherein in each iteration, the current estimate vector is further phase synchronized by a synchronization signal generated by a local oscillation generator and a linear feedback shift register, and the synchronized current estimate vector is obtained.

9. The FPGA-based satellite signal decoder of claim 8, wherein said BCH decoding module is configured to calculate a comprehensive mismatch operator for said LDPC decoding result; calculating a polynomial through a Berlekamp algorithm; finding the root of the polynomial using the Chein Search algorithm; the root is used for displaying the error code position; and correcting errors according to the error code positions to obtain the final decoding result.

10. The FPGA-based implemented satellite signal decoder of claim 6, wherein said satellite signal decoder includes a plurality of said BCH decoding modules;