CN116545400A - Differential clamp circuit, method for controlling differential clamp circuit, power amplifier and radio frequency system - Google Patents
Differential clamp circuit, method for controlling differential clamp circuit, power amplifier and radio frequency system Download PDFInfo
- Publication number
- CN116545400A CN116545400A CN202310756327.0A CN202310756327A CN116545400A CN 116545400 A CN116545400 A CN 116545400A CN 202310756327 A CN202310756327 A CN 202310756327A CN 116545400 A CN116545400 A CN 116545400A
- Authority
- CN
- China
- Prior art keywords
- differential
- radio frequency
- field effect
- output
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 10
- 230000005669 field effect Effects 0.000 claims description 72
- 239000003990 capacitor Substances 0.000 claims description 26
- 230000000903 blocking effect Effects 0.000 claims description 18
- 230000000087 stabilizing effect Effects 0.000 claims description 17
- 230000009466 transformation Effects 0.000 claims description 6
- 230000003321 amplification Effects 0.000 claims description 4
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 4
- 238000004891 communication Methods 0.000 abstract description 12
- 238000010586 diagram Methods 0.000 description 8
- 230000001276 controlling effect Effects 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 230000000670 limiting effect Effects 0.000 description 3
- 238000010295 mobile communication Methods 0.000 description 3
- 230000008054 signal transmission Effects 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 241001125929 Trisopterus luscus Species 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The invention discloses a differential clamping circuit, a method for controlling the differential clamping circuit, a power amplifier and a radio frequency system, wherein the differential clamping circuit comprises: a clamp module and a differential power amplifier module; the clamping module and the differential power amplifier module adopt symmetrical differential structures; the clamping module is configured to output a clamping signal according to the received first bias voltage and a differential radio frequency input signal with differential symmetry and feed back the clamping signal to the differential power amplifier module; the differential power amplifier module is configured to power amplify a received differential radio frequency input signal in accordance with a received clamp signal to provide an output signal. The invention meets the requirement of 5G communication and simultaneously meets the requirements of 2G and 4G networks by designing the differential clamping circuit, and realizes coexistence of 2G, 4G and 5G.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a differential clamping circuit, a method for controlling the differential clamping circuit, a power amplifier and a radio frequency system.
Background
2G is also called GSM, and has the full name: global System for Mobile Communications Chinese is the Global System for Mobile communications, and the advent of 2G marks the origin of digital communications. For use in different 2G environments, the Power level of the system transmission is automatically adjusted (Random Power) according to the system monitoring.
With the rapid development of fourth-generation and fifth-generation communication, 2G is gradually cooled down, but the 2G demand in the market does not disappear. In the old people in China, a part of groups which only require to call and send short messages and are sensitive to cost for mobile communication services exist. In addition, 2G has been developed in China for 20 years, and has a stronger coverage capacity than 4G by adopting low-frequency signals, and in some special places such as underground garages and remote mountain areas, the 2G network still meets the basic requirements in areas which cannot be covered by the 4G network and the 5G network.
In order to achieve 2G, 4G and 5G, a power amplifier is required to be designed in the rf system to meet the rf output power of 2G and 5G, but the current designs of 2G, 4G and 5G have great differences in the rf power amplifier design.
A single differential power amplifier is difficult to satisfy both the 2G and 4G network requirements and the 5G communication requirements, and therefore, a power amplifier for implementing coexistence of 2G and 4G and 5G communication requirements without adding other modules is needed to solve the above-mentioned problems.
Disclosure of Invention
In order to solve the technical problems, the invention provides a differential clamping circuit, a method for controlling output power of the differential clamping circuit, a power amplifier and a radio frequency system, which realize that the same differential power amplifying module can meet the 5G communication requirement and simultaneously consider the requirements of a 2G network and a 4G network, and realize coexistence of the 2G network, the 4G network and the 5G network.
The aim of the invention is realized by the following technical scheme:
the first aspect of the present invention discloses a differential clamp circuit, comprising: a clamp module and a differential power amplifier module;
the clamping module and the differential power amplifier module adopt symmetrical differential structures;
the clamping module is configured to output a clamping signal according to the received first bias voltage and a differential radio frequency input signal with differential symmetry and feed back the clamping signal to the differential power amplifier module;
the differential power amplifier module is configured to power amplify a received differential radio frequency input signal in accordance with a received clamp signal to provide an output signal.
Specifically, a differential clamp circuit further includes: a balun transformation module;
the balun transformation module includes: a first balun and/or a second balun;
the first balun includes: a single-ended radio frequency input node, a first output node and a second output node; the second balun includes: a single-ended radio frequency output node, a first input node and a second input node;
the first balun transformer is configured to receive a single-ended radio frequency input signal through a single-ended radio frequency input node, and transform the single-ended radio frequency input signal into a differential radio frequency input signal with differential symmetry;
the differential radio frequency input signal comprises: a first differential radio frequency input signal and a second differential radio frequency input signal;
the first differential radio frequency input signal is output to the clamping module and the differential power amplifier module through a first output node;
the second differential radio frequency input signal is output to the clamping module and the differential power amplifier module through a second output node;
the differential power amplifier module performs power amplification on the first differential radio frequency input signal and the second differential radio frequency input signal to provide a first differential radio frequency output signal and a second differential radio frequency output signal;
the second balun transformer is configured to receive the first differential radio frequency output signal through the first input node, to receive the second differential radio frequency output signal through the second input node, to transform the first differential radio frequency output signal and the second differential radio frequency output signal into a single-ended radio frequency output signal and to output the single-ended radio frequency output signal through the single-ended radio frequency output node.
Specifically, the differential power amplifier module includes: the first double-gate field effect transistor and the second double-gate field effect transistor;
the first grid electrode of the first double-grid field effect transistor is coupled with a first output node, the drain electrode of the first double-grid field effect transistor is coupled with a first input node, and the source electrode of the first double-grid field effect transistor is grounded;
the first grid electrode of the second double-grid field effect transistor is coupled with the second output node, the drain electrode of the second double-grid field effect transistor is coupled with the second input node, and the source electrode of the second double-grid field effect transistor is grounded.
Specifically, the clamp module includes: the first bias voltage input node is connected with the first resistor;
the grid electrode of the third field effect transistor is coupled with the first output node, and the grid electrode of the fourth field effect transistor is coupled with the second output node;
the drain electrode of the third field effect transistor and the drain electrode of the fourth field effect transistor are coupled with a first bias voltage input node through a first resistor and output clamping signals to a first grid electrode of the first double-grid field effect transistor and a second grid electrode of the second double-grid field effect transistor;
the source of the third field effect transistor and the source of the fourth field effect transistor are grounded.
Preferably, a differential clamp circuit further comprises: a voltage stabilizing bias module;
the voltage stabilizing bias module comprises: a second bias voltage input node, a third output node, and a fourth output node; the third output node is coupled with the first grid electrode of the first double-grid field effect transistor, and the fourth output node is coupled with the first grid electrode of the second double-grid field effect transistor;
the voltage stabilizing bias module is configured to receive a second bias voltage through a second bias voltage input node, output a first starting voltage to a first grid electrode of the first double-grid field effect transistor through a third output node, and output a second starting voltage to a first grid electrode of the second double-grid field effect transistor through a fourth output node.
Preferably, a differential clamp circuit further comprises: a blocking capacitor;
the blocking capacitor includes: a first blocking capacitor and a second blocking capacitor;
the third output node is coupled to the first output node through a first blocking capacitor, and the fourth output node is coupled to the second output node through a second blocking capacitor.
Preferably, a differential clamp circuit further comprises: a first matching circuit coupled to the second gate of the first double-gate field effect transistor and a second matching circuit coupled to the second gate of the second double-gate field effect transistor;
the first matching circuit includes: a third resistor and a third capacitor connected to each other;
the second matching circuit includes: a fourth resistor and a fourth capacitor connected to each other;
preferably, the differential clamping circuit is characterized in that the third field effect transistor and the fourth field effect transistor are single gate field effect transistors or double gate field effect transistors.
A second aspect of the invention discloses a method of controlling the output power of a differential clamp circuit, comprising:
determining an output power level requirement;
and determining the value of the first bias voltage according to the output power class requirement and inputting the value into the clamping module.
A third aspect of the present invention discloses a differential power amplifier comprising the differential clamping circuit of the first aspect.
A fourth aspect of the invention discloses a radio frequency system comprising the differential power amplifier of the third aspect.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the differential clamping circuit is provided, different first bias voltages are input to the clamping module, the clamping module outputs and feeds back clamping signals to the differential power amplifier module to adjust the power of the output signals amplified by the differential power amplifier module, so that the power of the output signals can not be continuously increased along with the increase of the power of the single-ended radio frequency input signals after the power is increased to required power, the power is stabilized near the required power value, the distortion degree of the differential clamping circuit is reduced, the bandwidth of the circuit is increased, the stability and the linearity of the circuit are improved, and the requirements of 2G and 4G networks are met; the differential power amplifier module is used for amplifying the power of the differential radio frequency input signal, eliminating noise in the differential clamping circuit, improving the reliability and precision of the differential radio frequency input signal and meeting the radio frequency requirement of 5G communication. The differential power amplifier module and the clamping module adopt completely symmetrical differential circuit structures, so that the phase and balance degree of the circuit are ensured, meanwhile, the differential radio frequency input signal meets the differential symmetry, and the anti-interference capability of the differential radio frequency input signal is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a differential clamp circuit according to one embodiment of the present invention;
FIG. 2 is a schematic diagram of a differential clamp circuit according to a second embodiment of the present invention;
FIG. 3 is a third schematic diagram of a differential clamp circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of one of the connections of the differential clamp circuit provided by one embodiment of the present invention;
FIG. 5 is a second schematic diagram of a differential clamp circuit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a clamp module of a differential clamp circuit according to an embodiment of the present invention;
FIG. 7 is a second schematic diagram of a clamp module of a differential clamp circuit according to an embodiment of the present invention;
FIG. 8 is one of the analog simulation schematics of the differential clamp circuit provided by one embodiment of the present invention;
FIG. 9 is a second simulation diagram of a differential clamp circuit according to an embodiment of the present invention.
Detailed Description
The objects, technical solutions and advantages of the present invention will become more apparent by the following detailed description of the present invention with reference to the accompanying drawings. It should be understood that the description is only illustrative and is not intended to limit the scope of the invention. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the present invention.
The following description of the embodiments of the present invention will be made apparent and fully understood from the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be noted that directions or positional relationships indicated as being "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are directions or positional relationships described based on the drawings are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the apparatus or elements to be referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
The existing differential power amplifier module has high power consumption and high cost, and coexistence of 2G, 4G and 5G networks cannot be realized. The invention provides a differential clamping circuit which comprises a clamping module and a differential power amplifier module, wherein the clamping module is used for adjusting the power of a differential radio frequency input signal by feeding back a clamping signal to the differential power amplifier module, and the clamping module is arranged on the premise of not increasing the differential power amplifier module, so that the power amplification of the differential radio frequency input signal is realized, the power design requirement of an output signal is met, and the power of the output signal is maintained near a required power value.
Example 1
As shown in fig. 1, embodiment 1 of the present application provides a differential clamp circuit, which includes a clamp module 1000 and a differential power amplifier module 2000.
The clamp module 1000 is configured to receive the differential radio frequency input signal 10 and the first bias voltage 20, and output the clamp signal 30 for feedback to the differential power amplifier module 2000. The clamp signal 30 output from the clamp module 1000 is output to the differential power amplifier module 2000, so that the maximum output power of the differential power amplifier module 2000 is maintained stable.
The differential power amplifier module 2000 is configured to power amplify the received differential radio frequency input signal 10 in accordance with the received clamp signal 30 to provide a radio frequency output signal 40.
The clamping module 1000 and the differential power amplifier module 2000 adopt symmetrical differential structures, so that the reliability and stability of the circuit are improved, noise and signal interference in the circuit are reduced, and the control of signal gain and linear distortion of the differential radio frequency input signal 10 is realized. The differential radio frequency input signal 10 has differential symmetry, increases the common mode rejection ratio, reduces the interference to ground and errors, and reduces the system noise.
Further, the clamp signal 30 may be accurately expressed as a clamp differential signal 30.
According to the power class requirements of the different single-ended radio frequency output signals 40, a first bias voltage 20 is determined, and the first bias voltage 20 corresponds to the power of the single-ended radio frequency output signal 40, i.e. after the corresponding first bias voltage 20 is selected, the power of the single-ended radio frequency output signal 40 is determined accordingly. Initially, the power of the single-ended radio frequency output signal 40 increases with the power of the differential radio frequency input signal 10; then, after the power of the differential radio frequency input signal 10 increases to a certain value, the power of the single-ended radio frequency output signal 40 does not increase with the increase of the power of the differential radio frequency input signal 10, and is stabilized around the required power point. The clamping module 1000 effectively limits the power of the differential radio frequency input signal 10, improves the stability and reliability of the system, and the differential power amplifying module 2000 amplifies the power of the differential radio frequency input signal 10, and improves the amplitude and frequency response of the signal.
Based on the above structure, when applied in a 2G scenario, the first bias voltage 20 may be determined according to the level requirement of the 2G output power, and the differential power amplifier module 2000 output power may be limited within the 2G requirement by using the clamp module 1000. Therefore, under the condition that the differential power amplifier module is not added, the clamping module 1000 and the differential power amplifier module 2000 are utilized, so that 2G and 4G coexist on the premise of low power consumption and low cost, the output power of 2G and 4G can be enhanced on the premise of not influencing the communication quality of 5G, the transmission distance and coverage range of signals are greatly improved, and the reliability and stability of a network are improved.
Example 2
In practical applications, it is often used to arrange two lines of equal length to achieve differential symmetry of a single-ended radio frequency input signal. Because the capacitance and inductance values between the two lines are different, the impedance is different, so that the balance of signals is influenced, and the wiring mode is easy to be in close contact with other lines, elements and the like, is easy to be influenced by external noise, interference and other factors, so that the anti-interference performance of a single-ended radio frequency input signal is poor, and further, the circuit is abnormal, and the stability of a system is influenced.
Therefore, in the embodiment 2 of the differential clamping circuit provided by the invention, the balun conversion module is added on the basis of the embodiment 1, and comprises the first balun, so that the differential radio frequency input signal meeting the differential symmetry requirement can be obtained by simply inputting the single-ended radio frequency input signal to the input end of the first balun, complicated wiring design and optimization are not needed, the precision of the differential radio frequency output signal is greatly improved, and the stability and reliability of signal transmission are ensured.
As shown in fig. 2, the balun transformation module 3000 includes a first balun transformer 100, where the first balun transformer 100 can transform a single-ended input signal 5 into two differential radio frequency input signals 10 with equal magnitudes and 180 ° phase difference; the differential radio frequency input signal 10 comprises a first differential radio frequency input signal 11 and a second differential radio frequency input signal 12, the first differential radio frequency input signal 11 being input to the clamping module 1000 and the differential power amplifier module 2000, the second differential radio frequency input signal 12 being input to the clamping module 1000 and the differential power amplifier module 2000. The differential power amplifier module 2000 power amplifies the received first and second differential radio frequency input signals 11, 12 according to the received clamp signal 30 to provide first and second differential radio frequency output signals 13, 14.
Preferably, the balun transformer module 3000 further comprises a second balun transformer 200. The second balun transformer 200 is configured to transform the received first and second differential radio frequency output signals 13 and 14 into a single-ended radio frequency output signal 40 and output, improving the transmission quality of the signals. The second balun transformer 200 may be configured according to the structure of a subsequent circuit or device.
In the aspect of signal transmission, the differential symmetry of the differential radio frequency input signal 10 is ensured by combining the first balun transformer 100, the differential power amplifying module 2000 and the clamping module 1000, and the quality of signal transmission is improved; in the aspect of signal reception, the second balun transformer 200 is utilized to avoid the problems of distortion, large noise and the like of the single-ended radio frequency output signal 40, realize the protection of the signal and improve the reliability of the circuit.
Example 3
The differential power amplifier module needs a bias module to supply power in use, the current bias module uses a plurality of external components, the output of the starting voltage can be realized only by virtue of a plurality of resistors and capacitors matched with loads, the debugging difficulty and cost of the circuit are increased, and the output starting voltage is easily influenced by environment and has poor stability.
Therefore, the invention provides an embodiment 3 of a differential clamping circuit, and a voltage stabilizing bias module is added on the basis of embodiments 1 and 2, so that the differential power amplifier module can be started quickly, the operation gain of differential signals is improved, and the stability of the circuit is ensured.
As shown in fig. 3, the voltage stabilizing bias module 4000 is configured to receive the second bias voltage 50, and output the first turn-on voltage 60 and the second turn-on voltage 70 to turn on the differential power amplifier module 2000, so that the differential power amplifier module 2000 can be quickly started, the operation gain of the differential signal is improved, and the stability of the circuit is ensured.
Further, the voltage stabilizing bias module 4000 includes a bias circuit provided with a diode and a second resistor. The bias circuit is configured to receive the second bias voltage 50 through the second bias voltage input node 61, output the first turn-on voltage 60 to the first gate of the first dual-gate fet Q1 through the third output node 62 to turn on the first dual-gate fet Q1, and output the second turn-on voltage 70 to the first gate of the second dual-gate fet Q2 through the fourth output node 63 to turn on the second dual-gate fet Q2 after the diode voltage stabilizing and the second resistor voltage dividing operations. The bias circuit consists of a diode and a resistor, has a simple structure and low cost, has certain anti-interference capability, and greatly improves the stability and reliability of the differential clamping circuit.
Example 4
The differential power amplifier module 2000, the clamp module 1000, and the voltage stabilizing bias module 4000 may select appropriate devices as needed. Embodiment 4 of the present invention describes in detail a specific device of the differential clamp circuit.
As shown in fig. 3, 4 and 6, the balun module 3000 includes a first balun transformer 100 and a second balun transformer 200. The first balun 100 comprises a single-ended radio frequency input node 31, a first output node 15 and a second output node 16; the second balun 200 comprises a single-ended radio frequency output node 32, a first input node 17 and a second input node 18.
The differential power amplifier module 2000 includes a first dual-gate fet Q1 and a second dual-gate fet Q2. The first grid electrode of the first double-grid field effect transistor Q1 is coupled with the first output node 15, the drain electrode is coupled with the first input node 17, and the source electrode is grounded; the second double gate field effect transistor Q2 has a first gate coupled to the second output node 16, a drain coupled to the second input node 18, and a source coupled to ground.
The clamp module 1000 includes a third fet Q3, a fourth fet Q4, a first bias voltage input node 21, and a first resistor 22. The grid electrode of the third field effect transistor Q3 is coupled with the first output node 15, and the grid electrode of the fourth field effect transistor Q4 is coupled with the second output node 16; the drain electrode of the third field effect transistor Q3 and the drain electrode of the fourth field effect transistor Q4 are coupled together through a first resistor 22 and a first bias voltage input node 21, and a clamping signal 30 is output to the second grid electrode of the first double-grid field effect transistor Q1 and the second grid electrode of the second double-grid field effect transistor Q2; the source of the third fet Q3 and the source of the fourth fet Q4 are grounded.
The regulated bias module 4000 includes a second bias voltage input node 61, a third output node 62, and a fourth output node 63. The third output node 62 is coupled to the first gate of the first double gate field effect transistor and the fourth output node 63 is coupled to the second gate of the second double gate field effect transistor.
The single-ended radio frequency input signal 5 with a certain power is input into the first balun transformer 100 through the single-ended radio frequency input node 31, and is transformed into a first differential radio frequency input signal 11 and a second differential radio frequency input signal 12 with equal size and 180 DEG phase difference through the impedance transformation of the first balun transformer 100. The first differential rf input signal 11 is input to the first gate of the first dual-gate fet Q1 and the gate of the third fet Q3 via the first output node 15, and the second differential rf input signal 12 is input to the first gate of the second dual-gate fet Q2 and the gate of the fourth fet Q4 via the second output node 16.
Given the second bias voltage 50 through the second bias voltage input node 61, the voltage stabilizing bias module 4000 outputs a first turn-on voltage to the first gate of the first dual-gate fet Q1 through the third output node 62 to turn on the first gate of the first dual-gate fet Q1, and outputs a second turn-on voltage to the first gate of the second dual-gate fet Q2 through the fourth output node 63 to turn on the first gate of the second dual-gate fet Q2.
The first and second double gate field effect transistors Q1 and Q2 power-amplify the first and second differential radio frequency input signals 11 and 12, respectively, to provide first and second differential radio frequency output signals 13 and 14. The first differential rf output signal 13 and the second differential rf output signal 14 are input to the second balun 200 via the first input node 17 and the second input node 18, respectively, impedance-transformed by the second balun 200, and output the single-ended rf output signal 40 via the single-ended rf output node 32.
As the power of the single-ended rf input signal 5 increases, so does the power to the clamp module 1000 and the differential power amplifier module 2000, the power of the single-ended rf output signal 40. When the power of the single-ended rf input signal 5 increases to a certain value, the first differential rf input signal 11 and the second differential rf input signal 12 cause the gate of the third fet Q3 and the gate of the fourth fet Q4 to open, at which time the first bias voltage 20 corresponding to the power level of the single-ended rf output signal 40 is given by the first bias voltage input node 21, the current flowing through the first resistor 22 increases, the voltage of the first resistor 22 increases, and the voltage value of the clamp signal 30 decreases. The clamp signal 30 is fed back to the gate of the first dual-gate fet Q1 and the gate of the second dual-gate fet Q2 such that the gate voltage of the first dual-gate fet Q1 and the gate voltage of the second dual-gate fet Q2 are reduced, resulting in a reduction in the power of the single-ended rf output signal 40 of the differential power amplifier module 2000. Therefore, a stable loop is formed, and even if the power of the single-ended rf input signal 5 increases again, the power of the single-ended rf output signal 40 is still stable near the required power value, so that the network requirements of 2G and 4G are satisfied while 5G communication is satisfied.
Preferably, the differential clamp circuit further includes a first matching circuit coupled to the second gate of the first dual-gate fet Q1 and a second matching circuit coupled to the second gate of the second dual-gate fet Q2.
The first matching circuit comprises a third resistor and a third capacitor, and the third resistor is connected with the third capacitor; the second matching circuit comprises a fourth resistor and a fourth capacitor, and the fourth resistor is connected with the fourth capacitor. The second grid electrode of the first double-grid field effect tube Q1 is coupled with the first matching circuit, the second grid electrode of the second double-grid field effect tube Q2 is coupled with the second matching circuit, adjustment and optimization of amplification factors of the first double-grid field effect tube Q1 and the second double-grid field effect tube Q2 are achieved, noise interference of the second grid electrode to the first grid electrode under abnormal conditions is avoided, and stability and linearity of the differential clamping circuit are improved.
Preferably, the third fet Q3 and the fourth fet Q4 in the clamping module 1000 may be single gate fets (shown in fig. 6) or double gate fets, as shown in fig. 7, and the third fet Q5 and the fourth fet Q6 may be double gate fets. The double-gate field effect transistor is added with the second gate on the basis of the single-gate field effect transistor, has a certain shielding effect, enables the feedback capacitance between the drain electrode and the first gate to be very small, and further improves the stability of the differential clamping circuit.
Example 5
Since the first gate of the first double-gate fet Q1 and the gate of the third fet Q3 are both coupled to the first output node 15, the third output node 62 of the voltage stabilizing bias module 4000 is coupled to the first gate of the first double-gate fet Q1; the first grid electrode of the second double-grid field effect transistor Q2 and the grid electrode of the fourth field effect transistor Q4 are both coupled with the second output node 16, and the fourth output node 63 of the voltage stabilizing bias module 4000 is coupled with the first grid electrode of the second double-grid field effect transistor Q2; the voltage stabilizing bias module 4000 and the clamping module 1000 form a loop, and the first turn-on voltage 60 and the second turn-on voltage 70 of the voltage stabilizing bias module 4000 affect the clamping signal 30 of the clamping module 1000, so that the power of the single-ended rf output signal 40 of the differential power amplifier module 3000 is affected by the second bias voltage 50.
Therefore, in embodiment 5 of the differential clamping circuit provided by the invention, a blocking capacitor is added on the basis of embodiment 3 so as to reduce the interference of direct current voltage to the differential clamping circuit.
As shown in fig. 5, the third output node 62 is coupled to the first output node 15 via a first blocking capacitor 71 and the fourth output node 63 is coupled to the second output node 16 via a second blocking capacitor 72. The first blocking capacitor 71 and the second blocking capacitor 72 play a role in blocking direct current and alternating current, eliminate direct current components and noise in the loops of the voltage stabilizing bias module 4000 and the clamp module 1000, and simultaneously ensure that the static working point of the whole differential clamp circuit is biased to a correct position.
As shown in fig. 8 and 9, the horizontal axis Pin represents the power of the single-ended rf input signal 5, the vertical axis Pout represents the power of the single-ended rf output signal 40, dBm represents the magnitude of the power, and Bias represents the first Bias voltage.
As shown in fig. 8, the power of the single-ended rf output signal 40 increases with the power of the single-ended rf input signal 5, which satisfies the communication requirement of 5G, but cannot satisfy the network requirements of 2G and 4G.
As shown in fig. 9, the simulation result of the differential clamping circuit in the present invention shows that when the first bias voltage 20 is 0.1V, the final power of the single-ended rf output signal 40 is 15dBm; when the first bias voltage 20 is 0.2V, the final power of the single-ended rf output signal 40 is 20dBm; when the first bias voltage 20 is 0.5V, the final power of the single-ended rf output signal 40 is 25dBm; when the first bias voltage 20 is 0.9V, the final power of the single-ended rf output signal 40 is 30dBm; when the first bias voltage 20 is 1.5V, the final power of the single-ended rf output signal 40 is 35dBm.
At the different first bias voltages 20, when the power of the single-ended radio frequency input signal 5 is less than 15dBm, the power of the single-ended radio frequency output signal 40 increases with the increase of the power of the single-ended radio frequency input signal 5; when the power of the single-ended rf input signal 5 is greater than 15dBm, the power of the single-ended rf output signal 40 is not increased with the increase of the power of the single-ended rf input signal 5, and is maintained near the required power value, so that the stability and linearity of the circuit are improved, and the coexistence of 2G and 4G is realized while the 5G communication requirement is satisfied.
Based on the circuit structure, the application also discloses a method for controlling the output power of the differential clamping circuit, which comprises the steps of determining the requirement of the output power grade, determining the value of the first bias voltage according to the requirement of the output power grade, inputting the value into the clamping module, effectively controlling the output power of the differential clamping circuit, adapting to the requirements of different output power grades, and simultaneously adjusting the first bias voltage to improve the performance and the stability of the circuit.
Specifically, when the above-described circuit needs to be applied in a 2G environment, the clamp module may be enabled to exert a power limiting effect. The value of the first bias voltage needs to be determined according to the output power class requirement of 2G and input to the clamping module so as to effectively control the output power of the differential clamping circuit. The first bias voltage may be selected to be 1.5V when the output power requirement is 35dBm.
Based on the circuit structure, the application also discloses a differential power amplifier which comprises the differential clamping circuit in the embodiment, effectively amplifies the radio frequency input signal, outputs a radio frequency output signal more stably and accurately, and ensures the transmission quality of the radio frequency signal.
Based on the circuit structure, the application also discloses a radio frequency system, which comprises the differential power amplifier, has high-precision, stable and reliable performance, and improves the sensitivity and coordination of the system.
It is to be understood that the above-described embodiments of the present invention are merely illustrative of or explanation of the principles of the present invention and are in no way limiting of the invention. Accordingly, any modification, equivalent replacement, improvement, etc. made without departing from the spirit and scope of the present invention should be included in the scope of the present invention. Furthermore, the appended claims are intended to cover all such changes and modifications that fall within the scope and boundary of the appended claims, or equivalents of such scope and boundary.
Claims (11)
1. A differential clamp circuit, comprising: a clamp module and a differential power amplifier module;
the clamping module and the differential power amplifier module are both in symmetrical differential structures;
the clamping module is configured to output a clamping signal according to the received first bias voltage and a differential radio frequency input signal with differential symmetry and feed back the clamping signal to the differential power amplifier module;
the differential power amplifier module is configured to power amplify the received differential radio frequency input signal in accordance with the received clamp signal to provide an output signal.
2. The differential clamp circuit of claim 1, further comprising: a balun transformation module;
the balun transformation module includes: a first balun and/or a second balun;
the first balun includes: a single-ended radio frequency input node, a first output node and a second output node; the second balun includes: a single-ended radio frequency output node, a first input node and a second input node;
the first balun transformer is configured to receive a single-ended radio frequency input signal through the single-ended radio frequency input node, transform the single-ended radio frequency input signal into the differential radio frequency input signal having differential symmetry;
the differential radio frequency input signal comprises: a first differential radio frequency input signal and a second differential radio frequency input signal;
the first differential radio frequency input signal is output to the clamping module and the differential power amplifier module through the first output node;
the second differential radio frequency input signal is output to the clamping module and the differential power amplifier module through the second output node;
the differential power amplifier module performs power amplification on the first differential radio frequency input signal and the second differential radio frequency input signal to provide a first differential radio frequency output signal and a second differential radio frequency output signal;
the second balun transformer is configured to receive the first differential radio frequency output signal through the first input node, receive the second differential radio frequency output signal through the second input node, transform the first differential radio frequency output signal and the second differential radio frequency output signal into a single-ended radio frequency output signal and output through the single-ended radio frequency output node.
3. The differential clamp circuit of claim 2, wherein the differential power amplifier module comprises: the first double-gate field effect transistor and the second double-gate field effect transistor;
the first grid electrode of the first double-grid field effect transistor is coupled with the first output node, the drain electrode of the first double-grid field effect transistor is coupled with the first input node, and the source electrode of the first double-grid field effect transistor is grounded;
the first grid electrode of the second double-grid field effect transistor is coupled with the second output node, the drain electrode of the second double-grid field effect transistor is coupled with the second input node, and the source electrode of the second double-grid field effect transistor is grounded.
4. The differential clamp circuit of claim 3, wherein the clamp module comprises: the first bias voltage input node is connected with the first resistor;
the grid electrode of the third field effect transistor is coupled with the first output node, and the grid electrode of the fourth field effect transistor is coupled with the second output node;
the drain electrode of the third field effect transistor and the drain electrode of the fourth field effect transistor are coupled with the first bias voltage input node through the first resistor and output the clamping signal to the first grid electrode of the first double-grid field effect transistor and the second grid electrode of the second double-grid field effect transistor;
and the source electrode of the third field effect transistor and the source electrode of the fourth field effect transistor are grounded.
5. The differential clamp circuit of claim 3, further comprising: a voltage stabilizing bias module;
the voltage stabilizing bias module comprises: a second bias voltage input node, a third output node, and a fourth output node; the third output node is coupled with the first gate of the first double-gate field effect transistor, and the fourth output node is coupled with the first gate of the second double-gate field effect transistor;
the voltage stabilizing bias module is configured to receive a second bias voltage through the second bias voltage input node, output a first starting voltage to the first grid electrode of the first double-grid field effect transistor through the third output node, and output a second starting voltage to the first grid electrode of the second double-grid field effect transistor through the fourth output node.
6. The differential clamp circuit of claim 5, further comprising: a blocking capacitor;
the blocking capacitor includes: a first blocking capacitor and a second blocking capacitor;
the third output node is coupled to the first output node through the first blocking capacitor, and the fourth output node is coupled to the second output node through the second blocking capacitor.
7. The differential clamp circuit of claim 6, further comprising: a first matching circuit coupled to the second gate of the first double-gate field effect transistor and a second matching circuit coupled to the second gate of the second double-gate field effect transistor;
the first matching circuit includes: a third resistor and a third capacitor connected to each other;
the second matching circuit includes: and a fourth resistor and a fourth capacitor connected.
8. The differential clamp circuit of claim 4, wherein the third field effect transistor and the fourth field effect transistor are single gate field effect transistors or double gate field effect transistors.
9. A method of controlling the output power of a differential clamp circuit for use in a differential clamp circuit as claimed in any one of claims 1 to 8, the method comprising:
determining an output power level requirement;
and determining the value of the first bias voltage according to the output power grade requirement and inputting the value to the clamping module.
10. A differential power amplifier comprising the differential clamp circuit of any one of claims 1-8.
11. A radio frequency system comprising the differential power amplifier of claim 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310756327.0A CN116545400B (en) | 2023-06-26 | 2023-06-26 | Differential clamp circuit, method for controlling differential clamp circuit, power amplifier and radio frequency system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310756327.0A CN116545400B (en) | 2023-06-26 | 2023-06-26 | Differential clamp circuit, method for controlling differential clamp circuit, power amplifier and radio frequency system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116545400A true CN116545400A (en) | 2023-08-04 |
| CN116545400B CN116545400B (en) | 2023-12-19 |
Family
ID=87452736
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310756327.0A Active CN116545400B (en) | 2023-06-26 | 2023-06-26 | Differential clamp circuit, method for controlling differential clamp circuit, power amplifier and radio frequency system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116545400B (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030114129A1 (en) * | 2001-12-17 | 2003-06-19 | Jerng Albert C. | System and method for a radio frequency receiver front end utilizing a balun to couple a low-noise amplifier to a mixer |
| US20160336921A1 (en) * | 2015-05-13 | 2016-11-17 | Qualcomm Incorporated | Active balun for wideband applications |
| CN106452377A (en) * | 2016-09-29 | 2017-02-22 | 锐迪科微电子（上海）有限公司 | Self-adaptively compensated radio-frequency power amplifier |
| CN108352816A (en) * | 2015-10-27 | 2018-07-31 | 瑞典爱立信有限公司 | Distributed power amplifier |
| CN111262536A (en) * | 2020-04-02 | 2020-06-09 | 中国地震局地质研究所 | Ultrasonic guided wave broadband linear power amplifying device |
| CN215990714U (en) * | 2021-09-27 | 2022-03-08 | 深圳飞骧科技股份有限公司 | Radio frequency power amplifier and radio frequency front end architecture applied to 5G communication system |
| CN115580241A (en) * | 2022-12-09 | 2023-01-06 | 三微电子科技(苏州)有限公司 | Power amplifier and bias circuit thereof |
| WO2023078056A1 (en) * | 2021-11-05 | 2023-05-11 | 深圳飞骧科技股份有限公司 | High-efficiency radio frequency power amplifier |
-
2023
- 2023-06-26 CN CN202310756327.0A patent/CN116545400B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030114129A1 (en) * | 2001-12-17 | 2003-06-19 | Jerng Albert C. | System and method for a radio frequency receiver front end utilizing a balun to couple a low-noise amplifier to a mixer |
| US20160336921A1 (en) * | 2015-05-13 | 2016-11-17 | Qualcomm Incorporated | Active balun for wideband applications |
| CN108352816A (en) * | 2015-10-27 | 2018-07-31 | 瑞典爱立信有限公司 | Distributed power amplifier |
| CN106452377A (en) * | 2016-09-29 | 2017-02-22 | 锐迪科微电子（上海）有限公司 | Self-adaptively compensated radio-frequency power amplifier |
| CN111262536A (en) * | 2020-04-02 | 2020-06-09 | 中国地震局地质研究所 | Ultrasonic guided wave broadband linear power amplifying device |
| CN215990714U (en) * | 2021-09-27 | 2022-03-08 | 深圳飞骧科技股份有限公司 | Radio frequency power amplifier and radio frequency front end architecture applied to 5G communication system |
| WO2023078056A1 (en) * | 2021-11-05 | 2023-05-11 | 深圳飞骧科技股份有限公司 | High-efficiency radio frequency power amplifier |
| CN115580241A (en) * | 2022-12-09 | 2023-01-06 | 三微电子科技(苏州)有限公司 | Power amplifier and bias circuit thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116545400B (en) | 2023-12-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107332517B (en) | High-linearity broadband stacked low-noise amplifier based on gain compensation technology | |
| CN102497167B (en) | Radio-frequency ultra-wideband low-noise amplifier based on inductance compensation | |
| CN103248324A (en) | High-linearity low-noise amplifier | |
| CN108574464B (en) | Low-power-consumption high-linearity dual-mode millimeter wave broadband stacked low-noise amplifier | |
| WO2023082933A1 (en) | Radio frequency power amplifier | |
| CN209330069U (en) | A kind of active biased Cascode radio frequency amplifier | |
| US20120218041A1 (en) | Amplifier circuit | |
| CN103401514A (en) | Low-noise amplifier | |
| WO2023045283A1 (en) | Low-phase shift variable gain amplifier and radio frequency signal processing method | |
| US11533031B2 (en) | Amplifier, amplification circuit and phase shifter | |
| Heaney et al. | Ultra low power low noise amplifiers for wireless communications | |
| CN108900167B (en) | Impedance compensation circuit and power amplification compensation circuit | |
| CN111313844A (en) | Self-adaptive bias circuit applied to low-noise amplifier chip | |
| US10256781B2 (en) | Complementary metal oxide silicon transceiver having integrated power amplifier | |
| CN102647157A (en) | Single-ended input differential output type radio frequency low-noise amplifier | |
| CN102332877A (en) | Differential complementary metal oxide semiconductor (CMOS) multimode low-noise amplifier with on-chip active Balun | |
| CN105720938A (en) | dB linear ultra-wideband variable gain amplifier | |
| KR101590605B1 (en) | Linear power amplifier for wireless transmitter | |
| CN103281038A (en) | Wideband low noise amplifier | |
| CN103916084A (en) | Gain adjustable low noise amplifier circuit | |
| CN211579935U (en) | Self-adaptive bias circuit applied to low-noise amplifier chip | |
| CN116545400B (en) | Differential clamp circuit, method for controlling differential clamp circuit, power amplifier and radio frequency system | |
| CN114070215A (en) | Power amplifier, power amplifier system and operation method thereof | |
| US7944308B2 (en) | Amplifier circuit and the controlling method thereof | |
| US8994451B1 (en) | RF amplifier |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |