CN116545260A - DC-DC converter, chip and electronic equipment - Google Patents
DC-DC converter, chip and electronic equipment Download PDFInfo
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- CN116545260A CN116545260A CN202310532741.3A CN202310532741A CN116545260A CN 116545260 A CN116545260 A CN 116545260A CN 202310532741 A CN202310532741 A CN 202310532741A CN 116545260 A CN116545260 A CN 116545260A
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The present disclosure provides a DC-DC converter, a chip and an electronic device, including: a load adjustment rate correction circuit, an error amplifier circuit, a duty cycle modulation circuit, and a power stage circuit; the load adjustment rate correction circuit generates an offset correction voltage according to the first reference voltage and the output end voltage of the error amplifier circuit, and voltage drops the first input voltage according to the offset correction voltage so as to generate a second input voltage and provide the second input voltage for the error amplifier circuit; the error amplifier circuit provides output end voltages of the error amplifier circuit for the load adjustment rate correction circuit and the duty ratio modulation circuit according to the second reference voltage and the second input voltage; the duty ratio modulation circuit generates a control signal based on a current source controlled by upper tube current in the power stage circuit and the output end voltage of the error amplifier circuit; the power stage circuit controls the switches of an upper pipe and a lower pipe in the power stage circuit according to the clock signal and the control signal, and generates output voltage.
Description
Cross Reference to Related Applications
The present application claims the benefit of italian patent application No.102022000001883 filed 2, 3, 2022, which is incorporated herein by reference.
Technical Field
The present description relates generally to electronic circuits and systems, and more particularly to buck-boost refresh circuits.
Background
When the desired output voltage V out Very close to the converter input voltage Vin, the pure buck DC-DC converter and the pure boost DC-DC converter may not operate properly because in this case the duty cycle of the Pulse Width Modulated (PWM) signal driving the commutation of the transfer switching stage tends to be close to 1 (or equivalently, 100%). In this case, a driver circuit that drives the switching elements of the converter is required to operate at a fast pace, which is often not achievable in conventional converters.
The non-inverting buck-boost DC-DC converter is a type of DC-DC converter that relies on a full bridge switching architecture and can produce an output voltage V out The output voltage V out May also be equal to the value of the converter input voltage Vin (V out ≈V in )。
The buck-boost converter may be driven to operate in either a pure buck mode or a pure boost mode if the application requires it. In the case of a full-bridge switching architecture comprising only n-channel metal oxide semiconductor (NMOS) transistors (i.e. a full-bridge architecture in which the high-side switch is also implemented as an NMOS transistor), the operation of the converter may rely on providing two dedicated bootstrap circuits configured to supply the driver circuit driving the high-side switch through an external capacitance of stored energy when each power half-bridge circuit is switching.
The bootstrap circuit may also include a bootstrap voltage refresh circuit that is capable of providing energy to the inactive (i.e., non-switching) half-bridge circuit when the converter is operating in either a pure buck mode or a pure boost mode. According to some known solutions, the refresh circuitry may become complex, occupy a large silicon area and/or have low efficiency.
Accordingly, there is a need in the art to provide buck-boost DC-DC converters that include improved bootstrap voltage refresh circuits.
Disclosure of Invention
One or more embodiments may relate to a corresponding method of operating a buck-boost DC-DC converter.
In one or more embodiments, a buck-boost converter circuit includes an input node configured to receive an input voltage and an output node configured to provide an output voltage. The converter includes a first half-bridge circuit disposed between an input node and a ground node, the first half-bridge circuit including a first high-side switch disposed between the input node and a first switch node, and a first low-side switch disposed between the first switch node and the ground node. The converter includes a second half-bridge circuit disposed between the output node and the ground node, the second half-bridge circuit including a second high-side switch disposed between the output node and the second switch node, and a second low-side switch disposed between the second switch node and the ground node. The converter includes a control circuit configured to receive a first control signal and a second control signal, the first control signal indicating a buck-boost converter circuit operating in a buck mode if the first control signal is asserted, the second control signal indicating a buck-boost converter circuit operating in a boost mode if the second control signal is asserted, the control circuit further configured to generate a buck pulse width modulated control signal and a boost pulse width modulated control signal. The converter includes a first high-side driver circuit configured to receive the buck pulse-width modulation control signal and to drive the first high-side switch in accordance with the buck pulse-width modulation control signal. The first high-side driver circuit is biased between a first high-side supply voltage node and a first switching node. The converter includes a second high-side driver circuit configured to receive the boost pulse width modulation control signal and drive the second high-side switch in accordance with the boost pulse width modulation control signal. The second high-side driver circuit is biased between a second high-side supply voltage node and a second switching node. The first bootstrap circuit is configured to selectively conduct from the reference voltage node toward the first high-side supply voltage node, and the second bootstrap circuit is configured to selectively conduct from the reference voltage node toward the second high-side supply voltage node. The first voltage sensing circuit is configured to sense a voltage between the first high-side supply voltage node and the first switch node and assert a first activation signal in response to the sensed voltage being below a first threshold. The second voltage sensing circuit is configured to sense a voltage between the second high-side supply voltage node and the second switching node and assert a second activation signal in response to the sensed voltage being below a second threshold. At least one charge transfer switch is directly connected between the first high side supply voltage node and the second high side supply voltage node. The converter includes a bootstrap refresh control circuit configured to close the at least one charge transfer switch in response to:
i) The first control signal is asserted, the first high-side switch is turned on and the second activation signal is asserted; or alternatively
ii) the second control signal is asserted, the second high side switch is turned on and the first activation signal is asserted.
Accordingly, one or more embodiments may provide a buck-boost DC-DC converter including a bootstrap voltage refresh circuit that is simple, occupies a small silicon area, and/or has improved efficiency.
In one or more embodiments, the first high-side switch, the first low-side switch, the second high-side switch, and the second low-side switch comprise n-channel MOS transistors.
In one or more embodiments, the at least one charge transfer switch includes at least one p-channel MOS transistor.
In one or more embodiments, the at least one charge transfer switch includes a first charge transfer switch directly connected between the intermediate node of the charge transfer path and a first high-side supply voltage node, and a second charge transfer switch directly connected between the intermediate node of the charge transfer path and a second high-side supply voltage node.
In one or more embodiments, the at least one charge transfer switch includes at least one switch having a variable resistance value. The bootstrap refresher control circuit is further configured to determine a voltage difference between the first high-side supply voltage node and the second high-side supply voltage node, and a resistance value of the at least one charge transfer switch is set in accordance with the determined voltage difference. A higher resistance value of the at least one charge transfer switch is set in response to the determined higher value of the voltage difference.
In one or more embodiments, the at least one charge transfer switch includes a plurality of selectively activatable switches connected in parallel. The bootstrap refresh control circuit is configured to generate a respective control signal for activating the selectively activatable switches connected in parallel in accordance with the determined voltage difference. A fewer number of parallel connected switches are activated in response to a higher value of the determined voltage difference.
In one or more embodiments, the bootstrap refresh control circuitry is configured to determine a voltage difference between the first high-side supply voltage node and the second high-side supply voltage node as a difference between the input voltage and the output voltage.
In one or more embodiments, the bootstrap refresher control circuit is configured to determine the voltage difference between the first high-side supply voltage node and the second high-side supply voltage node as a function of the output voltage and at least one of a duty cycle of the buck pulse width modulation control signal and a duty cycle of the boost pulse width modulation control signal.
In one or more embodiments, the first voltage sensing circuit includes: a first voltage-to-current converter circuit configured to generate a first output current indicative of a voltage between the first high-side supply voltage node and the first switching node; a first resistor coupled to the ground node and arranged to receive the first output current to generate a first voltage signal indicative of a voltage between the first high-side supply voltage node and the first switch node; and a first comparator configured to compare the first voltage signal with the first threshold and assert the first activation signal in response to the first voltage signal being below the first threshold. The second voltage sensing circuit includes: a second voltage-to-current converter circuit configured to generate a second output current indicative of a voltage between the second high-side supply voltage node and the second switching node; a second resistor coupled to the ground node and arranged to receive the second output current to generate a second voltage signal indicative of a voltage between the second high-side supply voltage node and the second switch node; and a second comparator configured to compare the second voltage signal to the second threshold and assert the second activation signal in response to the second voltage signal being below the second threshold.
In one or more embodiments, the first bootstrap circuit includes a semiconductor junction (e.g., diode-connected transistor, etc.) having an anode terminal coupled to the reference voltage node and a cathode terminal coupled to the first high-side supply voltage node. The second bootstrap circuit includes a semiconductor junction (e.g., diode-connected transistor, etc.) having an anode terminal coupled to the reference voltage node and a cathode terminal coupled to the second high-side supply voltage node.
In one or more embodiments, the first bootstrap circuit includes a first bootstrap switch disposed between the reference voltage node and the first high-side supply voltage node, and the second bootstrap circuit includes a second bootstrap switch disposed between the reference voltage node and the second high-side supply voltage node. The circuit includes a control circuit configured to close the first bootstrap switch in response to the first low-side switch being on and the first high-side switch not being on, and to close the second bootstrap switch in response to the second low-side switch being on and the second high-side switch not being on.
In one or more embodiments, a method of operating a buck-boost converter circuit includes receiving an input voltage at an input node. The method includes receiving a first control signal and a second control signal at the control circuit, indicating the buck-boost converter circuit operating in a buck mode if the first control signal is asserted, and indicating the buck-boost converter circuit operating in a boost mode if the second control signal is asserted. The method includes generating a buck pulse width modulation control signal and a boost pulse width modulation control signal at a control circuit. The method includes receiving a buck pulse width modulation control signal at a first high-side driver circuit and driving a first high-side switch according to the buck pulse width modulation control signal. The method includes receiving the boost pulse width modulation control signal at the second high side driver circuit and driving the second high side switch in accordance with the boost pulse width modulation control signal. The method includes sensing, at a first voltage sensing circuit, a voltage between a first high-side supply voltage node and a first switching node, and asserting a first activation signal in response to the sensed voltage being below a first threshold. The method includes sensing, at a second voltage sensing circuit, a voltage between a second high-side supply voltage node and a second switching node, and asserting a second activation signal in response to the sensed voltage being below a second threshold. The method includes closing the at least one charge transfer switch in response to:
i) The first control signal is asserted, the first high-side switch is turned on and the second activation signal is asserted, or
ii) the second control signal is asserted, the second high side switch is turned on and the first activation signal is asserted.
Drawings
One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:
FIG. 1 is a circuit diagram of an exemplary non-inverting buck-boost DC-DC converter;
FIG. 2 is an exemplary timing diagram of possible behavior of buck and boost PWM control signals and inductor current in a buck-boost DC-DC converter operating in a buck-boost mode;
FIG. 3 is an exemplary timing diagram of possible behavior of buck PWM control signals and inductor current in a buck-boost DC-DC converter operating in buck mode;
FIG. 4 is an exemplary timing diagram of possible behavior of the boost PWM control signal and the inductor current in a buck-boost DC-DC converter operating in a boost mode;
FIG. 5 is an exemplary circuit diagram of a buck-boost DC-DC converter of an exemplary buck-boost DC-DC powered bootstrap circuit;
FIG. 6 is an exemplary timing diagram of possible behavior of the power supply voltage of the high side buck driver circuit in the DC-DC converter of FIG. 5 when the operation of the DC-DC converter is converted from buck mode or buck-boost mode to boost mode;
FIG. 7 is an exemplary timing diagram of possible behavior of the power supply voltage of the high side boost driver circuit in the DC-DC converter of FIG. 5 when the operation of the DC-DC converter is converted from boost mode or buck-boost mode to buck mode;
FIG. 8 is an exemplary circuit diagram of a buck-boost DC-DC converter including a steering circuit configured to supply a high-side driver circuit and a steering refresh circuit in accordance with one or more embodiments of the present invention;
FIG. 9 is an exemplary circuit diagram of implementation details of a buck-boost DC-DC converter according to one or more embodiments of the present disclosure; and
fig. 10 is an exemplary block diagram of a possible operation of a buck-boost DC-DC converter according to one or more embodiments of the present description.
Detailed Description
In the following description, one or more specific details are set forth in order to provide a thorough understanding of examples of the embodiments described herein. Embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.
References in the framework of this specification to "an embodiment" or "one embodiment" are intended to indicate that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in one embodiment" that may occur in one or more points of the present specification do not necessarily refer to the same embodiment. Furthermore, the particular configurations, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
The headings/reference numerals used herein are provided for convenience only and thus do not limit the scope of protection or the scope of the embodiments.
In the drawings attached hereto, identical parts or elements are denoted by identical reference numerals/numerals unless the context indicates otherwise, and the corresponding description will not be repeated for the sake of brevity.
By introducing a detailed description of the exemplary embodiments, and referring first to fig. 1, fig. 1 is a circuit diagram of an exemplary buck-boost DC-DC converter 10.
The converter 10 comprises a converter arranged to provide an input voltage V in And provides a reference (or ground) voltage V gnd A first half-bridge circuit (e.g., a buck half-bridge) between reference (or ground) nodes 104. The first half-bridge circuit comprises a first high-side switch HS1 arranged between the input node 102 and a first intermediate (switch) node 106, and a first low-side switch LS1 arranged between the intermediate node 106 and a reference node 104. The high-side switch HS1 is driven by a driver circuit 108, the driver circuit 108 being supplied with a voltage V from a power supply node 109 boot1 Power supply and reception of buck PWM control signal PWM buck The low side switch LS1 is driven by a driver circuit 110, the driver circuit 110 being driven by a voltage V drv Power supply and reception of buck PWM control signal PWM buck Complementary signals of (2)The converter 10 comprises a converter arranged to provide an output voltage V out Output node 112 of (1) and a lifterSupply ground voltage V gnd A second half-bridge circuit (e.g., a boost half-bridge) between ground nodes 104. The second half-bridge circuit comprises a second high-side switch HS2 arranged between the output node 112 and a second intermediate (switch) node 114, and a second low-side switch LS2 arranged between the intermediate node 114 and the ground node 104. The high-side switch HS2 is driven by a driver circuit 116, the driver circuit 116 being supplied with a voltage V from a power supply node 117 boot2 Providing and receiving a boost PWM control signal PWM boost The low side switch LS2 is driven by a driver circuit 118, the driver circuit 118 being driven by a voltage V drv Providing and receiving a boost PWM control signal PWM boost Is added to the signal of the (b). Switches HS1, LS1, HS2 and LS2 may include (e.g., consist of) n-channel metal oxide semiconductor (NMOS) transistors, such as power NMOS transistors. An inductive element L (e.g., an inductor, possibly external to the integrated circuit of converter 10) may be disposed between half-bridge intermediate nodes 106 and 114 to provide a full-bridge switching structure. The driver circuits 108, 110, 116, and 118 receive respective PWM control signals (e.g., activation signals) from the logic circuit 120, the logic circuit 120 being configured to control operation of the DC-DC converter 10 (e.g., to modulate the control signals PWM) buck And PWM boost And the duty cycle of its complement signal, so as to generate an output voltage V having a desired DC value out ). Input capacitor C in May be disposed between the input node 102 and the ground node 104 (e.g., external to the integrated circuit of the converter 10). Output capacitor C out May be disposed between the output node 112 and the ground node 104 (e.g., external to the integrated circuit of the converter 10).
Thus, buck-boost DC-DC converter 10 illustrated in fig. 1 may be understood as a cascade arrangement of a "pure" buck converter (including switches HS1 and LS 1) and a "pure" boost converter (including switches HS2 and LS 2) that share an inductive component L disposed between their intermediate nodes 106 and 114.
Although increasing the architecture complexity relative to a pure buck converter or a pure boost converter, buck-boost converters may be used at V out ≈V in Operation is facilitated and may also operate as a pure buck or pure boost converter depending on (transient) system requirements. In particular, for a buck-boost converter as shown in fig. 1, three modes of operation may be identified.
In a proper way for V out ≈V in In a first mode of operation (buck-boost mode), the two half-bridges are in a corresponding signal PWM buck And PWM boost Under control of (typically at the same frequency) and generates a current I in the inductor L L The current I L With a four-phase distribution as illustrated in the timing diagram of fig. 2. Input voltage V in And output voltage V out The ratio between them depends on the signal PWM driving the two half-bridges buck And PWM boost Duty ratio D of (2) buck And D boost ：V out ＝D buck /D boost *V in 。
In a proper way for V out <V in In the second mode of operation (buck mode), only the buck half-bridge (including switches HS1, LS 1) is operated in signal PWM buck While the boost operating half-bridge (comprising switches HS2, LS 2) remains in the high side switching state, i.e. the high side switch HS2 is always ON (ON) and the low side switch LS2 is always OFF (OFF). This operation generates a current I in the inductor L L Having a two-phase distribution as illustrated in the timing diagram of fig. 3. Input voltage V in And output voltage V out The ratio between them depends at least as a first approximation on the signal PWM driving the first half-bridge HS1, LS1 buck Duty ratio D of (2) buck ：V out ＝D buck *V in 。
In a proper way for V out >V in In the third operating mode (boost mode) of (i) only the boost operating half-bridge (including switches HS2, LS 2) is switched under control of the signal PWM boost, while the buck operating half-bridge (including switches HS1, LS 1) remains in the high side switching state, i.e. the high side switch HS1 is always ON (ON) and the low side switch LS1 is always OFF (OFF). This operation generates a current I in the inductor L L Having a two-phase distribution as illustrated in the timing diagram of fig. 4. Input voltage V in And output voltage V out The ratio between them depends at least as a first approximation on the signal PWM driving the second half-bridge HS2, LS2 boost Duty ratio D of (2) boost ：V out ＝V in /D boost 。
The architecture of the power switching stage of the DC-DC converter can be designed to improve the converter power efficiency while maintaining a low silicon area footprint. In this context, as illustrated in fig. 1, the low-side switches LS1 and LS2 are typically implemented as n-channel MOS (NMOS) power transistors driven by driver circuits 110 and 118, the driver circuits 110 and 118 being supplied with a supply voltage V typically available within a semiconductor chip drv (referred to as the ground voltage V at node 104) gnd ). The high-side switches HS1 and HS2 operating at a higher voltage can in principle be implemented as p-channel MOS (PMOS) power transistors. However, the resistance of PMOS transistors is typically three to five times higher than that of NMOS transistors having the same area, so that implementing high-side switches HS1 and HS2 as PMOS transistors will result in a much higher area footprint in order to achieve similar performance. Therefore, as shown in fig. 1, the high-side switches HS1 and HS2 may also be implemented as NMOS transistors, so that the area of the power switching stage of the DC-DC converter 10 may be kept low and the efficiency may be improved. However, this solution depends on the implementation of the high-side driver circuits 108 and 116, the reference voltages (or floating grounds) of the high-side driver circuits 108 and 116 need to track the voltage V at the intermediate node 106 or 114 of the respective half-bridge SW1 Or V SW2 (i.e., the voltage V at the floating ground tracking node 106 of the driver circuit 108) SW1 While the floating ground of driver circuit 116 tracks voltage V at node 114 SW2 )。
As shown in fig. 5, the DC-DC converter 10 may thus include a voltage level V configured to be derived from the voltage levels at nodes 106 and 114, respectively SW1 And V SW2 The generation of the supply voltage V for the driver circuits 108 and 116 begins boot1 And V boot2 Is provided. Voltage V boot1 Can be compared with voltage V SW1 (at least) an amount V higher drv And a voltage V boot2 Can be compared with voltage V SW2 (at least) an amount V higher drv . In addition, the power supply nodes 109 and 117 are capable of providing a sufficient amount of charge to charge the gate capacitances of the respective high-side switches HS1 and HS2 via the respective driver circuits 108 and 116. Thus, the first bootstrap capacitor C B1 (e.g., an off-chip discrete capacitor) may be coupled between node 106 and power supply node 109, and a second bootstrap capacitance C B2 (e.g., off-chip discrete capacitors) may be coupled between node 114 and power supply node 117. Capacitor C B1 And C B2 May have a large capacitance, for example equal to or higher than 100nF.
Capacitor C B1 And C B2 Can be charged in a controlled manner in order to generate the desired supply voltage V boot1 And V boot2 And provides the correct voltages on the high side driver circuits 108 and 116. Thus, the DC-DC converter 10 may include a voltage source coupled at node 109 and providing a reference voltage V ref First bootstrap circuit D between nodes 500 of (c) B1 (illustrated in fig. 5 as a diode, but possibly implemented as a switch in alternative embodiments), and coupled at node 117 and providing a reference voltage V ref Second bootstrap circuit D between nodes 500 of (c) B2 (illustrated in fig. 5 as a diode, but possibly implemented as a switch in alternative embodiments), wherein the reference voltage V ref Is equal to or higher than the supply voltage V drv 。
Bootstrap circuit D B1 And D B2 Configured to pair the capacitor C according to the timing of the corresponding half-bridge circuit B1 And C B2 And (5) charging. In particular, during the low-side ON phase, the half-bridge intermediate node (106 or 114) is driven to ground voltage V via the respective low-side switch (LS 1 or LS 2) gnd Resulting in a corresponding bootstrap capacitance (C B1 Or C B2 ) Via the reference voltage V ref ≥V drv The corresponding bootstrap circuit (D B1 Or D B2 ) Is charged. During the high side interface phase, a bootstrap capacitor (C B1 Or C B2 ) It should be possible to provide sufficient energy (charge) to power up the respective driver circuit (108 or 116) and turn on the respective high-side switch (HS 1 or HS 2) without passing through the respective bootstrap circuit (D B1 Or D B2 ) To node 500 leakage current. Therefore, bootstrap circuit D B1 And D B2 One possible implementation of (a) may rely on corresponding diodes arranged to be turned on (only) from node 500 to nodes 109 and 117, respectively. Bootstrap circuit D B1 And D B2 May rely on a pair of switches D driven in synchronization with the switching activity of the full bridge architecture B1 And D B2 (e.g. switch D B1 Is turned on during the on phase of the low-side switch LS1 and is not turned on during the on phase of the high-side switch HS1, and switch D B2 Is turned on during the on phase of the low-side switch LS2 and is not turned on during the on phase of the high-side switch HS 2).
Bootstrap circuit C disclosed with reference to FIG. 5 B1 ，D B1 ，C B2 ，D B2 May not be compatible with operation of buck-boost DC-DC converter 10 in a pure buck mode during which high-side switch HS2 remains always ON (ON) and in a pure boost mode during which high-side switch HS1 remains always ON (ON). In fact, in these modes of operation, the bootstrap capacitance coupled to the half-bridge that is driven statically (i.e., not switched) will not be recharged by the corresponding bootstrap circuit (or will be charged only once when the converter 10 is started up). Even if the statically driven half-bridge does not switch, the corresponding bootstrap capacitor will discharge during time (e.g. due to current leakage effects), causing the corresponding high-side switch to turn off after a certain time interval.
For example, FIG. 6 is a diagram of capacitance C when the operation of DC-DC converter 10 transitions from buck mode or buck-boost mode (interval T1) to pure boost mode (interval T2) B1 Voltage V across (i.e. between nodes 109 and 106) cboot1 Is provided, is a timing diagram of an example of a possible behavior of (a). In the pure boost mode, bootstrap circuit D B1 Is disabled (i.e. it is not on) because of the applied voltage V ref And voltage V boot1 The following conditions:
V ref <V boot1 ＝V SW1 +V drv ＝V in +V drv
thus, the capacitor C B1 Due to leakageAnd discharge.
Similarly, FIG. 7 is a diagram of capacitor C when the operation of DC-DC converter 10 transitions from boost mode or buck-boost mode (interval T1) to pure buck mode (interval T2) B2 Voltage V across (i.e. between nodes 117 and 114) cboot2 Is provided, is a timing diagram of an example of a possible behavior of (a). In the pure buck mode, bootstrap circuit D B2 Is disabled (i.e. it is not on) because of the applied voltage V ref And voltage V boot2 The following conditions:
V ref <V boot2 ＝V SW2 +V drv ＝V out +V drv
thus, the capacitor C B2 Discharge due to leakage.
Make bootstrap circuit C B1 ，D B1 ，C B2 ，D B2 Possible solutions compatible with operation of buck-boost DC-DC converter 10 in both buck-only and boost-only modes rely on coupling to capacitor C B1 And C B2 As illustrated in the circuit diagram of fig. 8, in addition to the "initiate refresh" circuit 80. The enabling refresh circuit 80 is configured to bootstrap capacitor C by relying on switching activity at another intermediate node 114 (or 106) when there is no switching activity at the respective intermediate node 106 (or 114) B1 (or C) B2 ) Maintain a proper voltage V cboot1 (or V) cboot2 ). Basically, since in the pure buck mode (or boost mode) the switching half-bridge HS1, LS1 (or HS2, LS 2) has its bootstrap capacitor C "active B1 (or C) B2 ) To be higher than the other bootstrap capacitance C B2 (or C) B1 ) Voltage V at boot2 (or V) boot1 ) Voltage V of (2) boot1 (or V) boot2 ) Charging, thus "active" bootstrap capacitance C B1 (or C) B2 ) Can be used for another bootstrap capacitor C B2 (or C) B1 ) And (5) charging. Document US 2019/032687 A1 is an example of a buck-boost converter comprising a bootstrap voltage refresh circuit.
FIG. 9 is an exemplary circuit diagram of buck-boost DC-DC converter 10 according to one or more embodiments, including according to the description with reference to FIG. 8A bootstrap refresh circuit operating in principle. It should be noted that for ease of illustration, some components of converter 10 may not be visible in fig. 9 (e.g., an (external) capacitor C coupled to nodes 102 and 112, respectively in And C out And a bootstrap circuit D coupled to nodes 109 and 117, respectively B1 And D B2 )。
As shown in fig. 9, one or more embodiments may include a first switch M1 and a second switch M2 connected in direct series between node 109 and node 117. For example, the first switch M1 may be directly connected between the node 109 and the intermediate node 902, while the second switch M2 may be directly connected between the node 117 and the intermediate node 902. The switches M1, M2 may comprise (e.g., consist of) PMOS transistors; for example, the first PMOS transistor M1 may have a source terminal coupled to the node 109 and a drain terminal coupled to the node 902, and the second PMOS transistor M2 may have a source terminal coupled to the node 117 and a drain terminal coupled to the node 902, such that during operation, the body diodes (not visible in fig. 9) of the transistors M1 and M2 are arranged in opposite directions (e.g., "back-to-back").
The diode 904 may be coupled between the node 902 and the ground node 104, conducting electricity from the node 104 toward the node 902 (e.g., having an anode terminal coupled to the ground node 104 and a cathode terminal coupled to the intermediate node 902). Diode 904 may operate as a clamp circuit to avoid uncontrolled negative voltage drift of node 902 when the voltage refresh circuit is inactive (e.g., open).
When the DC-DC converter 10 is operating in either a pure buck mode or a pure boost mode, the switches M1, M2 may be connected to the signal PWM buck Or PWM boost The synchronous mode (as discussed further below) is activated to bootstrap capacitor C B1 Or C B2 Charging (e.g., transferring charge from one bootstrap capacitor to another).
Accordingly, one or more embodiments may advantageously not include any diodes disposed between nodes 109 and 117. The absence of a diode in the current path between nodes 109 and 117 may result in a lower silicon area of converter circuit 10, and/or result in bootstrap capacitanceC B1 And C B2 A wide voltage operating range can be used to transfer energy from one to the other to each other. For example, in the known solution disclosed in the previously cited document US 2019/03266817 A1, it comprises a diode in the current path between two bootstrap capacitors, the voltage V across one bootstrap capacitor high Must be greater than the voltage V across the other bootstrap capacitor low At least a quantity V corresponding to the threshold voltage of the diode diode (V high ≥V low +V diode ) To allow charge transfer from one bootstrap capacitor to the other. Conversely, in one or more embodiments as shown in FIG. 9, if the voltage V across a bootstrap capacitor high Higher than the voltage V across the other bootstrap capacitor low (V high ≥V low ) Then a bootstrap capacitance (C B1 Or C B2 ) To another bootstrap capacitor (C respectively B2 Or C B1 ) Is a charge transfer of (a). This results in a voltage at the input voltage V in And/or output voltage V out The uniformity of the voltage across the recharged bootstrap capacitor is improved at the varying values of (a), which in turn facilitates more uniform operation of the driver circuits 108, 116.
In one or more embodiments, switches M1 and M2 (as discussed further below) may be controlled to prevent bootstrap capacitance coupled to the "stable" half-bridge from discharging via the low-side switches of the "switching" half-bridge. This may be achieved by opening (e.g., turning off) switches M1 and M2 when the low side switches of the "switch" half bridge are on. Specifically, during pure buck mode operation, when the low side buck switch LS1 is on (e.g., on), the switches M1 and M2 may be off (e.g., off). Similarly, during pure boost mode operation, when the low side boost switch LS2 is on (e.g., on), the switches M1 and M2 may be off (e.g., off).
Additionally, in one or more embodiments, the switches M1, M2 (e.g., PMOS transistors) may be sized to have a bootstrap capacitance C that is prevented in the on state B1 And C B2 An overcharged resistance value. In practice, the switches M1, M2 may be in accordance with the logic of the respective comparator circuit coupled theretoBootstrap capacitor C B1 And C B2 The voltage sensed across it. The comparator circuit may operate in a high voltage domain and may detect information sensed (i.e., capacitance C B1 And C B2 Is affected by latency in the range of transmission from the high voltage domain to the low voltage domain via a dedicated level shifter circuit. During such a wait time, the bootstrap capacitor being recharged (i.e., the bootstrap capacitor coupled to the "stable" half-bridge) may continue to be charged (e.g., proportionally) depending on the voltage Δv across the switches M1, M2 (i.e., the voltage sensed between nodes 109 and 117). To avoid overcharging the bootstrap capacitance, the threshold voltage of the comparator and the on-resistance values of the switches M1, M2 may be selected accordingly.
In one or more embodiments, since the DC-DC converter 10 may be at the input voltage V in And/or output voltage V out The switches M1, M2 may comprise (e.g. consist of) switches with variable and selectable resistances. Thus, the on-resistances of the switches M1, M2 may be selected according to the voltage Δv sensed between the nodes 109 and 117. For example, each switch M1, M2 may comprise a plurality of PMOS transistors connected in parallel, wherein each parallel connected transistor is selectively activatable to provide a certain resistance between nodes 109 and 117. One or more parallel connected transistors within the switches M1, M2 may be selected according to the voltage Δv between the nodes 109 and 117. For example, across bootstrap capacitance C B1 And C B2 Voltage V of (2) cboot1 And V cboot2 Under the assumption of approximately the same, the voltage DeltaV between nodes 109 and 117 may be approximately equal to the input voltage V at node 102 in And the output voltage V at node 112 out The difference between: deltaV= |V in -V out Graph I. Thus, in one or more embodiments, the resistance values of the switches M1, M2 (e.g., the number of activated parallel-connected PMOS transistors) may be based on V in And V out Is selected (directly sensed or indirectly determined).
The principle of operation discussed above will be further explained with reference to the circuit diagram of fig. 9.
As previously discussed, a DC-DC buck-boost converter 10 in accordance with one or more embodiments may include a logic circuit 120, the logic circuit 120 configured to generate a control signal PWM for the driver circuits 108, 110, 116, and 118 by generating the control signal PWM buck PWM (pulse Width modulation) boost (and its complement) to control the operation of the DC-DC converter 10 so as to produce an output voltage V having a desired DC value (e.g., as a function of the output from the control loop of the converter 10) out . The logic circuit 120 may receive a first control signal B0 and a second control signal BU, the first control signal B0 instructing the converter 10 to operate in the boost mode when the first control signal B0 is asserted (e.g., b0= '1'), and the second control signal BU instructing the converter 10 to operate in the buck mode when the second control signal BU is asserted (e.g., bu= '1'). If both signals BO and BU are asserted, converter 10 operates in buck-boost mode.
As illustrated in fig. 9, one or more embodiments may include a control circuit configured to sense the bootstrap capacitance C B1 ，C B2 The voltages across the terminals and, depending on the sensed voltages, an activation signal C is generated for the switches M1, M2. In particular, capacitor C B1 The voltage across the capacitor may be equal to a first threshold V th1 Comparing, capacitance C B2 The voltage across the capacitor may be equal to the second threshold V th2 Comparison (possible V) th1 ＝V th2 )。
For example, one or more embodiments may include a voltage-to-current (V2I) converter circuit 906 1 The voltage-to-current (V2I) converter circuit 906 1 Coupled to capacitor C B1 And is configured to generate a representative capacitance C B1 Voltage V at both ends cboot1 For example, proportional to the output current of (a) the (b). From V2I converter circuit 906 1 May be injected into a resistor R1 coupled to the ground node 104 to generate a voltage V representative of (e.g., proportional to) the voltage V cboot1 Voltage signal V of (2) 1 . Comparator circuit 908 1 A voltage signal V may be received at a first (e.g., inverting) input (e.g., a comparator with hysteresis) 1 And at a second (e.g., non-inverting)) Receiving a threshold signal V at an input th1 And may generate the output signal C1 based on the comparison. For example, when V 1 <V th1 When, signal C1 (e.g., c1= '1') may be asserted.
Similarly, one or more embodiments may include a voltage-to-current (V2I) converter circuit 906 2 The voltage-to-current (V2I) converter circuit 906 2 Coupled to capacitor C B2 And is configured to generate a representative capacitance C B2 Voltage V at both ends cboot2 For example, proportional to the output current of (a) the (b). From V2I converter circuit 906 2 May be injected into a resistor R2 (e.g., equal to R1) coupled to the ground node 104 to produce a voltage V cboot2 (e.g. with voltage V) cboot2 Proportional) voltage signal V 2 . Comparator circuit 908 2 A voltage signal V may be received at a first (e.g., inverting) input (e.g., a comparator with hysteresis) 2 And receives a threshold signal V at a second (e.g., non-inverting) input th2 And an output signal C2 depending on the comparison can be generated. For example, when V 2 <V th2 When, signal C2 may be asserted (e.g., c2= '1').
The (combinational) logic circuit 910 receives the signals C1, C2, BO and BU and generates the output activation signal C according to the following logic: if signal B0 is asserted (e.g., b0= '1') and signal BU is de-asserted (e.g., bu= '0'), then c=c1 (i.e., circuit 910 passes signal C1 to the output); if signal B0 is deasserted (e.g., b0= '0') and signal BU is asserted (e.g., bu= '1'), then c=c2 (i.e., circuit 910 passes signal C2 to the output); if signal BO is asserted and signal BU is asserted (e.g., bo= '1' and bu= '1'), then c= '0'.
More generally, the logical operation of the circuit 910 described above results in: if the converter 10 is operating in a pure boost mode, then when capacitor C B1 Voltage V at both ends cboot1 Below a certain threshold (i.e. when in capacitance C B1 Upon detection of an under-voltage condition), switches M1 and M2 may be activated; if the converter 10 is operating in a pure buck mode, then capacitor C is present B2 Electric at both endsPressure V cboot2 Below a certain threshold (i.e. when in capacitance C B2 Upon detection of an under-voltage condition), switches M1 and M2 may be activated; and if converter 10 is operating in buck-boost mode, switches M1 and M2 may not be activated.
Note that the capacitance C B1 And C B2 Voltage V at both ends cboot1 And voltage V cboot2 Involving floating ground nodes 106 and 114 (i.e., in the high voltage portion of converter 10) and providing V2I converter circuitry 906 1 And 906 2 Helping to combine these voltages with a threshold V in the low voltage portion of the converter 10 th1 And V th2 A comparison is made allowing the use of a low voltage comparator 908 1 And 908 2 . It should be appreciated that different embodiments may include different voltage sensing structures configured to produce the indicated bootstrap capacitance C B1 And C B2 Voltage V at both ends cboot1 And V cboot2 Signals C1 and C2 of (C). For example, one or more embodiments may include two comparator circuits implemented in a floating voltage section (i.e., referenced to switch nodes 106 and 114, respectively) and configured to generate a voltage according to capacitance C B1 Voltage V on cboot1 And capacitor C B2 Voltage V on cboot2 Is provided, the corresponding logic signal of the direct sensing of (a). Such logic signals may be fed to respective level shifter circuits to generate logic signals C1 and C2 for logic circuit 910.
As illustrated in fig. 9, one or more embodiments may include a circuit 912, the circuit 912 configured to rely on an input voltage V when in an on state in And output voltage V out The difference between them determines the appropriate resistance of the switches M1, M2. In particular, if each switch M1, M2 includes a plurality of MOS transistors connected in parallel, the circuit 912 may be configured to determine the number of such parallel-connected transistors to be activated simultaneously. Thus, circuit 912 may generate an output signal D that represents the number of transistors to activate. For example, signal D may comprise an N-bit signal, where N is the number of parallel transistors included in each of switches M1 and M2, with each bit of signal D being used to control the phase in switches M1, M2Should be a transistor.
As previously described, the resistance of the switches M1, M2 may be substantially dependent on the input voltage V in And output voltage V out The difference is selected. For example, in one or more embodiments, the circuit 912 may be configured to provide the voltage to V in accordance with in And V is equal to out The difference between them is related to a look-up table of a certain number of transistors that have to be activated to determine the number of transistors to be activated. In one or more embodiments, the output voltage V out Is generally known within the scope set by the application, and may need to be collected about the input voltage V in Is a piece of information of (a).
In one or more embodiments, the input voltage V in Can be sensed by a dedicated voltage sensor circuit, can be converted to a digital value by an analog-to-digital (A/D) converter, and can be ultimately matched with the output voltage V out A comparison is made.
In one or more embodiments, to avoid implementing a dedicated input voltage sensor and/or a dedicated A/D converter, the output voltage V may be relied upon by out The sum of the values of (2) depends on the signal PWM buck Duty ratio D of (2) buck Value and/or signal PWM boost Duty ratio D of (2) boost Indirectly determined in relation to the input voltage V in Because of D buck ＝V out /V in And D is boost ＝V in /V out . Thus, in one or more embodiments, the output voltage V may be based on out And input voltage V in The resistance value of the switches M1, M2 (e.g., the number of parallel PMOS transistors to be activated) is selected. Duty cycle D buck And/or D boost The value of (2) may be determined, for example, by means of a "fast" clock signal that conventionally drives a pair of digital counters that count the signal PWM buck And PWM boost Counting the actual duration of the high side access phase. Once D is measured buck And/or D boost V can be set in Calculated indirectly as V in ＝V out /D buck And/or V in ＝V out /D boost 。
In one or more embodiments, the signal D generated by the circuit 912 can be fed to a corresponding level shifter circuit 914 1 ，914 2 Level shifter circuit 914 1 ，914 2 The voltage level of signal D is shifted from the low voltage portion of the converter 10 to the floating ground portion. Each bit of the N-bit signal D may be fed to a respective voltage shifter circuit 914 1 ，914 2 . Similarly, the signal C generated by the logic circuit 910 may be fed to a respective level shifter circuit 916 1 ，916 2 Level shifter circuit 916 1 ，916 2 The voltage level of signal C is shifted from the low voltage portion of the converter 10 to the floating ground portion. Similarly, signal PWM generated by logic circuit 120 buck And PWM boost May be fed to a corresponding level shifter circuit 918 1 ，918 2 Level shifter circuit 918 1 ，918 2 PWM of the signal buck And PWM boost Is shifted from the low voltage portion of the converter 10 to the floating ground portion.
In one or more embodiments, each of the parallel-connected transistors of switches M1 and M2 may be received at a respective logic gate 920 1 ，920 2 As a combination of various control signals. In particular, each transistor in switches M1, M2 may be coupled to an output of a respective NAND logic gate that combines multiple (e.g., four) input signals. To each NAND logic gate 920 1 ，920 2 May be the corresponding high side communication signal generated by PWM generator circuit 120 (i.e., for gate 920) 1 Signal PWM of (2) buck And for door 920 2 Signal PWM of (2) boost ) Which indicates that the respective high-side switch (HS 1 or HS 2) is expected to be active. To each NAND logic gate 920 1 ，920 2 May be the corresponding Vgs ON signals generated by driver circuits 108 and 116 (i.e., from driver 108 for gate 920) 1 And an output signal B1 from the driver for gate 920 2 Indicating that the respective high-side switch (HS 1 or HS 2) is actually activated by the respective driver circuit. To each NAND logic gate 920 1 ，920 2 May be a signal C generated by the circuit 910 indicating a corresponding bootstrap capacitance (C B1 Or C B2 ) Will be charged. To each NAND logic gate 920 1 ，920 2 May be a bit of signal D generated by circuit 912 indicating that the corresponding PMOS transistor in switch M1 or M2 is to be activated.
The operation of the DC-DC converter 10 illustrated in fig. 9 may be further understood with reference to the block diagram of fig. 10. As shown in fig. 10, a first operation step 1000 may include determining a current operation mode of the converter 10, i.e., a buck mode (output O1) or a boost mode (output O2). In the case of a buck mode of operation (e.g., bu= '1'), step 1002 follows 1 May include enabling comparator 908 2 (and possibly disable comparator 908) 1 ) Because the capacitance C must be monitored B2 Is set, is provided. Step 1004 follows 1 May include determining the number of transistors connected in parallel in the switches M1, M2 to be activated (i.e., setting the value of the N-bit signal D). Step 1006 1 And may then include checking the capacitance C B2 Voltage V at both ends cboot2 Whether or not it is below a certain threshold value and checking the signal PWM buck And B1 is asserted (i.e., checks whether the high-side switch HS1 is on). As step 1006 1 As a result of a positive result of (a), in a subsequent step 1008 1 In which the bootstrap capacitor C can be refreshed by activating the switches M1, M2 (according to the value of the signal D) B2 . As step 1006 1 As a result of the negative result of (a), the checking step 1006 may be repeated as long as the converter 10 remains in the step-down operation mode 1 . Similarly, in the case of a boost mode of operation (e.g., bo= '1'), step 1002 following step 1000 2 May include enabling comparator 908 1 (and possibly disable comparator 908) 2 ) Because the capacitance C must be monitored B1 Is set, is provided. Step 1004 follows 2 May include determining parallel-connected ones of the switches M1, M2 to be activatedThe number of body tubes (i.e., the value of the N-bit signal D is set). Next step 1006 2 May include checking the capacitance C B1 Voltage V at both ends cboot1 Whether or not it is below a certain threshold value and checking the signal PWM boost And B2 is asserted (i.e., checks whether the high-side switch HS2 is on). As step 1006 2 As a result of a positive result of (a), in a subsequent step 1008 2 In which the bootstrap capacitor C can be refreshed by activating the switches M1, M2 (according to the value of the signal D) B1 . As step 1006 2 As a result of the negative result of (a), the checking step 1006 may be repeated as long as the converter 10 remains in the step-up operation mode 2 。
In the case where the converter 10 operates in buck-boost mode (e.g., bu= '1' and bo= '1'), the comparator 908 is within a range where the bootstrap capacitance does not need to be refreshed 1 And 908 2 None of which is activated and the refresh circuitry is inactive (e.g., disabled).
Without prejudice to the underlying principles, the details and the embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the scope of the protection.
Claims (20)
1. A buck-boost converter circuit comprising:
a first half-bridge circuit disposed between an input node and a ground node, the input node configured to receive an input voltage, the first half-bridge circuit comprising a first high-side switch disposed between the input node and a first switch node, and a first low-side switch disposed between the first switch node and the ground node;
A second half-bridge circuit disposed between an output node and the ground node, the output node configured to provide an output voltage, the second half-bridge circuit including a second high-side switch disposed between the output node and a second switch node, and a second low-side switch disposed between the second switch node and the ground node;
a control circuit configured to receive a first control signal that, when asserted, instructs the buck-boost converter circuit to operate in a buck mode and a second control signal that, when asserted, instructs the buck-boost converter circuit to operate in a boost mode, the control circuit further configured to generate a buck pulse width modulation control signal and a boost pulse width modulation control signal;
a first high-side driver circuit configured to receive the buck pulse width modulation control signal and to drive the first high-side switch in accordance with the buck pulse width modulation control signal, the first high-side driver circuit being biased between a first high-side supply voltage node and the first switch node;
a second high-side driver circuit configured to receive the boost pulse width modulation control signal and to drive the second high-side switch in accordance with the boost pulse width modulation control signal, the second high-side driver circuit being biased between a second high-side supply voltage node and the second switch node;
A first bootstrap circuit configured to selectively conduct from a reference voltage node toward the first high-side supply voltage node;
a second bootstrap circuit configured to selectively conduct from the reference voltage node toward the second high-side supply voltage node;
a first voltage sensing circuit configured to sense a voltage between the first high-side supply voltage node and the first switching node and assert a first activation signal in response to the sensed voltage being below a first threshold;
a second voltage sensing circuit configured to sense a voltage between the second high-side supply voltage node and the second switching node and assert a second activation signal in response to the sensed voltage being below a second threshold;
at least one charge transfer switch directly connected between the first high-side supply voltage node and the second high-side supply voltage node; and
bootstrap refresh control circuitry configured to close the at least one charge transfer switch in response to:
the first control signal is asserted, the first high-side switch is turned on and the second activation signal is asserted, or
The second control signal is asserted, the second high-side switch is turned on and the first activation signal is asserted.
2. The buck-boost converter circuit of claim 1, wherein the first high-side switch, the first low-side switch, the second high-side switch, and the second low-side switch comprise n-channel MOS transistors.
3. The buck-boost converter circuit of claim 1, wherein the at least one charge transfer switch includes at least one p-channel MOS transistor.
4. The buck-boost converter circuit of claim 1, wherein the at least one charge transfer switch includes a first charge transfer switch directly connected between an intermediate node of a charge transfer path and the first high-side supply voltage node, and a second charge transfer switch directly connected between the intermediate node of the charge transfer path and the second high-side supply voltage node.
5. The buck-boost converter circuit of claim 1, wherein the at least one charge transfer switch comprises at least one switch having a selectable resistance value, and wherein the bootstrap refresh control circuitry is further configured to:
Determining a voltage difference between the first high-side supply voltage node and the second high-side supply voltage node; and
the resistance value of the at least one charge transfer switch is set according to the determined voltage difference, wherein a higher resistance value of the at least one charge transfer switch is set in response to a higher value of the determined voltage difference.
6. The buck-boost converter circuit of claim 5, wherein the at least one charge transfer switch includes a plurality of selectively activatable switches connected in parallel, and wherein the bootstrap refresher control circuitry is configured to generate respective control signals for activating the selectively activatable switches connected in parallel as a function of the determined voltage difference, wherein fewer switches connected in parallel are activated in response to the determined increased value of the voltage difference.
7. The buck-boost converter circuit of claim 5, wherein the bootstrap refresher control circuitry is configured to determine the voltage difference between the first high-side supply voltage node and the second high-side supply voltage node as a difference between the input voltage and the output voltage.
8. The buck-boost converter circuit of claim 5, wherein the bootstrap refresher control circuitry is configured to determine the voltage difference between the first high-side supply voltage node and the second high-side supply voltage node as a function of the output voltage and at least one of a duty cycle of the buck pulse width modulation control signal and a duty cycle of the boost pulse width modulation control signal.
9. The buck-boost converter circuit of claim 1, wherein:
the first voltage sensing circuit includes:
a first voltage-to-current converter circuit configured to generate a first output current indicative of a voltage between the first high-side supply voltage node and the first switching node;
a first resistor coupled to a ground node and arranged to receive the first output current to generate a first voltage signal indicative of a voltage between the first high-side supply voltage node and the first switch node; and
a first comparator configured to compare the first voltage signal to the first threshold and assert the first activation signal in response to the first voltage signal being below the first threshold; and
The second voltage sensing circuit includes:
a second voltage-to-current converter circuit configured to generate a second output current indicative of a voltage between the second high-side supply voltage node (117) and the second switching node;
a second resistor coupled to the ground node and arranged to receive the second output current to generate a second voltage signal indicative of a voltage between the second high-side supply voltage node and the second switch node; and
a second comparator configured to compare the second voltage signal to the second threshold and assert the second activation signal in response to the second voltage signal being below the second threshold.
10. The buck-boost converter circuit of claim 1, wherein:
the first bootstrap circuit includes a semiconductor junction having an anode terminal coupled to the reference voltage node and a cathode terminal coupled to the first high-side supply voltage node; and
the second bootstrap circuit includes a semiconductor junction having an anode terminal coupled to the reference voltage node and a cathode terminal coupled to the second high-side supply voltage node.
11. The buck-boost converter circuit of claim 1, wherein:
the first bootstrap circuit includes a first bootstrap switch disposed between the reference voltage node and the first high-side supply voltage node;
the second bootstrap circuit includes a second bootstrap switch disposed between the reference voltage node and the second high-side supply voltage node; and
the buck-boost converter further includes control circuitry configured to:
closing the first bootstrap switch in response to the first low-side switch being on and the first high-side switch not being on, and
the second bootstrap switch is closed in response to the second low-side switch being on and the second high-side switch not being on.
12. A method of operating the buck-boost converter circuit of claim 1, the method comprising:
receiving an input voltage at an input node;
receiving, at a control circuit, a first control signal that, when asserted, instructs the buck-boost converter circuit to operate in a buck mode and a second control signal that, when asserted, instructs the buck-boost converter circuit to operate in a boost mode;
Generating the buck pulse width modulation control signal and the boost pulse width modulation control signal at the control circuit;
receiving the buck pulse width modulation control signal at a first high-side driver circuit and driving a first high-side switch in accordance with the buck pulse width modulation control signal;
receiving the boost pulse width modulation control signal at a second high side driver circuit and driving a second high side switch in accordance with the boost pulse width modulation control signal;
sensing, by a first voltage sensing circuit, a voltage between a first high-side supply voltage node and a first switching node, and asserting a first activation signal in response to the sensed voltage being below a first threshold;
sensing, by the second voltage sensing circuit, a voltage between the second high-side supply voltage node and the second switching node, and asserting a second activation signal in response to the sensed voltage being below a second threshold; and
closing at least one charge transfer switch in response to:
the first control signal is asserted, the first high-side switch is turned on and the second activation signal is asserted, or
The second control signal is asserted, the second high-side switch is turned on and the first activation signal is asserted.
13. A buck-boost converter circuit comprising:
a buck-boost controller comprising:
a first voltage sensing circuit configured to be coupled to a boost switch driver power supply node of the buck converter circuit;
a second voltage sensing circuit configured to be coupled to a boost switch driver power supply node of the boost converter circuit;
a transfer switch controller coupled to the first voltage sensing circuit and the second voltage sensing circuit and configured to be coupled to at least one charge transfer switch coupled between the boost switch driver power supply node of the buck converter circuit and the boost switch driver power supply node of the boost converter circuit, the transfer switch controller configured to close the at least one charge transfer switch in response to:
the high-side switch of the buck converter circuit is on, the second voltage sense circuit indicates that a voltage between the boost switch driver power supply node of the boost converter circuit and an output node of the high-side switch of the boost converter circuit is less than a first predetermined threshold, and the buck-boost converter is in a buck conversion mode; and
The high-side switch of the boost converter circuit is on, the first voltage sense circuit indicates that a voltage between the boost switch driver power supply node of the buck converter circuit and an output node of the high-side switch of the buck converter circuit is less than a second predetermined threshold, and the buck-boost converter is in a boost conversion mode.
14. The circuit of claim 13, wherein:
the at least one charge transfer switch includes a plurality of charge transfer switches connected in parallel; and
the transfer switch controller is further configured to:
activating a first number of the plurality of charge transfer switches when the first voltage sensing circuit and the second voltage sensing circuit indicate that a voltage difference between a voltage of a boost switch driver power supply node of the boost converter circuit and a voltage of a boost switch driver power supply node of the buck converter circuit is a first value, and
when the first voltage sensing circuit and the second voltage sensing circuit indicate that a voltage difference between a voltage of a boost switch driver power supply node of the boost converter circuit and a voltage of a boost switch driver power supply node of the buck converter circuit is a second value, a second number of charge transfer switches of the plurality of charge transfer switches is activated, wherein the first number is less than the second number and the first value is greater than the second value.
15. The circuit of claim 14, further comprising a plurality of charge transfer switches.
16. The circuit of claim 13, further comprising:
a first half-bridge circuit comprising a high side switch of the buck converter circuit and a low side switch of the buck converter circuit, wherein the high side switch of the buck converter circuit is connected to an input of the buck-boost converter;
a second half-bridge circuit comprising a high side switch of the boost converter circuit and a low side switch of the boost converter circuit, wherein the high side switch of the boost converter circuit is connected to the output of the buck-boost converter;
a first driver circuit having a power supply input coupled to a boost switch driver power supply node of the buck converter circuit, and an output coupled to a control node of the first half-bridge circuit; and
a second driver circuit having a power supply input coupled to a boost switch driver power supply node of the boost converter circuit, and
an output coupled to a control node of the second half-bridge circuit.
17. The circuit of claim 16, further comprising:
the at least one charge transfer switch;
A first capacitor coupled between an output of the first half-bridge circuit and a boost switch driver power supply node of the buck converter circuit; and
a second capacitor is coupled between the output of the second half-bridge circuit and a boost switch driver power supply node of the boost converter circuit.
18. The circuit of claim 13, wherein:
the first voltage sensing circuit includes a first comparator; and
the second voltage sensing circuit includes a second comparator.
19. A method of operating a buck-boost power supply, the buck-boost power supply comprising: a first half-bridge circuit, a first driver circuit coupled to the first half-bridge circuit and a first boost power supply node, a second half-bridge circuit, a second driver circuit coupled to the second half-bridge circuit and a second boost power supply node, and a charge transfer switch coupled between the first boost power supply node and the second boost power supply node, the method comprising:
the buck-boost power supply is operated in buck mode by:
providing a PWM signal to the first half-bridge circuit,
maintaining the high side switch of the second half-bridge circuit on and the low side switch of the second half-bridge circuit off, and
Turning on the charge transfer switch when a voltage between the second boost power supply node and an output of the second half-bridge circuit is below a first threshold; and
operating the buck-boost power supply in a boost mode by:
providing a PWM signal to the second half-bridge circuit,
maintaining the high side switch of the first half-bridge circuit on and the low side switch of the first half-bridge circuit off, and
the charge transfer switch is turned on when a voltage between the first boost power supply node and an output of the first half-bridge circuit is below a second threshold.
20. The method according to claim 19, wherein:
the charge transfer switch has a variable resistance; and
the method further comprises:
decreasing the variable resistance of the charge transfer switch as a voltage difference between the first boost power supply node and the second boost power supply node decreases, and
the variable resistance of the charge transfer switch increases as a voltage difference between the first boost power supply node and the second boost power supply node increases.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310532741.3A CN116545260A (en) | 2023-05-11 | 2023-05-11 | DC-DC converter, chip and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310532741.3A CN116545260A (en) | 2023-05-11 | 2023-05-11 | DC-DC converter, chip and electronic equipment |
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| Publication Number | Publication Date |
|---|---|
| CN116545260A true CN116545260A (en) | 2023-08-04 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310532741.3A Pending CN116545260A (en) | 2023-05-11 | 2023-05-11 | DC-DC converter, chip and electronic equipment |
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| Country | Link |
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| CN (1) | CN116545260A (en) |
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2023
- 2023-05-11 CN CN202310532741.3A patent/CN116545260A/en active Pending
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